0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos4 SoC series common device tree source
0004 *
0005 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 * Copyright (c) 2010-2011 Linaro Ltd.
0008 * www.linaro.org
0009 *
0010 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
0011 * SoCs from Exynos4 series can include this file and provide values for SoCs
0012 * specfic bindings.
0013 *
0014 * Note: This file does not include device nodes for all the controllers in
0015 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
0016 * nodes can be added to this file.
0017 */
0018
0019 #include <dt-bindings/clock/exynos4.h>
0020 #include <dt-bindings/clock/exynos-audss-clk.h>
0021 #include <dt-bindings/interrupt-controller/arm-gic.h>
0022 #include <dt-bindings/interrupt-controller/irq.h>
0023
0024 / {
0025 interrupt-parent = <&gic>;
0026 #address-cells = <1>;
0027 #size-cells = <1>;
0028
0029 aliases {
0030 spi0 = &spi_0;
0031 spi1 = &spi_1;
0032 spi2 = &spi_2;
0033 i2c0 = &i2c_0;
0034 i2c1 = &i2c_1;
0035 i2c2 = &i2c_2;
0036 i2c3 = &i2c_3;
0037 i2c4 = &i2c_4;
0038 i2c5 = &i2c_5;
0039 i2c6 = &i2c_6;
0040 i2c7 = &i2c_7;
0041 i2c8 = &i2c_8;
0042 csis0 = &csis_0;
0043 csis1 = &csis_1;
0044 fimc0 = &fimc_0;
0045 fimc1 = &fimc_1;
0046 fimc2 = &fimc_2;
0047 fimc3 = &fimc_3;
0048 serial0 = &serial_0;
0049 serial1 = &serial_1;
0050 serial2 = &serial_2;
0051 serial3 = &serial_3;
0052 };
0053
0054 pmu: pmu {
0055 compatible = "arm,cortex-a9-pmu";
0056 interrupt-parent = <&combiner>;
0057 status = "disabled";
0058 };
0059
0060 soc: soc {
0061 compatible = "simple-bus";
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 ranges;
0065
0066 clock_audss: clock-controller@3810000 {
0067 compatible = "samsung,exynos4210-audss-clock";
0068 reg = <0x03810000 0x0C>;
0069 #clock-cells = <1>;
0070 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
0071 <&clock CLK_SCLK_AUDIO0>,
0072 <&clock CLK_SCLK_AUDIO0>;
0073 clock-names = "pll_ref", "pll_in", "sclk_audio",
0074 "sclk_pcm_in";
0075 };
0076
0077 i2s0: i2s@3830000 {
0078 compatible = "samsung,s5pv210-i2s";
0079 reg = <0x03830000 0x100>;
0080 clocks = <&clock_audss EXYNOS_I2S_BUS>,
0081 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
0082 <&clock_audss EXYNOS_SCLK_I2S>;
0083 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
0084 #clock-cells = <1>;
0085 clock-output-names = "i2s_cdclk0";
0086 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
0087 dma-names = "tx", "rx", "tx-sec";
0088 samsung,idma-addr = <0x03000000>;
0089 #sound-dai-cells = <1>;
0090 status = "disabled";
0091 };
0092
0093 chipid@10000000 {
0094 compatible = "samsung,exynos4210-chipid";
0095 reg = <0x10000000 0x100>;
0096 };
0097
0098 scu: snoop-control-unit@10500000 {
0099 compatible = "arm,cortex-a9-scu";
0100 reg = <0x10500000 0x2000>;
0101 };
0102
0103 memory-controller@12570000 {
0104 compatible = "samsung,exynos4210-srom";
0105 reg = <0x12570000 0x14>;
0106 };
0107
0108 mipi_phy: video-phy {
0109 compatible = "samsung,s5pv210-mipi-video-phy";
0110 #phy-cells = <1>;
0111 syscon = <&pmu_system_controller>;
0112 };
0113
0114 pd_mfc: power-domain@10023c40 {
0115 compatible = "samsung,exynos4210-pd";
0116 reg = <0x10023C40 0x20>;
0117 #power-domain-cells = <0>;
0118 label = "MFC";
0119 };
0120
0121 pd_g3d: power-domain@10023c60 {
0122 compatible = "samsung,exynos4210-pd";
0123 reg = <0x10023C60 0x20>;
0124 #power-domain-cells = <0>;
0125 label = "G3D";
0126 };
0127
0128 pd_lcd0: power-domain@10023c80 {
0129 compatible = "samsung,exynos4210-pd";
0130 reg = <0x10023C80 0x20>;
0131 #power-domain-cells = <0>;
0132 label = "LCD0";
0133 };
0134
0135 pd_tv: power-domain@10023c20 {
0136 compatible = "samsung,exynos4210-pd";
0137 reg = <0x10023C20 0x20>;
0138 #power-domain-cells = <0>;
0139 power-domains = <&pd_lcd0>;
0140 label = "TV";
0141 };
0142
0143 pd_cam: power-domain@10023c00 {
0144 compatible = "samsung,exynos4210-pd";
0145 reg = <0x10023C00 0x20>;
0146 #power-domain-cells = <0>;
0147 label = "CAM";
0148 };
0149
0150 pd_gps: power-domain@10023ce0 {
0151 compatible = "samsung,exynos4210-pd";
0152 reg = <0x10023CE0 0x20>;
0153 #power-domain-cells = <0>;
0154 label = "GPS";
0155 };
0156
0157 pd_gps_alive: power-domain@10023d00 {
0158 compatible = "samsung,exynos4210-pd";
0159 reg = <0x10023D00 0x20>;
0160 #power-domain-cells = <0>;
0161 label = "GPS alive";
0162 };
0163
0164 gic: interrupt-controller@10490000 {
0165 compatible = "arm,cortex-a9-gic";
0166 #interrupt-cells = <3>;
0167 interrupt-controller;
0168 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
0169 };
0170
0171 combiner: interrupt-controller@10440000 {
0172 compatible = "samsung,exynos4210-combiner";
0173 #interrupt-cells = <2>;
0174 interrupt-controller;
0175 reg = <0x10440000 0x1000>;
0176 };
0177
0178 sys_reg: syscon@10010000 {
0179 compatible = "samsung,exynos4-sysreg", "syscon";
0180 reg = <0x10010000 0x400>;
0181 };
0182
0183 pmu_system_controller: system-controller@10020000 {
0184 compatible = "samsung,exynos4210-pmu", "syscon";
0185 reg = <0x10020000 0x4000>;
0186 interrupt-controller;
0187 #interrupt-cells = <3>;
0188 interrupt-parent = <&gic>;
0189 };
0190
0191 dsi_0: dsi@11c80000 {
0192 compatible = "samsung,exynos4210-mipi-dsi";
0193 reg = <0x11C80000 0x10000>;
0194 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0195 power-domains = <&pd_lcd0>;
0196 phys = <&mipi_phy 1>;
0197 phy-names = "dsim";
0198 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
0199 clock-names = "bus_clk", "sclk_mipi";
0200 status = "disabled";
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 };
0204
0205 camera: camera {
0206 compatible = "samsung,fimc", "simple-bus";
0207 status = "disabled";
0208 #address-cells = <1>;
0209 #size-cells = <1>;
0210 #clock-cells = <1>;
0211 clock-output-names = "cam_a_clkout", "cam_b_clkout";
0212 ranges;
0213
0214 fimc_0: fimc@11800000 {
0215 compatible = "samsung,exynos4210-fimc";
0216 reg = <0x11800000 0x1000>;
0217 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0218 clocks = <&clock CLK_FIMC0>,
0219 <&clock CLK_SCLK_FIMC0>;
0220 clock-names = "fimc", "sclk_fimc";
0221 power-domains = <&pd_cam>;
0222 samsung,sysreg = <&sys_reg>;
0223 iommus = <&sysmmu_fimc0>;
0224 status = "disabled";
0225 };
0226
0227 fimc_1: fimc@11810000 {
0228 compatible = "samsung,exynos4210-fimc";
0229 reg = <0x11810000 0x1000>;
0230 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0231 clocks = <&clock CLK_FIMC1>,
0232 <&clock CLK_SCLK_FIMC1>;
0233 clock-names = "fimc", "sclk_fimc";
0234 power-domains = <&pd_cam>;
0235 samsung,sysreg = <&sys_reg>;
0236 iommus = <&sysmmu_fimc1>;
0237 status = "disabled";
0238 };
0239
0240 fimc_2: fimc@11820000 {
0241 compatible = "samsung,exynos4210-fimc";
0242 reg = <0x11820000 0x1000>;
0243 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0244 clocks = <&clock CLK_FIMC2>,
0245 <&clock CLK_SCLK_FIMC2>;
0246 clock-names = "fimc", "sclk_fimc";
0247 power-domains = <&pd_cam>;
0248 samsung,sysreg = <&sys_reg>;
0249 iommus = <&sysmmu_fimc2>;
0250 status = "disabled";
0251 };
0252
0253 fimc_3: fimc@11830000 {
0254 compatible = "samsung,exynos4210-fimc";
0255 reg = <0x11830000 0x1000>;
0256 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0257 clocks = <&clock CLK_FIMC3>,
0258 <&clock CLK_SCLK_FIMC3>;
0259 clock-names = "fimc", "sclk_fimc";
0260 power-domains = <&pd_cam>;
0261 samsung,sysreg = <&sys_reg>;
0262 iommus = <&sysmmu_fimc3>;
0263 status = "disabled";
0264 };
0265
0266 csis_0: csis@11880000 {
0267 compatible = "samsung,exynos4210-csis";
0268 reg = <0x11880000 0x4000>;
0269 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0270 clocks = <&clock CLK_CSIS0>,
0271 <&clock CLK_SCLK_CSIS0>;
0272 clock-names = "csis", "sclk_csis";
0273 bus-width = <4>;
0274 power-domains = <&pd_cam>;
0275 phys = <&mipi_phy 0>;
0276 phy-names = "csis";
0277 status = "disabled";
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 };
0281
0282 csis_1: csis@11890000 {
0283 compatible = "samsung,exynos4210-csis";
0284 reg = <0x11890000 0x4000>;
0285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0286 clocks = <&clock CLK_CSIS1>,
0287 <&clock CLK_SCLK_CSIS1>;
0288 clock-names = "csis", "sclk_csis";
0289 bus-width = <2>;
0290 power-domains = <&pd_cam>;
0291 phys = <&mipi_phy 2>;
0292 phy-names = "csis";
0293 status = "disabled";
0294 #address-cells = <1>;
0295 #size-cells = <0>;
0296 };
0297 };
0298
0299 rtc: rtc@10070000 {
0300 compatible = "samsung,s3c6410-rtc";
0301 reg = <0x10070000 0x100>;
0302 interrupt-parent = <&pmu_system_controller>;
0303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0305 clocks = <&clock CLK_RTC>;
0306 clock-names = "rtc";
0307 status = "disabled";
0308 };
0309
0310 keypad: keypad@100a0000 {
0311 compatible = "samsung,s5pv210-keypad";
0312 reg = <0x100A0000 0x100>;
0313 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0314 clocks = <&clock CLK_KEYIF>;
0315 clock-names = "keypad";
0316 status = "disabled";
0317 };
0318
0319 sdhci_0: mmc@12510000 {
0320 compatible = "samsung,exynos4210-sdhci";
0321 reg = <0x12510000 0x100>;
0322 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
0324 clock-names = "hsmmc", "mmc_busclk.2";
0325 status = "disabled";
0326 };
0327
0328 sdhci_1: mmc@12520000 {
0329 compatible = "samsung,exynos4210-sdhci";
0330 reg = <0x12520000 0x100>;
0331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0332 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
0333 clock-names = "hsmmc", "mmc_busclk.2";
0334 status = "disabled";
0335 };
0336
0337 sdhci_2: mmc@12530000 {
0338 compatible = "samsung,exynos4210-sdhci";
0339 reg = <0x12530000 0x100>;
0340 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0341 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
0342 clock-names = "hsmmc", "mmc_busclk.2";
0343 status = "disabled";
0344 };
0345
0346 sdhci_3: mmc@12540000 {
0347 compatible = "samsung,exynos4210-sdhci";
0348 reg = <0x12540000 0x100>;
0349 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0350 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
0351 clock-names = "hsmmc", "mmc_busclk.2";
0352 status = "disabled";
0353 };
0354
0355 exynos_usbphy: exynos-usbphy@125b0000 {
0356 compatible = "samsung,exynos4210-usb2-phy";
0357 reg = <0x125B0000 0x100>;
0358 samsung,pmureg-phandle = <&pmu_system_controller>;
0359 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
0360 clock-names = "phy", "ref";
0361 #phy-cells = <1>;
0362 status = "disabled";
0363 };
0364
0365 hsotg: hsotg@12480000 {
0366 compatible = "samsung,s3c6400-hsotg";
0367 reg = <0x12480000 0x20000>;
0368 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0369 clocks = <&clock CLK_USB_DEVICE>;
0370 clock-names = "otg";
0371 phys = <&exynos_usbphy 0>;
0372 phy-names = "usb2-phy";
0373 status = "disabled";
0374 };
0375
0376 ehci: usb@12580000 {
0377 compatible = "samsung,exynos4210-ehci";
0378 reg = <0x12580000 0x100>;
0379 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0380 clocks = <&clock CLK_USB_HOST>;
0381 clock-names = "usbhost";
0382 status = "disabled";
0383 phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
0384 phy-names = "host", "hsic0", "hsic1";
0385 };
0386
0387 ohci: usb@12590000 {
0388 compatible = "samsung,exynos4210-ohci";
0389 reg = <0x12590000 0x100>;
0390 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0391 clocks = <&clock CLK_USB_HOST>;
0392 clock-names = "usbhost";
0393 status = "disabled";
0394 phys = <&exynos_usbphy 1>;
0395 phy-names = "host";
0396 };
0397
0398 gpu: gpu@13000000 {
0399 compatible = "samsung,exynos4210-mali", "arm,mali-400";
0400 reg = <0x13000000 0x10000>;
0401 /*
0402 * CLK_G3D is not actually bus clock but a IP-level clock.
0403 * The bus clock is not described in hardware manual.
0404 */
0405 clocks = <&clock CLK_G3D>,
0406 <&clock CLK_SCLK_G3D>;
0407 clock-names = "bus", "core";
0408 power-domains = <&pd_g3d>;
0409 status = "disabled";
0410 };
0411
0412 i2s1: i2s@13960000 {
0413 compatible = "samsung,s3c6410-i2s";
0414 reg = <0x13960000 0x100>;
0415 clocks = <&clock CLK_I2S1>;
0416 clock-names = "iis";
0417 #clock-cells = <1>;
0418 clock-output-names = "i2s_cdclk1";
0419 dmas = <&pdma1 12>, <&pdma1 11>;
0420 dma-names = "tx", "rx";
0421 #sound-dai-cells = <1>;
0422 status = "disabled";
0423 };
0424
0425 i2s2: i2s@13970000 {
0426 compatible = "samsung,s3c6410-i2s";
0427 reg = <0x13970000 0x100>;
0428 clocks = <&clock CLK_I2S2>;
0429 clock-names = "iis";
0430 #clock-cells = <1>;
0431 clock-output-names = "i2s_cdclk2";
0432 dmas = <&pdma0 14>, <&pdma0 13>;
0433 dma-names = "tx", "rx";
0434 #sound-dai-cells = <1>;
0435 status = "disabled";
0436 };
0437
0438 mfc: codec@13400000 {
0439 compatible = "samsung,mfc-v5";
0440 reg = <0x13400000 0x10000>;
0441 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0442 power-domains = <&pd_mfc>;
0443 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
0444 clock-names = "mfc", "sclk_mfc";
0445 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
0446 iommu-names = "left", "right";
0447 };
0448
0449 serial_0: serial@13800000 {
0450 compatible = "samsung,exynos4210-uart";
0451 reg = <0x13800000 0x100>;
0452 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
0454 clock-names = "uart", "clk_uart_baud0";
0455 dmas = <&pdma0 15>, <&pdma0 16>;
0456 dma-names = "rx", "tx";
0457 status = "disabled";
0458 };
0459
0460 serial_1: serial@13810000 {
0461 compatible = "samsung,exynos4210-uart";
0462 reg = <0x13810000 0x100>;
0463 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0464 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
0465 clock-names = "uart", "clk_uart_baud0";
0466 dmas = <&pdma1 15>, <&pdma1 16>;
0467 dma-names = "rx", "tx";
0468 status = "disabled";
0469 };
0470
0471 serial_2: serial@13820000 {
0472 compatible = "samsung,exynos4210-uart";
0473 reg = <0x13820000 0x100>;
0474 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0475 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
0476 clock-names = "uart", "clk_uart_baud0";
0477 dmas = <&pdma0 17>, <&pdma0 18>;
0478 dma-names = "rx", "tx";
0479 status = "disabled";
0480 };
0481
0482 serial_3: serial@13830000 {
0483 compatible = "samsung,exynos4210-uart";
0484 reg = <0x13830000 0x100>;
0485 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
0487 clock-names = "uart", "clk_uart_baud0";
0488 dmas = <&pdma1 17>, <&pdma1 18>;
0489 dma-names = "rx", "tx";
0490 status = "disabled";
0491 };
0492
0493 i2c_0: i2c@13860000 {
0494 #address-cells = <1>;
0495 #size-cells = <0>;
0496 compatible = "samsung,s3c2440-i2c";
0497 reg = <0x13860000 0x100>;
0498 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0499 clocks = <&clock CLK_I2C0>;
0500 clock-names = "i2c";
0501 pinctrl-names = "default";
0502 pinctrl-0 = <&i2c0_bus>;
0503 status = "disabled";
0504 };
0505
0506 i2c_1: i2c@13870000 {
0507 #address-cells = <1>;
0508 #size-cells = <0>;
0509 compatible = "samsung,s3c2440-i2c";
0510 reg = <0x13870000 0x100>;
0511 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0512 clocks = <&clock CLK_I2C1>;
0513 clock-names = "i2c";
0514 pinctrl-names = "default";
0515 pinctrl-0 = <&i2c1_bus>;
0516 status = "disabled";
0517 };
0518
0519 i2c_2: i2c@13880000 {
0520 #address-cells = <1>;
0521 #size-cells = <0>;
0522 compatible = "samsung,s3c2440-i2c";
0523 reg = <0x13880000 0x100>;
0524 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0525 clocks = <&clock CLK_I2C2>;
0526 clock-names = "i2c";
0527 pinctrl-names = "default";
0528 pinctrl-0 = <&i2c2_bus>;
0529 status = "disabled";
0530 };
0531
0532 i2c_3: i2c@13890000 {
0533 #address-cells = <1>;
0534 #size-cells = <0>;
0535 compatible = "samsung,s3c2440-i2c";
0536 reg = <0x13890000 0x100>;
0537 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0538 clocks = <&clock CLK_I2C3>;
0539 clock-names = "i2c";
0540 pinctrl-names = "default";
0541 pinctrl-0 = <&i2c3_bus>;
0542 status = "disabled";
0543 };
0544
0545 i2c_4: i2c@138a0000 {
0546 #address-cells = <1>;
0547 #size-cells = <0>;
0548 compatible = "samsung,s3c2440-i2c";
0549 reg = <0x138A0000 0x100>;
0550 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0551 clocks = <&clock CLK_I2C4>;
0552 clock-names = "i2c";
0553 pinctrl-names = "default";
0554 pinctrl-0 = <&i2c4_bus>;
0555 status = "disabled";
0556 };
0557
0558 i2c_5: i2c@138b0000 {
0559 #address-cells = <1>;
0560 #size-cells = <0>;
0561 compatible = "samsung,s3c2440-i2c";
0562 reg = <0x138B0000 0x100>;
0563 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0564 clocks = <&clock CLK_I2C5>;
0565 clock-names = "i2c";
0566 pinctrl-names = "default";
0567 pinctrl-0 = <&i2c5_bus>;
0568 status = "disabled";
0569 };
0570
0571 i2c_6: i2c@138c0000 {
0572 #address-cells = <1>;
0573 #size-cells = <0>;
0574 compatible = "samsung,s3c2440-i2c";
0575 reg = <0x138C0000 0x100>;
0576 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0577 clocks = <&clock CLK_I2C6>;
0578 clock-names = "i2c";
0579 pinctrl-names = "default";
0580 pinctrl-0 = <&i2c6_bus>;
0581 status = "disabled";
0582 };
0583
0584 i2c_7: i2c@138d0000 {
0585 #address-cells = <1>;
0586 #size-cells = <0>;
0587 compatible = "samsung,s3c2440-i2c";
0588 reg = <0x138D0000 0x100>;
0589 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0590 clocks = <&clock CLK_I2C7>;
0591 clock-names = "i2c";
0592 pinctrl-names = "default";
0593 pinctrl-0 = <&i2c7_bus>;
0594 status = "disabled";
0595 };
0596
0597 i2c_8: i2c@138e0000 {
0598 #address-cells = <1>;
0599 #size-cells = <0>;
0600 compatible = "samsung,s3c2440-hdmiphy-i2c";
0601 reg = <0x138E0000 0x100>;
0602 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0603 clocks = <&clock CLK_I2C_HDMI>;
0604 clock-names = "i2c";
0605 status = "disabled";
0606
0607 hdmi_i2c_phy: hdmiphy@38 {
0608 compatible = "exynos4210-hdmiphy";
0609 reg = <0x38>;
0610 };
0611 };
0612
0613 spi_0: spi@13920000 {
0614 compatible = "samsung,exynos4210-spi";
0615 reg = <0x13920000 0x100>;
0616 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0617 dmas = <&pdma0 7>, <&pdma0 6>;
0618 dma-names = "tx", "rx";
0619 #address-cells = <1>;
0620 #size-cells = <0>;
0621 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
0622 clock-names = "spi", "spi_busclk0";
0623 pinctrl-names = "default";
0624 pinctrl-0 = <&spi0_bus>;
0625 status = "disabled";
0626 };
0627
0628 spi_1: spi@13930000 {
0629 compatible = "samsung,exynos4210-spi";
0630 reg = <0x13930000 0x100>;
0631 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0632 dmas = <&pdma1 7>, <&pdma1 6>;
0633 dma-names = "tx", "rx";
0634 #address-cells = <1>;
0635 #size-cells = <0>;
0636 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
0637 clock-names = "spi", "spi_busclk0";
0638 pinctrl-names = "default";
0639 pinctrl-0 = <&spi1_bus>;
0640 status = "disabled";
0641 };
0642
0643 spi_2: spi@13940000 {
0644 compatible = "samsung,exynos4210-spi";
0645 reg = <0x13940000 0x100>;
0646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0647 dmas = <&pdma0 9>, <&pdma0 8>;
0648 dma-names = "tx", "rx";
0649 #address-cells = <1>;
0650 #size-cells = <0>;
0651 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
0652 clock-names = "spi", "spi_busclk0";
0653 pinctrl-names = "default";
0654 pinctrl-0 = <&spi2_bus>;
0655 status = "disabled";
0656 };
0657
0658 pwm: pwm@139d0000 {
0659 compatible = "samsung,exynos4210-pwm";
0660 reg = <0x139D0000 0x1000>;
0661 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0662 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0663 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0664 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0665 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0666 clocks = <&clock CLK_PWM>;
0667 clock-names = "timers";
0668 #pwm-cells = <3>;
0669 status = "disabled";
0670 };
0671
0672 pdma0: dma-controller@12680000 {
0673 compatible = "arm,pl330", "arm,primecell";
0674 reg = <0x12680000 0x1000>;
0675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0676 clocks = <&clock CLK_PDMA0>;
0677 clock-names = "apb_pclk";
0678 #dma-cells = <1>;
0679 };
0680
0681 pdma1: dma-controller@12690000 {
0682 compatible = "arm,pl330", "arm,primecell";
0683 reg = <0x12690000 0x1000>;
0684 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0685 clocks = <&clock CLK_PDMA1>;
0686 clock-names = "apb_pclk";
0687 #dma-cells = <1>;
0688 };
0689
0690 mdma1: dma-controller@12850000 {
0691 compatible = "arm,pl330", "arm,primecell";
0692 reg = <0x12850000 0x1000>;
0693 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0694 clocks = <&clock CLK_MDMA>;
0695 clock-names = "apb_pclk";
0696 #dma-cells = <1>;
0697 };
0698
0699 fimd: fimd@11c00000 {
0700 compatible = "samsung,exynos4210-fimd";
0701 interrupt-parent = <&combiner>;
0702 reg = <0x11c00000 0x20000>;
0703 interrupt-names = "fifo", "vsync", "lcd_sys";
0704 interrupts = <11 0>, <11 1>, <11 2>;
0705 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
0706 clock-names = "sclk_fimd", "fimd";
0707 power-domains = <&pd_lcd0>;
0708 iommus = <&sysmmu_fimd0>;
0709 samsung,sysreg = <&sys_reg>;
0710 status = "disabled";
0711 };
0712
0713 tmu: tmu@100c0000 {
0714 interrupt-parent = <&combiner>;
0715 reg = <0x100C0000 0x100>;
0716 interrupts = <2 4>;
0717 status = "disabled";
0718 #thermal-sensor-cells = <0>;
0719 };
0720
0721 jpeg_codec: jpeg-codec@11840000 {
0722 compatible = "samsung,exynos4210-jpeg";
0723 reg = <0x11840000 0x1000>;
0724 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0725 clocks = <&clock CLK_JPEG>;
0726 clock-names = "jpeg";
0727 power-domains = <&pd_cam>;
0728 iommus = <&sysmmu_jpeg>;
0729 };
0730
0731 rotator: rotator@12810000 {
0732 compatible = "samsung,exynos4210-rotator";
0733 reg = <0x12810000 0x64>;
0734 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0735 clocks = <&clock CLK_ROTATOR>;
0736 clock-names = "rotator";
0737 iommus = <&sysmmu_rotator>;
0738 };
0739
0740 hdmi: hdmi@12d00000 {
0741 compatible = "samsung,exynos4210-hdmi";
0742 reg = <0x12D00000 0x70000>;
0743 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0744 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
0745 "sclk_hdmiphy", "mout_hdmi";
0746 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
0747 <&clock CLK_SCLK_PIXEL>,
0748 <&clock CLK_SCLK_HDMIPHY>,
0749 <&clock CLK_MOUT_HDMI>;
0750 phy = <&hdmi_i2c_phy>;
0751 power-domains = <&pd_tv>;
0752 samsung,syscon-phandle = <&pmu_system_controller>;
0753 #sound-dai-cells = <0>;
0754 status = "disabled";
0755 };
0756
0757 hdmicec: cec@100b0000 {
0758 compatible = "samsung,s5p-cec";
0759 reg = <0x100B0000 0x200>;
0760 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0761 clocks = <&clock CLK_HDMI_CEC>;
0762 clock-names = "hdmicec";
0763 samsung,syscon-phandle = <&pmu_system_controller>;
0764 hdmi-phandle = <&hdmi>;
0765 pinctrl-names = "default";
0766 pinctrl-0 = <&hdmi_cec>;
0767 status = "disabled";
0768 };
0769
0770 mixer: mixer@12c10000 {
0771 compatible = "samsung,exynos4210-mixer";
0772 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0773 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
0774 power-domains = <&pd_tv>;
0775 iommus = <&sysmmu_tv>;
0776 status = "disabled";
0777 };
0778
0779 ppmu_dmc0: ppmu@106a0000 {
0780 compatible = "samsung,exynos-ppmu";
0781 reg = <0x106a0000 0x2000>;
0782 clocks = <&clock CLK_PPMUDMC0>;
0783 clock-names = "ppmu";
0784 status = "disabled";
0785 };
0786
0787 ppmu_dmc1: ppmu@106b0000 {
0788 compatible = "samsung,exynos-ppmu";
0789 reg = <0x106b0000 0x2000>;
0790 clocks = <&clock CLK_PPMUDMC1>;
0791 clock-names = "ppmu";
0792 status = "disabled";
0793 };
0794
0795 ppmu_cpu: ppmu@106c0000 {
0796 compatible = "samsung,exynos-ppmu";
0797 reg = <0x106c0000 0x2000>;
0798 clocks = <&clock CLK_PPMUCPU>;
0799 clock-names = "ppmu";
0800 status = "disabled";
0801 };
0802
0803 ppmu_rightbus: ppmu@112a0000 {
0804 compatible = "samsung,exynos-ppmu";
0805 reg = <0x112a0000 0x2000>;
0806 clocks = <&clock CLK_PPMURIGHT>;
0807 clock-names = "ppmu";
0808 status = "disabled";
0809 };
0810
0811 ppmu_leftbus: ppmu@116a0000 {
0812 compatible = "samsung,exynos-ppmu";
0813 reg = <0x116a0000 0x2000>;
0814 clocks = <&clock CLK_PPMULEFT>;
0815 clock-names = "ppmu";
0816 status = "disabled";
0817 };
0818
0819 ppmu_camif: ppmu@11ac0000 {
0820 compatible = "samsung,exynos-ppmu";
0821 reg = <0x11ac0000 0x2000>;
0822 clocks = <&clock CLK_PPMUCAMIF>;
0823 clock-names = "ppmu";
0824 status = "disabled";
0825 };
0826
0827 ppmu_lcd0: ppmu@11e40000 {
0828 compatible = "samsung,exynos-ppmu";
0829 reg = <0x11e40000 0x2000>;
0830 clocks = <&clock CLK_PPMULCD0>;
0831 clock-names = "ppmu";
0832 status = "disabled";
0833 };
0834
0835 ppmu_fsys: ppmu@12630000 {
0836 compatible = "samsung,exynos-ppmu";
0837 reg = <0x12630000 0x2000>;
0838 status = "disabled";
0839 };
0840
0841 ppmu_image: ppmu@12aa0000 {
0842 compatible = "samsung,exynos-ppmu";
0843 reg = <0x12aa0000 0x2000>;
0844 clocks = <&clock CLK_PPMUIMAGE>;
0845 clock-names = "ppmu";
0846 status = "disabled";
0847 };
0848
0849 ppmu_tv: ppmu@12e40000 {
0850 compatible = "samsung,exynos-ppmu";
0851 reg = <0x12e40000 0x2000>;
0852 clocks = <&clock CLK_PPMUTV>;
0853 clock-names = "ppmu";
0854 status = "disabled";
0855 };
0856
0857 ppmu_g3d: ppmu@13220000 {
0858 compatible = "samsung,exynos-ppmu";
0859 reg = <0x13220000 0x2000>;
0860 clocks = <&clock CLK_PPMUG3D>;
0861 clock-names = "ppmu";
0862 status = "disabled";
0863 };
0864
0865 ppmu_mfc_left: ppmu@13660000 {
0866 compatible = "samsung,exynos-ppmu";
0867 reg = <0x13660000 0x2000>;
0868 clocks = <&clock CLK_PPMUMFC_L>;
0869 clock-names = "ppmu";
0870 status = "disabled";
0871 };
0872
0873 ppmu_mfc_right: ppmu@13670000 {
0874 compatible = "samsung,exynos-ppmu";
0875 reg = <0x13670000 0x2000>;
0876 clocks = <&clock CLK_PPMUMFC_R>;
0877 clock-names = "ppmu";
0878 status = "disabled";
0879 };
0880
0881 sysmmu_mfc_l: sysmmu@13620000 {
0882 compatible = "samsung,exynos-sysmmu";
0883 reg = <0x13620000 0x1000>;
0884 interrupt-parent = <&combiner>;
0885 interrupts = <5 5>;
0886 clock-names = "sysmmu", "master";
0887 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
0888 power-domains = <&pd_mfc>;
0889 #iommu-cells = <0>;
0890 };
0891
0892 sysmmu_mfc_r: sysmmu@13630000 {
0893 compatible = "samsung,exynos-sysmmu";
0894 reg = <0x13630000 0x1000>;
0895 interrupt-parent = <&combiner>;
0896 interrupts = <5 6>;
0897 clock-names = "sysmmu", "master";
0898 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
0899 power-domains = <&pd_mfc>;
0900 #iommu-cells = <0>;
0901 };
0902
0903 sysmmu_tv: sysmmu@12e20000 {
0904 compatible = "samsung,exynos-sysmmu";
0905 reg = <0x12E20000 0x1000>;
0906 interrupt-parent = <&combiner>;
0907 interrupts = <5 4>;
0908 clock-names = "sysmmu", "master";
0909 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
0910 power-domains = <&pd_tv>;
0911 #iommu-cells = <0>;
0912 };
0913
0914 sysmmu_fimc0: sysmmu@11a20000 {
0915 compatible = "samsung,exynos-sysmmu";
0916 reg = <0x11A20000 0x1000>;
0917 interrupt-parent = <&combiner>;
0918 interrupts = <4 2>;
0919 clock-names = "sysmmu", "master";
0920 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
0921 power-domains = <&pd_cam>;
0922 #iommu-cells = <0>;
0923 };
0924
0925 sysmmu_fimc1: sysmmu@11a30000 {
0926 compatible = "samsung,exynos-sysmmu";
0927 reg = <0x11A30000 0x1000>;
0928 interrupt-parent = <&combiner>;
0929 interrupts = <4 3>;
0930 clock-names = "sysmmu", "master";
0931 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
0932 power-domains = <&pd_cam>;
0933 #iommu-cells = <0>;
0934 };
0935
0936 sysmmu_fimc2: sysmmu@11a40000 {
0937 compatible = "samsung,exynos-sysmmu";
0938 reg = <0x11A40000 0x1000>;
0939 interrupt-parent = <&combiner>;
0940 interrupts = <4 4>;
0941 clock-names = "sysmmu", "master";
0942 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
0943 power-domains = <&pd_cam>;
0944 #iommu-cells = <0>;
0945 };
0946
0947 sysmmu_fimc3: sysmmu@11a50000 {
0948 compatible = "samsung,exynos-sysmmu";
0949 reg = <0x11A50000 0x1000>;
0950 interrupt-parent = <&combiner>;
0951 interrupts = <4 5>;
0952 clock-names = "sysmmu", "master";
0953 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
0954 power-domains = <&pd_cam>;
0955 #iommu-cells = <0>;
0956 };
0957
0958 sysmmu_jpeg: sysmmu@11a60000 {
0959 compatible = "samsung,exynos-sysmmu";
0960 reg = <0x11A60000 0x1000>;
0961 interrupt-parent = <&combiner>;
0962 interrupts = <4 6>;
0963 clock-names = "sysmmu", "master";
0964 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
0965 power-domains = <&pd_cam>;
0966 #iommu-cells = <0>;
0967 };
0968
0969 sysmmu_rotator: sysmmu@12a30000 {
0970 compatible = "samsung,exynos-sysmmu";
0971 reg = <0x12A30000 0x1000>;
0972 interrupt-parent = <&combiner>;
0973 interrupts = <5 0>;
0974 clock-names = "sysmmu", "master";
0975 clocks = <&clock CLK_SMMU_ROTATOR>,
0976 <&clock CLK_ROTATOR>;
0977 #iommu-cells = <0>;
0978 };
0979
0980 sysmmu_fimd0: sysmmu@11e20000 {
0981 compatible = "samsung,exynos-sysmmu";
0982 reg = <0x11E20000 0x1000>;
0983 interrupt-parent = <&combiner>;
0984 interrupts = <5 2>;
0985 clock-names = "sysmmu", "master";
0986 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
0987 power-domains = <&pd_lcd0>;
0988 #iommu-cells = <0>;
0989 };
0990
0991 sss: sss@10830000 {
0992 compatible = "samsung,exynos4210-secss";
0993 reg = <0x10830000 0x300>;
0994 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0995 clocks = <&clock CLK_SSS>;
0996 clock-names = "secss";
0997 };
0998
0999 prng: rng@10830400 {
1000 compatible = "samsung,exynos4-rng";
1001 reg = <0x10830400 0x200>;
1002 clocks = <&clock CLK_SSS>;
1003 clock-names = "secss";
1004 };
1005 };
1006 };
1007
1008 #include "exynos-syscon-restart.dtsi"
