0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos3250 SoC device tree source
0004 *
0005 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
0009 * based board files can include this file and provide values for board specfic
0010 * bindings.
0011 *
0012 * Note: This file does not include device nodes for all the controllers in
0013 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
0014 * nodes can be added to this file.
0015 */
0016
0017 #include "exynos4-cpu-thermal.dtsi"
0018 #include <dt-bindings/clock/exynos3250.h>
0019 #include <dt-bindings/interrupt-controller/arm-gic.h>
0020 #include <dt-bindings/interrupt-controller/irq.h>
0021
0022 / {
0023 compatible = "samsung,exynos3250";
0024 interrupt-parent = <&gic>;
0025 #address-cells = <1>;
0026 #size-cells = <1>;
0027
0028 aliases {
0029 pinctrl0 = &pinctrl_0;
0030 pinctrl1 = &pinctrl_1;
0031 mshc0 = &mshc_0;
0032 mshc1 = &mshc_1;
0033 mshc2 = &mshc_2;
0034 spi0 = &spi_0;
0035 spi1 = &spi_1;
0036 i2c0 = &i2c_0;
0037 i2c1 = &i2c_1;
0038 i2c2 = &i2c_2;
0039 i2c3 = &i2c_3;
0040 i2c4 = &i2c_4;
0041 i2c5 = &i2c_5;
0042 i2c6 = &i2c_6;
0043 i2c7 = &i2c_7;
0044 serial0 = &serial_0;
0045 serial1 = &serial_1;
0046 serial2 = &serial_2;
0047 };
0048
0049 cpus {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 cpu-map {
0054 cluster0 {
0055 core0 {
0056 cpu = <&cpu0>;
0057 };
0058 core1 {
0059 cpu = <&cpu1>;
0060 };
0061 };
0062 };
0063
0064 cpu0: cpu@0 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a7";
0067 reg = <0>;
0068 clock-frequency = <1000000000>;
0069 clocks = <&cmu CLK_ARM_CLK>;
0070 clock-names = "cpu";
0071 #cooling-cells = <2>;
0072
0073 operating-points = <
0074 1000000 1150000
0075 900000 1112500
0076 800000 1075000
0077 700000 1037500
0078 600000 1000000
0079 500000 962500
0080 400000 925000
0081 300000 887500
0082 200000 850000
0083 100000 850000
0084 >;
0085 };
0086
0087 cpu1: cpu@1 {
0088 device_type = "cpu";
0089 compatible = "arm,cortex-a7";
0090 reg = <1>;
0091 clock-frequency = <1000000000>;
0092 clocks = <&cmu CLK_ARM_CLK>;
0093 clock-names = "cpu";
0094 #cooling-cells = <2>;
0095
0096 operating-points = <
0097 1000000 1150000
0098 900000 1112500
0099 800000 1075000
0100 700000 1037500
0101 600000 1000000
0102 500000 962500
0103 400000 925000
0104 300000 887500
0105 200000 850000
0106 100000 850000
0107 >;
0108 };
0109 };
0110
0111 xusbxti: clock-0 {
0112 compatible = "fixed-clock";
0113 clock-frequency = <0>;
0114 #clock-cells = <0>;
0115 clock-output-names = "xusbxti";
0116 };
0117
0118 xxti: clock-1 {
0119 compatible = "fixed-clock";
0120 clock-frequency = <0>;
0121 #clock-cells = <0>;
0122 clock-output-names = "xxti";
0123 };
0124
0125 xtcxo: clock-2 {
0126 compatible = "fixed-clock";
0127 clock-frequency = <0>;
0128 #clock-cells = <0>;
0129 clock-output-names = "xtcxo";
0130 };
0131
0132 pmu {
0133 compatible = "arm,cortex-a7-pmu";
0134 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0135 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0136 };
0137
0138 soc: soc {
0139 compatible = "simple-bus";
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 ranges;
0143
0144 sram@2020000 {
0145 compatible = "mmio-sram";
0146 reg = <0x02020000 0x40000>;
0147 #address-cells = <1>;
0148 #size-cells = <1>;
0149 ranges = <0 0x02020000 0x40000>;
0150
0151 smp-sram@0 {
0152 compatible = "samsung,exynos4210-sysram";
0153 reg = <0x0 0x1000>;
0154 };
0155
0156 smp-sram@3f000 {
0157 compatible = "samsung,exynos4210-sysram-ns";
0158 reg = <0x3f000 0x1000>;
0159 };
0160 };
0161
0162 chipid@10000000 {
0163 compatible = "samsung,exynos4210-chipid";
0164 reg = <0x10000000 0x100>;
0165 };
0166
0167 sys_reg: syscon@10010000 {
0168 compatible = "samsung,exynos3-sysreg", "syscon";
0169 reg = <0x10010000 0x400>;
0170 };
0171
0172 pmu_system_controller: system-controller@10020000 {
0173 compatible = "samsung,exynos3250-pmu", "syscon";
0174 reg = <0x10020000 0x4000>;
0175 interrupt-controller;
0176 #interrupt-cells = <3>;
0177 interrupt-parent = <&gic>;
0178 clock-names = "clkout8";
0179 clocks = <&cmu CLK_FIN_PLL>;
0180 #clock-cells = <1>;
0181 };
0182
0183 mipi_phy: video-phy {
0184 compatible = "samsung,s5pv210-mipi-video-phy";
0185 #phy-cells = <1>;
0186 syscon = <&pmu_system_controller>;
0187 };
0188
0189 pd_cam: power-domain@10023c00 {
0190 compatible = "samsung,exynos4210-pd";
0191 reg = <0x10023C00 0x20>;
0192 #power-domain-cells = <0>;
0193 label = "CAM";
0194 };
0195
0196 pd_mfc: power-domain@10023c40 {
0197 compatible = "samsung,exynos4210-pd";
0198 reg = <0x10023C40 0x20>;
0199 #power-domain-cells = <0>;
0200 label = "MFC";
0201 };
0202
0203 pd_g3d: power-domain@10023c60 {
0204 compatible = "samsung,exynos4210-pd";
0205 reg = <0x10023C60 0x20>;
0206 #power-domain-cells = <0>;
0207 label = "G3D";
0208 };
0209
0210 pd_lcd0: power-domain@10023c80 {
0211 compatible = "samsung,exynos4210-pd";
0212 reg = <0x10023C80 0x20>;
0213 #power-domain-cells = <0>;
0214 label = "LCD0";
0215 };
0216
0217 pd_isp: power-domain@10023ca0 {
0218 compatible = "samsung,exynos4210-pd";
0219 reg = <0x10023CA0 0x20>;
0220 #power-domain-cells = <0>;
0221 label = "ISP";
0222 };
0223
0224 cmu: clock-controller@10030000 {
0225 compatible = "samsung,exynos3250-cmu";
0226 reg = <0x10030000 0x20000>;
0227 #clock-cells = <1>;
0228 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
0229 <&cmu CLK_MOUT_ACLK_266_SUB>;
0230 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
0231 <&cmu CLK_FIN_PLL>;
0232 };
0233
0234 cmu_dmc: clock-controller@105c0000 {
0235 compatible = "samsung,exynos3250-cmu-dmc";
0236 reg = <0x105C0000 0x2000>;
0237 #clock-cells = <1>;
0238 };
0239
0240 rtc: rtc@10070000 {
0241 compatible = "samsung,s3c6410-rtc";
0242 reg = <0x10070000 0x100>;
0243 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0244 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0245 interrupt-parent = <&pmu_system_controller>;
0246 status = "disabled";
0247 };
0248
0249 tmu: tmu@100c0000 {
0250 compatible = "samsung,exynos3250-tmu";
0251 reg = <0x100C0000 0x100>;
0252 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
0253 clocks = <&cmu CLK_TMU_APBIF>;
0254 clock-names = "tmu_apbif";
0255 #thermal-sensor-cells = <0>;
0256 status = "disabled";
0257 };
0258
0259 gic: interrupt-controller@10481000 {
0260 compatible = "arm,cortex-a15-gic";
0261 #interrupt-cells = <3>;
0262 interrupt-controller;
0263 reg = <0x10481000 0x1000>,
0264 <0x10482000 0x2000>,
0265 <0x10484000 0x2000>,
0266 <0x10486000 0x2000>;
0267 interrupts = <GIC_PPI 9
0268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0269 };
0270
0271 timer@10050000 {
0272 compatible = "samsung,exynos3250-mct",
0273 "samsung,exynos4210-mct";
0274 reg = <0x10050000 0x800>;
0275 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
0276 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
0277 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
0278 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
0279 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
0280 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
0281 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
0282 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
0283 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
0284 clock-names = "fin_pll", "mct";
0285 };
0286
0287 pinctrl_1: pinctrl@11000000 {
0288 compatible = "samsung,exynos3250-pinctrl";
0289 reg = <0x11000000 0x1000>;
0290 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
0291
0292 wakeup-interrupt-controller {
0293 compatible = "samsung,exynos4210-wakeup-eint";
0294 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0295 };
0296 };
0297
0298 pinctrl_0: pinctrl@11400000 {
0299 compatible = "samsung,exynos3250-pinctrl";
0300 reg = <0x11400000 0x1000>;
0301 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
0302 };
0303
0304 jpeg: codec@11830000 {
0305 compatible = "samsung,exynos3250-jpeg";
0306 reg = <0x11830000 0x1000>;
0307 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
0308 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
0309 clock-names = "jpeg", "sclk";
0310 power-domains = <&pd_cam>;
0311 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
0312 assigned-clock-rates = <0>, <150000000>;
0313 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
0314 iommus = <&sysmmu_jpeg>;
0315 status = "disabled";
0316 };
0317
0318 sysmmu_jpeg: sysmmu@11a60000 {
0319 compatible = "samsung,exynos-sysmmu";
0320 reg = <0x11a60000 0x1000>;
0321 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0322 clock-names = "sysmmu", "master";
0323 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
0324 power-domains = <&pd_cam>;
0325 #iommu-cells = <0>;
0326 };
0327
0328 fimd: fimd@11c00000 {
0329 compatible = "samsung,exynos3250-fimd";
0330 reg = <0x11c00000 0x30000>;
0331 interrupt-names = "fifo", "vsync", "lcd_sys";
0332 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0333 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0334 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0335 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
0336 clock-names = "sclk_fimd", "fimd";
0337 power-domains = <&pd_lcd0>;
0338 iommus = <&sysmmu_fimd0>;
0339 samsung,sysreg = <&sys_reg>;
0340 status = "disabled";
0341 };
0342
0343 dsi_0: dsi@11c80000 {
0344 compatible = "samsung,exynos3250-mipi-dsi";
0345 reg = <0x11C80000 0x10000>;
0346 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0347 samsung,phy-type = <0>;
0348 power-domains = <&pd_lcd0>;
0349 phys = <&mipi_phy 1>;
0350 phy-names = "dsim";
0351 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
0352 clock-names = "bus_clk", "pll_clk";
0353 #address-cells = <1>;
0354 #size-cells = <0>;
0355 status = "disabled";
0356 };
0357
0358 sysmmu_fimd0: sysmmu@11e20000 {
0359 compatible = "samsung,exynos-sysmmu";
0360 reg = <0x11e20000 0x1000>;
0361 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0362 clock-names = "sysmmu", "master";
0363 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
0364 power-domains = <&pd_lcd0>;
0365 #iommu-cells = <0>;
0366 };
0367
0368 hsotg: hsotg@12480000 {
0369 compatible = "samsung,s3c6400-hsotg";
0370 reg = <0x12480000 0x20000>;
0371 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&cmu CLK_USBOTG>;
0373 clock-names = "otg";
0374 phys = <&exynos_usbphy 0>;
0375 phy-names = "usb2-phy";
0376 status = "disabled";
0377 };
0378
0379 mshc_0: mmc@12510000 {
0380 compatible = "samsung,exynos5420-dw-mshc";
0381 reg = <0x12510000 0x1000>;
0382 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0383 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
0384 clock-names = "biu", "ciu";
0385 fifo-depth = <0x80>;
0386 #address-cells = <1>;
0387 #size-cells = <0>;
0388 status = "disabled";
0389 };
0390
0391 mshc_1: mmc@12520000 {
0392 compatible = "samsung,exynos5420-dw-mshc";
0393 reg = <0x12520000 0x1000>;
0394 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0395 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
0396 clock-names = "biu", "ciu";
0397 fifo-depth = <0x80>;
0398 #address-cells = <1>;
0399 #size-cells = <0>;
0400 status = "disabled";
0401 };
0402
0403 mshc_2: mmc@12530000 {
0404 compatible = "samsung,exynos5250-dw-mshc";
0405 reg = <0x12530000 0x1000>;
0406 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0407 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
0408 clock-names = "biu", "ciu";
0409 fifo-depth = <0x80>;
0410 #address-cells = <1>;
0411 #size-cells = <0>;
0412 status = "disabled";
0413 };
0414
0415 exynos_usbphy: exynos-usbphy@125b0000 {
0416 compatible = "samsung,exynos3250-usb2-phy";
0417 reg = <0x125B0000 0x100>;
0418 samsung,pmureg-phandle = <&pmu_system_controller>;
0419 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
0420 clock-names = "phy", "ref";
0421 #phy-cells = <1>;
0422 status = "disabled";
0423 };
0424
0425 pdma0: dma-controller@12680000 {
0426 compatible = "arm,pl330", "arm,primecell";
0427 reg = <0x12680000 0x1000>;
0428 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0429 clocks = <&cmu CLK_PDMA0>;
0430 clock-names = "apb_pclk";
0431 #dma-cells = <1>;
0432 };
0433
0434 pdma1: dma-controller@12690000 {
0435 compatible = "arm,pl330", "arm,primecell";
0436 reg = <0x12690000 0x1000>;
0437 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0438 clocks = <&cmu CLK_PDMA1>;
0439 clock-names = "apb_pclk";
0440 #dma-cells = <1>;
0441 };
0442
0443 adc: adc@126c0000 {
0444 compatible = "samsung,exynos3250-adc";
0445 reg = <0x126C0000 0x100>;
0446 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
0447 clock-names = "adc", "sclk";
0448 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
0449 #io-channel-cells = <1>;
0450 samsung,syscon-phandle = <&pmu_system_controller>;
0451 status = "disabled";
0452 };
0453
0454 gpu: gpu@13000000 {
0455 compatible = "samsung,exynos4210-mali", "arm,mali-400";
0456 reg = <0x13000000 0x10000>;
0457 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
0458 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
0459 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
0460 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
0461 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0462 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
0463 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0464 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
0465 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
0466 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
0467 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
0468 interrupt-names = "gp",
0469 "gpmmu",
0470 "pp0",
0471 "ppmmu0",
0472 "pp1",
0473 "ppmmu1",
0474 "pp2",
0475 "ppmmu2",
0476 "pp3",
0477 "ppmmu3",
0478 "pmu";
0479 clocks = <&cmu CLK_G3D>,
0480 <&cmu CLK_SCLK_G3D>;
0481 clock-names = "bus", "core";
0482 power-domains = <&pd_g3d>;
0483 status = "disabled";
0484 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
0485 };
0486
0487 mfc: codec@13400000 {
0488 compatible = "samsung,mfc-v7";
0489 reg = <0x13400000 0x10000>;
0490 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0491 clock-names = "mfc", "sclk_mfc";
0492 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
0493 power-domains = <&pd_mfc>;
0494 iommus = <&sysmmu_mfc>;
0495 };
0496
0497 sysmmu_mfc: sysmmu@13620000 {
0498 compatible = "samsung,exynos-sysmmu";
0499 reg = <0x13620000 0x1000>;
0500 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0501 clock-names = "sysmmu", "master";
0502 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
0503 power-domains = <&pd_mfc>;
0504 #iommu-cells = <0>;
0505 };
0506
0507 serial_0: serial@13800000 {
0508 compatible = "samsung,exynos4210-uart";
0509 reg = <0x13800000 0x100>;
0510 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0511 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
0512 clock-names = "uart", "clk_uart_baud0";
0513 pinctrl-names = "default";
0514 pinctrl-0 = <&uart0_data &uart0_fctl>;
0515 status = "disabled";
0516 };
0517
0518 serial_1: serial@13810000 {
0519 compatible = "samsung,exynos4210-uart";
0520 reg = <0x13810000 0x100>;
0521 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0522 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
0523 clock-names = "uart", "clk_uart_baud0";
0524 pinctrl-names = "default";
0525 pinctrl-0 = <&uart1_data>;
0526 status = "disabled";
0527 };
0528
0529 serial_2: serial@13820000 {
0530 compatible = "samsung,exynos4210-uart";
0531 reg = <0x13820000 0x100>;
0532 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0533 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
0534 clock-names = "uart", "clk_uart_baud0";
0535 pinctrl-names = "default";
0536 pinctrl-0 = <&uart2_data>;
0537 status = "disabled";
0538 };
0539
0540 i2c_0: i2c@13860000 {
0541 #address-cells = <1>;
0542 #size-cells = <0>;
0543 compatible = "samsung,s3c2440-i2c";
0544 reg = <0x13860000 0x100>;
0545 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0546 clocks = <&cmu CLK_I2C0>;
0547 clock-names = "i2c";
0548 pinctrl-names = "default";
0549 pinctrl-0 = <&i2c0_bus>;
0550 status = "disabled";
0551 };
0552
0553 i2c_1: i2c@13870000 {
0554 #address-cells = <1>;
0555 #size-cells = <0>;
0556 compatible = "samsung,s3c2440-i2c";
0557 reg = <0x13870000 0x100>;
0558 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0559 clocks = <&cmu CLK_I2C1>;
0560 clock-names = "i2c";
0561 pinctrl-names = "default";
0562 pinctrl-0 = <&i2c1_bus>;
0563 status = "disabled";
0564 };
0565
0566 i2c_2: i2c@13880000 {
0567 #address-cells = <1>;
0568 #size-cells = <0>;
0569 compatible = "samsung,s3c2440-i2c";
0570 reg = <0x13880000 0x100>;
0571 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0572 clocks = <&cmu CLK_I2C2>;
0573 clock-names = "i2c";
0574 pinctrl-names = "default";
0575 pinctrl-0 = <&i2c2_bus>;
0576 status = "disabled";
0577 };
0578
0579 i2c_3: i2c@13890000 {
0580 #address-cells = <1>;
0581 #size-cells = <0>;
0582 compatible = "samsung,s3c2440-i2c";
0583 reg = <0x13890000 0x100>;
0584 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0585 clocks = <&cmu CLK_I2C3>;
0586 clock-names = "i2c";
0587 pinctrl-names = "default";
0588 pinctrl-0 = <&i2c3_bus>;
0589 status = "disabled";
0590 };
0591
0592 i2c_4: i2c@138a0000 {
0593 #address-cells = <1>;
0594 #size-cells = <0>;
0595 compatible = "samsung,s3c2440-i2c";
0596 reg = <0x138A0000 0x100>;
0597 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0598 clocks = <&cmu CLK_I2C4>;
0599 clock-names = "i2c";
0600 pinctrl-names = "default";
0601 pinctrl-0 = <&i2c4_bus>;
0602 status = "disabled";
0603 };
0604
0605 i2c_5: i2c@138b0000 {
0606 #address-cells = <1>;
0607 #size-cells = <0>;
0608 compatible = "samsung,s3c2440-i2c";
0609 reg = <0x138B0000 0x100>;
0610 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0611 clocks = <&cmu CLK_I2C5>;
0612 clock-names = "i2c";
0613 pinctrl-names = "default";
0614 pinctrl-0 = <&i2c5_bus>;
0615 status = "disabled";
0616 };
0617
0618 i2c_6: i2c@138c0000 {
0619 #address-cells = <1>;
0620 #size-cells = <0>;
0621 compatible = "samsung,s3c2440-i2c";
0622 reg = <0x138C0000 0x100>;
0623 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0624 clocks = <&cmu CLK_I2C6>;
0625 clock-names = "i2c";
0626 pinctrl-names = "default";
0627 pinctrl-0 = <&i2c6_bus>;
0628 status = "disabled";
0629 };
0630
0631 i2c_7: i2c@138d0000 {
0632 #address-cells = <1>;
0633 #size-cells = <0>;
0634 compatible = "samsung,s3c2440-i2c";
0635 reg = <0x138D0000 0x100>;
0636 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0637 clocks = <&cmu CLK_I2C7>;
0638 clock-names = "i2c";
0639 pinctrl-names = "default";
0640 pinctrl-0 = <&i2c7_bus>;
0641 status = "disabled";
0642 };
0643
0644 spi_0: spi@13920000 {
0645 compatible = "samsung,exynos4210-spi";
0646 reg = <0x13920000 0x100>;
0647 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0648 dmas = <&pdma0 7>, <&pdma0 6>;
0649 dma-names = "tx", "rx";
0650 #address-cells = <1>;
0651 #size-cells = <0>;
0652 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
0653 clock-names = "spi", "spi_busclk0";
0654 samsung,spi-src-clk = <0>;
0655 pinctrl-names = "default";
0656 pinctrl-0 = <&spi0_bus>;
0657 status = "disabled";
0658 };
0659
0660 spi_1: spi@13930000 {
0661 compatible = "samsung,exynos4210-spi";
0662 reg = <0x13930000 0x100>;
0663 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0664 dmas = <&pdma1 7>, <&pdma1 6>;
0665 dma-names = "tx", "rx";
0666 #address-cells = <1>;
0667 #size-cells = <0>;
0668 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
0669 clock-names = "spi", "spi_busclk0";
0670 samsung,spi-src-clk = <0>;
0671 pinctrl-names = "default";
0672 pinctrl-0 = <&spi1_bus>;
0673 status = "disabled";
0674 };
0675
0676 i2s2: i2s@13970000 {
0677 compatible = "samsung,s3c6410-i2s";
0678 reg = <0x13970000 0x100>;
0679 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0680 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
0681 clock-names = "iis", "i2s_opclk0";
0682 dmas = <&pdma0 14>, <&pdma0 13>;
0683 dma-names = "tx", "rx";
0684 pinctrl-0 = <&i2s2_bus>;
0685 pinctrl-names = "default";
0686 status = "disabled";
0687 };
0688
0689 pwm: pwm@139d0000 {
0690 compatible = "samsung,exynos4210-pwm";
0691 reg = <0x139D0000 0x1000>;
0692 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0693 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0694 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0695 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0696 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0697 #pwm-cells = <3>;
0698 status = "disabled";
0699 };
0700
0701 ppmu_dmc0: ppmu@106a0000 {
0702 compatible = "samsung,exynos-ppmu";
0703 reg = <0x106a0000 0x2000>;
0704 status = "disabled";
0705 };
0706
0707 ppmu_dmc1: ppmu@106b0000 {
0708 compatible = "samsung,exynos-ppmu";
0709 reg = <0x106b0000 0x2000>;
0710 status = "disabled";
0711 };
0712
0713 ppmu_cpu: ppmu@106c0000 {
0714 compatible = "samsung,exynos-ppmu";
0715 reg = <0x106c0000 0x2000>;
0716 status = "disabled";
0717 };
0718
0719 ppmu_rightbus: ppmu@112a0000 {
0720 compatible = "samsung,exynos-ppmu";
0721 reg = <0x112a0000 0x2000>;
0722 clocks = <&cmu CLK_PPMURIGHT>;
0723 clock-names = "ppmu";
0724 status = "disabled";
0725 };
0726
0727 ppmu_leftbus: ppmu@116a0000 {
0728 compatible = "samsung,exynos-ppmu";
0729 reg = <0x116a0000 0x2000>;
0730 clocks = <&cmu CLK_PPMULEFT>;
0731 clock-names = "ppmu";
0732 status = "disabled";
0733 };
0734
0735 ppmu_camif: ppmu@11ac0000 {
0736 compatible = "samsung,exynos-ppmu";
0737 reg = <0x11ac0000 0x2000>;
0738 clocks = <&cmu CLK_PPMUCAMIF>;
0739 clock-names = "ppmu";
0740 status = "disabled";
0741 };
0742
0743 ppmu_lcd0: ppmu@11e40000 {
0744 compatible = "samsung,exynos-ppmu";
0745 reg = <0x11e40000 0x2000>;
0746 clocks = <&cmu CLK_PPMULCD0>;
0747 clock-names = "ppmu";
0748 status = "disabled";
0749 };
0750
0751 ppmu_fsys: ppmu@12630000 {
0752 compatible = "samsung,exynos-ppmu";
0753 reg = <0x12630000 0x2000>;
0754 clocks = <&cmu CLK_PPMUFILE>;
0755 clock-names = "ppmu";
0756 status = "disabled";
0757 };
0758
0759 ppmu_g3d: ppmu@13220000 {
0760 compatible = "samsung,exynos-ppmu";
0761 reg = <0x13220000 0x2000>;
0762 clocks = <&cmu CLK_PPMUG3D>;
0763 clock-names = "ppmu";
0764 status = "disabled";
0765 };
0766
0767 ppmu_mfc: ppmu@13660000 {
0768 compatible = "samsung,exynos-ppmu";
0769 reg = <0x13660000 0x2000>;
0770 clocks = <&cmu CLK_PPMUMFC_L>;
0771 clock-names = "ppmu";
0772 status = "disabled";
0773 };
0774
0775 bus_dmc: bus-dmc {
0776 compatible = "samsung,exynos-bus";
0777 clocks = <&cmu_dmc CLK_DIV_DMC>;
0778 clock-names = "bus";
0779 operating-points-v2 = <&bus_dmc_opp_table>;
0780 status = "disabled";
0781 };
0782
0783 bus_dmc_opp_table: opp-table1 {
0784 compatible = "operating-points-v2";
0785
0786 opp-50000000 {
0787 opp-hz = /bits/ 64 <50000000>;
0788 opp-microvolt = <800000>;
0789 };
0790 opp-100000000 {
0791 opp-hz = /bits/ 64 <100000000>;
0792 opp-microvolt = <800000>;
0793 };
0794 opp-134000000 {
0795 opp-hz = /bits/ 64 <134000000>;
0796 opp-microvolt = <800000>;
0797 };
0798 opp-200000000 {
0799 opp-hz = /bits/ 64 <200000000>;
0800 opp-microvolt = <825000>;
0801 };
0802 opp-400000000 {
0803 opp-hz = /bits/ 64 <400000000>;
0804 opp-microvolt = <875000>;
0805 };
0806 };
0807
0808 bus_leftbus: bus-leftbus {
0809 compatible = "samsung,exynos-bus";
0810 clocks = <&cmu CLK_DIV_GDL>;
0811 clock-names = "bus";
0812 operating-points-v2 = <&bus_leftbus_opp_table>;
0813 status = "disabled";
0814 };
0815
0816 bus_rightbus: bus-rightbus {
0817 compatible = "samsung,exynos-bus";
0818 clocks = <&cmu CLK_DIV_GDR>;
0819 clock-names = "bus";
0820 operating-points-v2 = <&bus_leftbus_opp_table>;
0821 status = "disabled";
0822 };
0823
0824 bus_lcd0: bus-lcd0 {
0825 compatible = "samsung,exynos-bus";
0826 clocks = <&cmu CLK_DIV_ACLK_160>;
0827 clock-names = "bus";
0828 operating-points-v2 = <&bus_leftbus_opp_table>;
0829 status = "disabled";
0830 };
0831
0832 bus_fsys: bus-fsys {
0833 compatible = "samsung,exynos-bus";
0834 clocks = <&cmu CLK_DIV_ACLK_200>;
0835 clock-names = "bus";
0836 operating-points-v2 = <&bus_leftbus_opp_table>;
0837 status = "disabled";
0838 };
0839
0840 bus_mcuisp: bus-mcuisp {
0841 compatible = "samsung,exynos-bus";
0842 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
0843 clock-names = "bus";
0844 operating-points-v2 = <&bus_mcuisp_opp_table>;
0845 status = "disabled";
0846 };
0847
0848 bus_isp: bus-isp {
0849 compatible = "samsung,exynos-bus";
0850 clocks = <&cmu CLK_DIV_ACLK_266>;
0851 clock-names = "bus";
0852 operating-points-v2 = <&bus_isp_opp_table>;
0853 status = "disabled";
0854 };
0855
0856 bus_peril: bus-peril {
0857 compatible = "samsung,exynos-bus";
0858 clocks = <&cmu CLK_DIV_ACLK_100>;
0859 clock-names = "bus";
0860 operating-points-v2 = <&bus_peril_opp_table>;
0861 status = "disabled";
0862 };
0863
0864 bus_mfc: bus-mfc {
0865 compatible = "samsung,exynos-bus";
0866 clocks = <&cmu CLK_SCLK_MFC>;
0867 clock-names = "bus";
0868 operating-points-v2 = <&bus_leftbus_opp_table>;
0869 status = "disabled";
0870 };
0871
0872 bus_leftbus_opp_table: opp-table2 {
0873 compatible = "operating-points-v2";
0874
0875 opp-50000000 {
0876 opp-hz = /bits/ 64 <50000000>;
0877 opp-microvolt = <900000>;
0878 };
0879 opp-80000000 {
0880 opp-hz = /bits/ 64 <80000000>;
0881 opp-microvolt = <900000>;
0882 };
0883 opp-100000000 {
0884 opp-hz = /bits/ 64 <100000000>;
0885 opp-microvolt = <1000000>;
0886 };
0887 opp-134000000 {
0888 opp-hz = /bits/ 64 <134000000>;
0889 opp-microvolt = <1000000>;
0890 };
0891 opp-200000000 {
0892 opp-hz = /bits/ 64 <200000000>;
0893 opp-microvolt = <1000000>;
0894 };
0895 };
0896
0897 bus_mcuisp_opp_table: opp-table3 {
0898 compatible = "operating-points-v2";
0899
0900 opp-50000000 {
0901 opp-hz = /bits/ 64 <50000000>;
0902 };
0903 opp-80000000 {
0904 opp-hz = /bits/ 64 <80000000>;
0905 };
0906 opp-100000000 {
0907 opp-hz = /bits/ 64 <100000000>;
0908 };
0909 opp-200000000 {
0910 opp-hz = /bits/ 64 <200000000>;
0911 };
0912 opp-400000000 {
0913 opp-hz = /bits/ 64 <400000000>;
0914 };
0915 };
0916
0917 bus_isp_opp_table: opp-table4 {
0918 compatible = "operating-points-v2";
0919
0920 opp-50000000 {
0921 opp-hz = /bits/ 64 <50000000>;
0922 };
0923 opp-80000000 {
0924 opp-hz = /bits/ 64 <80000000>;
0925 };
0926 opp-100000000 {
0927 opp-hz = /bits/ 64 <100000000>;
0928 };
0929 opp-200000000 {
0930 opp-hz = /bits/ 64 <200000000>;
0931 };
0932 opp-300000000 {
0933 opp-hz = /bits/ 64 <300000000>;
0934 };
0935 };
0936
0937 bus_peril_opp_table: opp-table5 {
0938 compatible = "operating-points-v2";
0939
0940 opp-50000000 {
0941 opp-hz = /bits/ 64 <50000000>;
0942 };
0943 opp-80000000 {
0944 opp-hz = /bits/ 64 <80000000>;
0945 };
0946 opp-100000000 {
0947 opp-hz = /bits/ 64 <100000000>;
0948 };
0949 };
0950 };
0951 };
0952
0953 #include "exynos3250-pinctrl.dtsi"
0954 #include "exynos-syscon-restart.dtsi"
