0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
0004 *
0005 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 *
0008 * Device tree source file for Samsung's ARTIK5 evaluation board
0009 * which is based on Samsung Exynos3250 SoC.
0010 */
0011
0012 /dts-v1/;
0013 #include "exynos3250-artik5.dtsi"
0014
0015 / {
0016 model = "Samsung ARTIK5 evaluation board";
0017 compatible = "samsung,artik5-eval", "samsung,artik5",
0018 "samsung,exynos3250", "samsung,exynos3";
0019 };
0020
0021 &mshc_2 {
0022 cap-sd-highspeed;
0023 disable-wp;
0024 vqmmc-supply = <&ldo3_reg>;
0025 card-detect-delay = <200>;
0026 clock-frequency = <100000000>;
0027 max-frequency = <100000000>;
0028 samsung,dw-mshc-ciu-div = <1>;
0029 samsung,dw-mshc-sdr-timing = <0 1>;
0030 samsung,dw-mshc-ddr-timing = <1 2>;
0031 pinctrl-names = "default";
0032 pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
0033 bus-width = <4>;
0034 status = "okay";
0035 };
0036
0037 &serial_2 {
0038 status = "okay";
0039 };
0040
0041 &spi_0 {
0042 status = "okay";
0043 cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>;
0044
0045 assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
0046 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
0047 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
0048 <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
0049 <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
0050 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
0051
0052 ethernet@0 {
0053 compatible = "asix,ax88796c";
0054 reg = <0x0>;
0055 local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */
0056 interrupt-parent = <&gpx2>;
0057 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
0058 spi-max-frequency = <40000000>;
0059 reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>;
0060
0061 controller-data {
0062 samsung,spi-feedback-delay = <2>;
0063 };
0064 };
0065 };
