0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002
0003 #include <dt-bindings/interrupt-controller/irq.h>
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/gpio/gpio.h>
0006 #include <dt-bindings/clock/en7523-clk.h>
0007
0008 / {
0009 interrupt-parent = <&gic>;
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 reserved-memory {
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 ranges;
0017
0018 npu_binary@84000000 {
0019 no-map;
0020 reg = <0x84000000 0xA00000>;
0021 };
0022
0023 npu_flag@84B0000 {
0024 no-map;
0025 reg = <0x84B00000 0x100000>;
0026 };
0027
0028 npu_pkt@85000000 {
0029 no-map;
0030 reg = <0x85000000 0x1A00000>;
0031 };
0032
0033 npu_phyaddr@86B00000 {
0034 no-map;
0035 reg = <0x86B00000 0x100000>;
0036 };
0037
0038 npu_rxdesc@86D00000 {
0039 no-map;
0040 reg = <0x86D00000 0x100000>;
0041 };
0042 };
0043
0044 psci {
0045 compatible = "arm,psci-0.2";
0046 method = "smc";
0047 };
0048
0049 cpus {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 cpu-map {
0054 cluster0 {
0055 core0 {
0056 cpu = <&cpu0>;
0057 };
0058 core1 {
0059 cpu = <&cpu1>;
0060 };
0061 };
0062 };
0063
0064 cpu0: cpu@0 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a53";
0067 reg = <0x0>;
0068 enable-method = "psci";
0069 clock-frequency = <80000000>;
0070 next-level-cache = <&L2_0>;
0071 };
0072
0073 cpu1: cpu@1 {
0074 device_type = "cpu";
0075 compatible = "arm,cortex-a53";
0076 reg = <0x1>;
0077 enable-method = "psci";
0078 clock-frequency = <80000000>;
0079 next-level-cache = <&L2_0>;
0080 };
0081
0082 L2_0: l2-cache0 {
0083 compatible = "cache";
0084 };
0085 };
0086
0087 scu: system-controller@1fa20000 {
0088 compatible = "airoha,en7523-scu";
0089 reg = <0x1fa20000 0x400>,
0090 <0x1fb00000 0x1000>;
0091 #clock-cells = <1>;
0092 };
0093
0094 gic: interrupt-controller@9000000 {
0095 compatible = "arm,gic-v3";
0096 interrupt-controller;
0097 #interrupt-cells = <3>;
0098 #address-cells = <1>;
0099 #size-cells = <1>;
0100 reg = <0x09000000 0x20000>,
0101 <0x09080000 0x80000>,
0102 <0x09400000 0x2000>,
0103 <0x09500000 0x2000>,
0104 <0x09600000 0x20000>;
0105 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
0106 };
0107
0108 timer {
0109 compatible = "arm,armv8-timer";
0110 interrupt-parent = <&gic>;
0111 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0112 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0113 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0114 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0115 };
0116
0117 uart1: serial@1fbf0000 {
0118 compatible = "ns16550";
0119 reg = <0x1fbf0000 0x30>;
0120 reg-io-width = <4>;
0121 reg-shift = <2>;
0122 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0123 clock-frequency = <1843200>;
0124 status = "okay";
0125 };
0126
0127 gpio0: gpio@1fbf0200 {
0128 compatible = "airoha,en7523-gpio";
0129 reg = <0x1fbf0204 0x4>,
0130 <0x1fbf0200 0x4>,
0131 <0x1fbf0220 0x4>,
0132 <0x1fbf0214 0x4>;
0133 gpio-controller;
0134 #gpio-cells = <2>;
0135 };
0136
0137 gpio1: gpio@1fbf0270 {
0138 compatible = "airoha,en7523-gpio";
0139 reg = <0x1fbf0270 0x4>,
0140 <0x1fbf0260 0x4>,
0141 <0x1fbf0264 0x4>,
0142 <0x1fbf0278 0x4>;
0143 gpio-controller;
0144 #gpio-cells = <2>;
0145 };
0146
0147 pcie0: pcie@1fa91000 {
0148 compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
0149 device_type = "pci";
0150 reg = <0x1fa91000 0x1000>;
0151 reg-names = "port0";
0152 linux,pci-domain = <0>;
0153 #address-cells = <3>;
0154 #size-cells = <2>;
0155 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0156 interrupt-names = "pcie_irq";
0157 clocks = <&scu EN7523_CLK_PCIE>;
0158 clock-names = "sys_ck0";
0159 bus-range = <0x00 0xff>;
0160 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
0161 status = "disabled";
0162
0163 #interrupt-cells = <1>;
0164 interrupt-map-mask = <0 0 0 7>;
0165 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0166 <0 0 0 2 &pcie_intc0 1>,
0167 <0 0 0 3 &pcie_intc0 2>,
0168 <0 0 0 4 &pcie_intc0 3>;
0169 pcie_intc0: interrupt-controller {
0170 interrupt-controller;
0171 #address-cells = <0>;
0172 #interrupt-cells = <1>;
0173 };
0174 };
0175
0176 pcie1: pcie@1fa92000 {
0177 compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
0178 device_type = "pci";
0179 reg = <0x1fa92000 0x1000>;
0180 reg-names = "port1";
0181 linux,pci-domain = <1>;
0182 #address-cells = <3>;
0183 #size-cells = <2>;
0184 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0185 interrupt-names = "pcie_irq";
0186 clocks = <&scu EN7523_CLK_PCIE>;
0187 clock-names = "sys_ck1";
0188 bus-range = <0x00 0xff>;
0189 ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
0190 status = "disabled";
0191
0192 #interrupt-cells = <1>;
0193 interrupt-map-mask = <0 0 0 7>;
0194 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
0195 <0 0 0 2 &pcie_intc1 1>,
0196 <0 0 0 3 &pcie_intc1 2>,
0197 <0 0 0 4 &pcie_intc1 3>;
0198 pcie_intc1: interrupt-controller {
0199 interrupt-controller;
0200 #address-cells = <0>;
0201 #interrupt-cells = <1>;
0202 };
0203 };
0204 };
