0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the Emma Mobile EV2 SoC
0004 *
0005 * Copyright (C) 2012 Renesas Solutions Corp.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010
0011 / {
0012 compatible = "renesas,emev2";
0013 interrupt-parent = <&gic>;
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 aliases {
0018 gpio0 = &gpio0;
0019 gpio1 = &gpio1;
0020 gpio2 = &gpio2;
0021 gpio3 = &gpio3;
0022 gpio4 = &gpio4;
0023 i2c0 = &iic0;
0024 i2c1 = &iic1;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 cpu0: cpu@0 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a9";
0034 reg = <0>;
0035 clock-frequency = <533000000>;
0036 };
0037 cpu1: cpu@1 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a9";
0040 reg = <1>;
0041 clock-frequency = <533000000>;
0042 };
0043 };
0044
0045 gic: interrupt-controller@e0020000 {
0046 compatible = "arm,pl390";
0047 interrupt-controller;
0048 #interrupt-cells = <3>;
0049 reg = <0xe0028000 0x1000>,
0050 <0xe0020000 0x0100>;
0051 };
0052
0053 pmu {
0054 compatible = "arm,cortex-a9-pmu";
0055 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0056 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0057 interrupt-affinity = <&cpu0>, <&cpu1>;
0058 };
0059
0060 clocks@e0110000 {
0061 compatible = "renesas,emev2-smu";
0062 reg = <0xe0110000 0x10000>;
0063 #address-cells = <2>;
0064 #size-cells = <0>;
0065
0066 c32ki: c32ki {
0067 compatible = "fixed-clock";
0068 clock-frequency = <32768>;
0069 #clock-cells = <0>;
0070 };
0071 iic0_sclkdiv: iic0_sclkdiv@624,0 {
0072 compatible = "renesas,emev2-smu-clkdiv";
0073 reg = <0x624 0>;
0074 clocks = <&pll3_fo>;
0075 #clock-cells = <0>;
0076 };
0077 iic0_sclk: iic0_sclk@48c,1 {
0078 compatible = "renesas,emev2-smu-gclk";
0079 reg = <0x48c 1>;
0080 clocks = <&iic0_sclkdiv>;
0081 #clock-cells = <0>;
0082 };
0083 iic1_sclkdiv: iic1_sclkdiv@624,16 {
0084 compatible = "renesas,emev2-smu-clkdiv";
0085 reg = <0x624 16>;
0086 clocks = <&pll3_fo>;
0087 #clock-cells = <0>;
0088 };
0089 iic1_sclk: iic1_sclk@490,1 {
0090 compatible = "renesas,emev2-smu-gclk";
0091 reg = <0x490 1>;
0092 clocks = <&iic1_sclkdiv>;
0093 #clock-cells = <0>;
0094 };
0095 pll3_fo: pll3_fo {
0096 compatible = "fixed-factor-clock";
0097 clocks = <&c32ki>;
0098 clock-div = <1>;
0099 clock-mult = <7000>;
0100 #clock-cells = <0>;
0101 };
0102 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
0103 compatible = "renesas,emev2-smu-clkdiv";
0104 reg = <0x610 0>;
0105 clocks = <&pll3_fo>;
0106 #clock-cells = <0>;
0107 };
0108 usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
0109 compatible = "renesas,emev2-smu-clkdiv";
0110 reg = <0x65c 0>;
0111 clocks = <&pll3_fo>;
0112 #clock-cells = <0>;
0113 };
0114 usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
0115 compatible = "renesas,emev2-smu-clkdiv";
0116 reg = <0x65c 16>;
0117 clocks = <&pll3_fo>;
0118 #clock-cells = <0>;
0119 };
0120 usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
0121 compatible = "renesas,emev2-smu-clkdiv";
0122 reg = <0x660 0>;
0123 clocks = <&pll3_fo>;
0124 #clock-cells = <0>;
0125 };
0126 usia_u0_sclk: usia_u0_sclk@4a0,1 {
0127 compatible = "renesas,emev2-smu-gclk";
0128 reg = <0x4a0 1>;
0129 clocks = <&usia_u0_sclkdiv>;
0130 #clock-cells = <0>;
0131 };
0132 usib_u1_sclk: usib_u1_sclk@4b8,1 {
0133 compatible = "renesas,emev2-smu-gclk";
0134 reg = <0x4b8 1>;
0135 clocks = <&usib_u1_sclkdiv>;
0136 #clock-cells = <0>;
0137 };
0138 usib_u2_sclk: usib_u2_sclk@4bc,1 {
0139 compatible = "renesas,emev2-smu-gclk";
0140 reg = <0x4bc 1>;
0141 clocks = <&usib_u2_sclkdiv>;
0142 #clock-cells = <0>;
0143 };
0144 usib_u3_sclk: usib_u3_sclk@4c0,1 {
0145 compatible = "renesas,emev2-smu-gclk";
0146 reg = <0x4c0 1>;
0147 clocks = <&usib_u3_sclkdiv>;
0148 #clock-cells = <0>;
0149 };
0150 sti_sclk: sti_sclk@528,1 {
0151 compatible = "renesas,emev2-smu-gclk";
0152 reg = <0x528 1>;
0153 clocks = <&c32ki>;
0154 #clock-cells = <0>;
0155 };
0156 };
0157
0158 timer@e0180000 {
0159 compatible = "renesas,em-sti";
0160 reg = <0xe0180000 0x54>;
0161 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0162 clocks = <&sti_sclk>;
0163 clock-names = "sclk";
0164 };
0165
0166 uart0: serial@e1020000 {
0167 compatible = "renesas,em-uart";
0168 reg = <0xe1020000 0x38>;
0169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0170 clocks = <&usia_u0_sclk>;
0171 clock-names = "sclk";
0172 };
0173
0174 uart1: serial@e1030000 {
0175 compatible = "renesas,em-uart";
0176 reg = <0xe1030000 0x38>;
0177 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0178 clocks = <&usib_u1_sclk>;
0179 clock-names = "sclk";
0180 };
0181
0182 uart2: serial@e1040000 {
0183 compatible = "renesas,em-uart";
0184 reg = <0xe1040000 0x38>;
0185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0186 clocks = <&usib_u2_sclk>;
0187 clock-names = "sclk";
0188 };
0189
0190 uart3: serial@e1050000 {
0191 compatible = "renesas,em-uart";
0192 reg = <0xe1050000 0x38>;
0193 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0194 clocks = <&usib_u3_sclk>;
0195 clock-names = "sclk";
0196 };
0197
0198 pfc: pinctrl@e0140200 {
0199 compatible = "renesas,pfc-emev2";
0200 reg = <0xe0140200 0x100>;
0201 };
0202
0203 gpio0: gpio@e0050000 {
0204 compatible = "renesas,em-gio";
0205 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
0206 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0208 gpio-controller;
0209 gpio-ranges = <&pfc 0 0 32>;
0210 #gpio-cells = <2>;
0211 ngpios = <32>;
0212 interrupt-controller;
0213 #interrupt-cells = <2>;
0214 };
0215
0216 gpio1: gpio@e0050080 {
0217 compatible = "renesas,em-gio";
0218 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
0219 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0221 gpio-controller;
0222 gpio-ranges = <&pfc 0 32 32>;
0223 #gpio-cells = <2>;
0224 ngpios = <32>;
0225 interrupt-controller;
0226 #interrupt-cells = <2>;
0227 };
0228
0229 gpio2: gpio@e0050100 {
0230 compatible = "renesas,em-gio";
0231 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
0232 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0233 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0234 gpio-controller;
0235 gpio-ranges = <&pfc 0 64 32>;
0236 #gpio-cells = <2>;
0237 ngpios = <32>;
0238 interrupt-controller;
0239 #interrupt-cells = <2>;
0240 };
0241
0242 gpio3: gpio@e0050180 {
0243 compatible = "renesas,em-gio";
0244 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
0245 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0246 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0247 gpio-controller;
0248 gpio-ranges = <&pfc 0 96 32>;
0249 #gpio-cells = <2>;
0250 ngpios = <32>;
0251 interrupt-controller;
0252 #interrupt-cells = <2>;
0253 };
0254
0255 gpio4: gpio@e0050200 {
0256 compatible = "renesas,em-gio";
0257 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
0258 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
0259 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0260 gpio-controller;
0261 gpio-ranges = <&pfc 0 128 31>;
0262 #gpio-cells = <2>;
0263 ngpios = <31>;
0264 interrupt-controller;
0265 #interrupt-cells = <2>;
0266 };
0267
0268 iic0: i2c@e0070000 {
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271 compatible = "renesas,iic-emev2";
0272 reg = <0xe0070000 0x28>;
0273 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
0274 clocks = <&iic0_sclk>;
0275 clock-names = "sclk";
0276 status = "disabled";
0277 };
0278
0279 iic1: i2c@e10a0000 {
0280 #address-cells = <1>;
0281 #size-cells = <0>;
0282 compatible = "renesas,iic-emev2";
0283 reg = <0xe10a0000 0x28>;
0284 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
0285 clocks = <&iic1_sclk>;
0286 clock-names = "sclk";
0287 status = "disabled";
0288 };
0289 };
