0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright 2011-2012 Calxeda, Inc.
0004 */
0005
0006 / {
0007 chosen {
0008 bootargs = "console=ttyAMA0";
0009 };
0010
0011 psci {
0012 compatible = "arm,psci";
0013 method = "smc";
0014 cpu_suspend = <0x84000002>;
0015 cpu_off = <0x84000004>;
0016 cpu_on = <0x84000006>;
0017 };
0018
0019 soc {
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022 compatible = "simple-bus";
0023 interrupt-parent = <&intc>;
0024
0025 sata@ffe08000 {
0026 compatible = "calxeda,hb-ahci";
0027 reg = <0xffe08000 0x10000>;
0028 interrupts = <0 83 4>;
0029 dma-coherent;
0030 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
0031 <&combophy0 1>, <&combophy0 2>,
0032 <&combophy0 3>;
0033 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
0034 <&gpioh 7 1>;
0035 calxeda,led-order = <4 0 1 2 3>;
0036 };
0037
0038 sdhci@ffe0e000 {
0039 compatible = "calxeda,hb-sdhci";
0040 reg = <0xffe0e000 0x1000>;
0041 interrupts = <0 90 4>;
0042 clocks = <&eclk>;
0043 status = "disabled";
0044 };
0045
0046 ipc@fff20000 {
0047 compatible = "arm,pl320", "arm,primecell";
0048 reg = <0xfff20000 0x1000>;
0049 interrupts = <0 7 4>;
0050 clocks = <&pclk>;
0051 clock-names = "apb_pclk";
0052 };
0053
0054 gpioe: gpio@fff30000 {
0055 #gpio-cells = <2>;
0056 compatible = "arm,pl061", "arm,primecell";
0057 gpio-controller;
0058 reg = <0xfff30000 0x1000>;
0059 interrupts = <0 14 4>;
0060 clocks = <&pclk>;
0061 clock-names = "apb_pclk";
0062 status = "disabled";
0063 };
0064
0065 gpiof: gpio@fff31000 {
0066 #gpio-cells = <2>;
0067 compatible = "arm,pl061", "arm,primecell";
0068 gpio-controller;
0069 reg = <0xfff31000 0x1000>;
0070 interrupts = <0 15 4>;
0071 clocks = <&pclk>;
0072 clock-names = "apb_pclk";
0073 status = "disabled";
0074 };
0075
0076 gpiog: gpio@fff32000 {
0077 #gpio-cells = <2>;
0078 compatible = "arm,pl061", "arm,primecell";
0079 gpio-controller;
0080 reg = <0xfff32000 0x1000>;
0081 interrupts = <0 16 4>;
0082 clocks = <&pclk>;
0083 clock-names = "apb_pclk";
0084 status = "disabled";
0085 };
0086
0087 gpioh: gpio@fff33000 {
0088 #gpio-cells = <2>;
0089 compatible = "arm,pl061", "arm,primecell";
0090 gpio-controller;
0091 reg = <0xfff33000 0x1000>;
0092 interrupts = <0 17 4>;
0093 clocks = <&pclk>;
0094 clock-names = "apb_pclk";
0095 status = "disabled";
0096 };
0097
0098 timer@fff34000 {
0099 compatible = "arm,sp804", "arm,primecell";
0100 reg = <0xfff34000 0x1000>;
0101 interrupts = <0 18 4>;
0102 clocks = <&pclk>;
0103 clock-names = "apb_pclk";
0104 };
0105
0106 rtc@fff35000 {
0107 compatible = "arm,pl031", "arm,primecell";
0108 reg = <0xfff35000 0x1000>;
0109 interrupts = <0 19 4>;
0110 clocks = <&pclk>;
0111 clock-names = "apb_pclk";
0112 };
0113
0114 serial@fff36000 {
0115 compatible = "arm,pl011", "arm,primecell";
0116 reg = <0xfff36000 0x1000>;
0117 interrupts = <0 20 4>;
0118 clocks = <&pclk>, <&pclk>;
0119 clock-names = "uartclk", "apb_pclk";
0120 };
0121
0122 smic@fff3a000 {
0123 compatible = "ipmi-smic";
0124 device_type = "ipmi";
0125 reg = <0xfff3a000 0x1000>;
0126 interrupts = <0 24 4>;
0127 reg-size = <4>;
0128 reg-spacing = <4>;
0129 };
0130
0131 sregs@fff3c000 {
0132 compatible = "calxeda,hb-sregs";
0133 reg = <0xfff3c000 0x1000>;
0134
0135 clocks {
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138
0139 osc: oscillator {
0140 #clock-cells = <0>;
0141 compatible = "fixed-clock";
0142 clock-frequency = <33333000>;
0143 };
0144
0145 ddrpll: ddrpll {
0146 #clock-cells = <0>;
0147 compatible = "calxeda,hb-pll-clock";
0148 clocks = <&osc>;
0149 reg = <0x108>;
0150 };
0151
0152 a9pll: a9pll {
0153 #clock-cells = <0>;
0154 compatible = "calxeda,hb-pll-clock";
0155 clocks = <&osc>;
0156 reg = <0x100>;
0157 };
0158
0159 a9periphclk: a9periphclk {
0160 #clock-cells = <0>;
0161 compatible = "calxeda,hb-a9periph-clock";
0162 clocks = <&a9pll>;
0163 reg = <0x104>;
0164 };
0165
0166 a9bclk: a9bclk {
0167 #clock-cells = <0>;
0168 compatible = "calxeda,hb-a9bus-clock";
0169 clocks = <&a9pll>;
0170 reg = <0x104>;
0171 };
0172
0173 emmcpll: emmcpll {
0174 #clock-cells = <0>;
0175 compatible = "calxeda,hb-pll-clock";
0176 clocks = <&osc>;
0177 reg = <0x10C>;
0178 };
0179
0180 eclk: eclk {
0181 #clock-cells = <0>;
0182 compatible = "calxeda,hb-emmc-clock";
0183 clocks = <&emmcpll>;
0184 reg = <0x114>;
0185 };
0186
0187 pclk: pclk {
0188 #clock-cells = <0>;
0189 compatible = "fixed-clock";
0190 clock-frequency = <150000000>;
0191 };
0192 };
0193 };
0194
0195 dma@fff3d000 {
0196 compatible = "arm,pl330", "arm,primecell";
0197 reg = <0xfff3d000 0x1000>;
0198 interrupts = <0 92 4>;
0199 clocks = <&pclk>;
0200 clock-names = "apb_pclk";
0201 };
0202
0203 ethernet@fff50000 {
0204 compatible = "calxeda,hb-xgmac";
0205 reg = <0xfff50000 0x1000>;
0206 interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
0207 dma-coherent;
0208 };
0209
0210 ethernet@fff51000 {
0211 compatible = "calxeda,hb-xgmac";
0212 reg = <0xfff51000 0x1000>;
0213 interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
0214 dma-coherent;
0215 };
0216
0217 combophy0: combo-phy@fff58000 {
0218 compatible = "calxeda,hb-combophy";
0219 #phy-cells = <1>;
0220 reg = <0xfff58000 0x1000>;
0221 phydev = <5>;
0222 };
0223
0224 combophy5: combo-phy@fff5d000 {
0225 compatible = "calxeda,hb-combophy";
0226 #phy-cells = <1>;
0227 reg = <0xfff5d000 0x1000>;
0228 phydev = <31>;
0229 };
0230 };
0231 };
