0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for DRA7xx clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm_core_aon_clocks {
0008 atl_clkin0_ck: clock-atl-clkin0 {
0009 #clock-cells = <0>;
0010 compatible = "ti,dra7-atl-clock";
0011 clock-output-names = "atl_clkin0_ck";
0012 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
0013 };
0014
0015 atl_clkin1_ck: clock-atl-clkin1 {
0016 #clock-cells = <0>;
0017 compatible = "ti,dra7-atl-clock";
0018 clock-output-names = "atl_clkin1_ck";
0019 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
0020 };
0021
0022 atl_clkin2_ck: clock-atl-clkin2 {
0023 #clock-cells = <0>;
0024 compatible = "ti,dra7-atl-clock";
0025 clock-output-names = "atl_clkin2_ck";
0026 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
0027 };
0028
0029 atl_clkin3_ck: clock-atl-clkin3 {
0030 #clock-cells = <0>;
0031 compatible = "ti,dra7-atl-clock";
0032 clock-output-names = "atl_clkin3_ck";
0033 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
0034 };
0035
0036 hdmi_clkin_ck: clock-hdmi-clkin {
0037 #clock-cells = <0>;
0038 compatible = "fixed-clock";
0039 clock-output-names = "hdmi_clkin_ck";
0040 clock-frequency = <0>;
0041 };
0042
0043 mlb_clkin_ck: clock-mlb-clkin {
0044 #clock-cells = <0>;
0045 compatible = "fixed-clock";
0046 clock-output-names = "mlb_clkin_ck";
0047 clock-frequency = <0>;
0048 };
0049
0050 mlbp_clkin_ck: clock-mlbp-clkin {
0051 #clock-cells = <0>;
0052 compatible = "fixed-clock";
0053 clock-output-names = "mlbp_clkin_ck";
0054 clock-frequency = <0>;
0055 };
0056
0057 pciesref_acs_clk_ck: clock-pciesref-acs {
0058 #clock-cells = <0>;
0059 compatible = "fixed-clock";
0060 clock-output-names = "pciesref_acs_clk_ck";
0061 clock-frequency = <100000000>;
0062 };
0063
0064 ref_clkin0_ck: clock-ref-clkin0 {
0065 #clock-cells = <0>;
0066 compatible = "fixed-clock";
0067 clock-output-names = "ref_clkin0_ck";
0068 clock-frequency = <0>;
0069 };
0070
0071 ref_clkin1_ck: clock-ref-clkin1 {
0072 #clock-cells = <0>;
0073 compatible = "fixed-clock";
0074 clock-output-names = "ref_clkin1_ck";
0075 clock-frequency = <0>;
0076 };
0077
0078 ref_clkin2_ck: clock-ref-clkin2 {
0079 #clock-cells = <0>;
0080 compatible = "fixed-clock";
0081 clock-output-names = "ref_clkin2_ck";
0082 clock-frequency = <0>;
0083 };
0084
0085 ref_clkin3_ck: clock-ref-clkin3 {
0086 #clock-cells = <0>;
0087 compatible = "fixed-clock";
0088 clock-output-names = "ref_clkin3_ck";
0089 clock-frequency = <0>;
0090 };
0091
0092 rmii_clk_ck: clock-rmii {
0093 #clock-cells = <0>;
0094 compatible = "fixed-clock";
0095 clock-output-names = "rmii_clk_ck";
0096 clock-frequency = <0>;
0097 };
0098
0099 sdvenc_clkin_ck: clock-sdvenc-clkin {
0100 #clock-cells = <0>;
0101 compatible = "fixed-clock";
0102 clock-output-names = "sdvenc_clkin_ck";
0103 clock-frequency = <0>;
0104 };
0105
0106 secure_32k_clk_src_ck: clock-secure-32k-clk-src {
0107 #clock-cells = <0>;
0108 compatible = "fixed-clock";
0109 clock-output-names = "secure_32k_clk_src_ck";
0110 clock-frequency = <32768>;
0111 };
0112
0113 sys_clk32_crystal_ck: clock-sys-clk32-crystal {
0114 #clock-cells = <0>;
0115 compatible = "fixed-clock";
0116 clock-output-names = "sys_clk32_crystal_ck";
0117 clock-frequency = <32768>;
0118 };
0119
0120 sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
0121 #clock-cells = <0>;
0122 compatible = "fixed-factor-clock";
0123 clock-output-names = "sys_clk32_pseudo_ck";
0124 clocks = <&sys_clkin1>;
0125 clock-mult = <1>;
0126 clock-div = <610>;
0127 };
0128
0129 virt_12000000_ck: clock-virt-12000000 {
0130 #clock-cells = <0>;
0131 compatible = "fixed-clock";
0132 clock-output-names = "virt_12000000_ck";
0133 clock-frequency = <12000000>;
0134 };
0135
0136 virt_13000000_ck: clock-virt-13000000 {
0137 #clock-cells = <0>;
0138 compatible = "fixed-clock";
0139 clock-output-names = "virt_13000000_ck";
0140 clock-frequency = <13000000>;
0141 };
0142
0143 virt_16800000_ck: clock-virt-16800000 {
0144 #clock-cells = <0>;
0145 compatible = "fixed-clock";
0146 clock-output-names = "virt_16800000_ck";
0147 clock-frequency = <16800000>;
0148 };
0149
0150 virt_19200000_ck: clock-virt-19200000 {
0151 #clock-cells = <0>;
0152 compatible = "fixed-clock";
0153 clock-output-names = "virt_19200000_ck";
0154 clock-frequency = <19200000>;
0155 };
0156
0157 virt_20000000_ck: clock-virt-20000000 {
0158 #clock-cells = <0>;
0159 compatible = "fixed-clock";
0160 clock-output-names = "virt_20000000_ck";
0161 clock-frequency = <20000000>;
0162 };
0163
0164 virt_26000000_ck: clock-virt-26000000 {
0165 #clock-cells = <0>;
0166 compatible = "fixed-clock";
0167 clock-output-names = "virt_26000000_ck";
0168 clock-frequency = <26000000>;
0169 };
0170
0171 virt_27000000_ck: clock-virt-27000000 {
0172 #clock-cells = <0>;
0173 compatible = "fixed-clock";
0174 clock-output-names = "virt_27000000_ck";
0175 clock-frequency = <27000000>;
0176 };
0177
0178 virt_38400000_ck: clock-virt-38400000 {
0179 #clock-cells = <0>;
0180 compatible = "fixed-clock";
0181 clock-output-names = "virt_38400000_ck";
0182 clock-frequency = <38400000>;
0183 };
0184
0185 sys_clkin2: clock-sys-clkin2 {
0186 #clock-cells = <0>;
0187 compatible = "fixed-clock";
0188 clock-output-names = "sys_clkin2";
0189 clock-frequency = <22579200>;
0190 };
0191
0192 usb_otg_clkin_ck: clock-usb-otg-clkin {
0193 #clock-cells = <0>;
0194 compatible = "fixed-clock";
0195 clock-output-names = "usb_otg_clkin_ck";
0196 clock-frequency = <0>;
0197 };
0198
0199 video1_clkin_ck: clock-video1-clkin {
0200 #clock-cells = <0>;
0201 compatible = "fixed-clock";
0202 clock-output-names = "video1_clkin_ck";
0203 clock-frequency = <0>;
0204 };
0205
0206 video1_m2_clkin_ck: clock-video1-m2-clkin {
0207 #clock-cells = <0>;
0208 compatible = "fixed-clock";
0209 clock-output-names = "video1_m2_clkin_ck";
0210 clock-frequency = <0>;
0211 };
0212
0213 video2_clkin_ck: clock-video2-clkin {
0214 #clock-cells = <0>;
0215 compatible = "fixed-clock";
0216 clock-output-names = "video2_clkin_ck";
0217 clock-frequency = <0>;
0218 };
0219
0220 video2_m2_clkin_ck: clock-video2-m2-clkin {
0221 #clock-cells = <0>;
0222 compatible = "fixed-clock";
0223 clock-output-names = "video2_m2_clkin_ck";
0224 clock-frequency = <0>;
0225 };
0226
0227 dpll_abe_ck: clock@1e0 {
0228 #clock-cells = <0>;
0229 compatible = "ti,omap4-dpll-m4xen-clock";
0230 clock-output-names = "dpll_abe_ck";
0231 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
0232 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
0233 };
0234
0235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
0236 #clock-cells = <0>;
0237 compatible = "ti,omap4-dpll-x2-clock";
0238 clock-output-names = "dpll_abe_x2_ck";
0239 clocks = <&dpll_abe_ck>;
0240 };
0241
0242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
0243 #clock-cells = <0>;
0244 compatible = "ti,divider-clock";
0245 clock-output-names = "dpll_abe_m2x2_ck";
0246 clocks = <&dpll_abe_x2_ck>;
0247 ti,max-div = <31>;
0248 ti,autoidle-shift = <8>;
0249 reg = <0x01f0>;
0250 ti,index-starts-at-one;
0251 ti,invert-autoidle-bit;
0252 };
0253
0254 abe_clk: clock-abe@108 {
0255 #clock-cells = <0>;
0256 compatible = "ti,divider-clock";
0257 clock-output-names = "abe_clk";
0258 clocks = <&dpll_abe_m2x2_ck>;
0259 ti,max-div = <4>;
0260 reg = <0x0108>;
0261 ti,index-power-of-two;
0262 };
0263
0264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
0265 #clock-cells = <0>;
0266 compatible = "ti,divider-clock";
0267 clock-output-names = "dpll_abe_m2_ck";
0268 clocks = <&dpll_abe_ck>;
0269 ti,max-div = <31>;
0270 ti,autoidle-shift = <8>;
0271 reg = <0x01f0>;
0272 ti,index-starts-at-one;
0273 ti,invert-autoidle-bit;
0274 };
0275
0276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
0277 #clock-cells = <0>;
0278 compatible = "ti,divider-clock";
0279 clock-output-names = "dpll_abe_m3x2_ck";
0280 clocks = <&dpll_abe_x2_ck>;
0281 ti,max-div = <31>;
0282 ti,autoidle-shift = <8>;
0283 reg = <0x01f4>;
0284 ti,index-starts-at-one;
0285 ti,invert-autoidle-bit;
0286 };
0287
0288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
0289 #clock-cells = <0>;
0290 compatible = "ti,mux-clock";
0291 clock-output-names = "dpll_core_byp_mux";
0292 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
0293 ti,bit-shift = <23>;
0294 reg = <0x012c>;
0295 };
0296
0297 dpll_core_ck: clock@120 {
0298 #clock-cells = <0>;
0299 compatible = "ti,omap4-dpll-core-clock";
0300 clock-output-names = "dpll_core_ck";
0301 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
0302 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
0303 };
0304
0305 dpll_core_x2_ck: clock-dpll-core-x2 {
0306 #clock-cells = <0>;
0307 compatible = "ti,omap4-dpll-x2-clock";
0308 clock-output-names = "dpll_core_x2_ck";
0309 clocks = <&dpll_core_ck>;
0310 };
0311
0312 dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
0313 #clock-cells = <0>;
0314 compatible = "ti,divider-clock";
0315 clock-output-names = "dpll_core_h12x2_ck";
0316 clocks = <&dpll_core_x2_ck>;
0317 ti,max-div = <63>;
0318 ti,autoidle-shift = <8>;
0319 reg = <0x013c>;
0320 ti,index-starts-at-one;
0321 ti,invert-autoidle-bit;
0322 };
0323
0324 mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
0325 #clock-cells = <0>;
0326 compatible = "fixed-factor-clock";
0327 clock-output-names = "mpu_dpll_hs_clk_div";
0328 clocks = <&dpll_core_h12x2_ck>;
0329 clock-mult = <1>;
0330 clock-div = <1>;
0331 };
0332
0333 dpll_mpu_ck: clock@160 {
0334 #clock-cells = <0>;
0335 compatible = "ti,omap5-mpu-dpll-clock";
0336 clock-output-names = "dpll_mpu_ck";
0337 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
0338 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
0339 };
0340
0341 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
0342 #clock-cells = <0>;
0343 compatible = "ti,divider-clock";
0344 clock-output-names = "dpll_mpu_m2_ck";
0345 clocks = <&dpll_mpu_ck>;
0346 ti,max-div = <31>;
0347 ti,autoidle-shift = <8>;
0348 reg = <0x0170>;
0349 ti,index-starts-at-one;
0350 ti,invert-autoidle-bit;
0351 };
0352
0353 mpu_dclk_div: clock-mpu-dclk-div {
0354 #clock-cells = <0>;
0355 compatible = "fixed-factor-clock";
0356 clock-output-names = "mpu_dclk_div";
0357 clocks = <&dpll_mpu_m2_ck>;
0358 clock-mult = <1>;
0359 clock-div = <1>;
0360 };
0361
0362 dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
0363 #clock-cells = <0>;
0364 compatible = "fixed-factor-clock";
0365 clock-output-names = "dsp_dpll_hs_clk_div";
0366 clocks = <&dpll_core_h12x2_ck>;
0367 clock-mult = <1>;
0368 clock-div = <1>;
0369 };
0370
0371 dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
0372 #clock-cells = <0>;
0373 compatible = "ti,mux-clock";
0374 clock-output-names = "dpll_dsp_byp_mux";
0375 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
0376 ti,bit-shift = <23>;
0377 reg = <0x0240>;
0378 };
0379
0380 dpll_dsp_ck: clock@234 {
0381 #clock-cells = <0>;
0382 compatible = "ti,omap4-dpll-clock";
0383 clock-output-names = "dpll_dsp_ck";
0384 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
0385 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
0386 assigned-clocks = <&dpll_dsp_ck>;
0387 assigned-clock-rates = <600000000>;
0388 };
0389
0390 dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
0391 #clock-cells = <0>;
0392 compatible = "ti,divider-clock";
0393 clock-output-names = "dpll_dsp_m2_ck";
0394 clocks = <&dpll_dsp_ck>;
0395 ti,max-div = <31>;
0396 ti,autoidle-shift = <8>;
0397 reg = <0x0244>;
0398 ti,index-starts-at-one;
0399 ti,invert-autoidle-bit;
0400 assigned-clocks = <&dpll_dsp_m2_ck>;
0401 assigned-clock-rates = <600000000>;
0402 };
0403
0404 iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
0405 #clock-cells = <0>;
0406 compatible = "fixed-factor-clock";
0407 clock-output-names = "iva_dpll_hs_clk_div";
0408 clocks = <&dpll_core_h12x2_ck>;
0409 clock-mult = <1>;
0410 clock-div = <1>;
0411 };
0412
0413 dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
0414 #clock-cells = <0>;
0415 compatible = "ti,mux-clock";
0416 clock-output-names = "dpll_iva_byp_mux";
0417 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
0418 ti,bit-shift = <23>;
0419 reg = <0x01ac>;
0420 };
0421
0422 dpll_iva_ck: clock@1a0 {
0423 #clock-cells = <0>;
0424 compatible = "ti,omap4-dpll-clock";
0425 clock-output-names = "dpll_iva_ck";
0426 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
0427 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
0428 assigned-clocks = <&dpll_iva_ck>;
0429 assigned-clock-rates = <1165000000>;
0430 };
0431
0432 dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
0433 #clock-cells = <0>;
0434 compatible = "ti,divider-clock";
0435 clock-output-names = "dpll_iva_m2_ck";
0436 clocks = <&dpll_iva_ck>;
0437 ti,max-div = <31>;
0438 ti,autoidle-shift = <8>;
0439 reg = <0x01b0>;
0440 ti,index-starts-at-one;
0441 ti,invert-autoidle-bit;
0442 assigned-clocks = <&dpll_iva_m2_ck>;
0443 assigned-clock-rates = <388333334>;
0444 };
0445
0446 iva_dclk: clock-iva-dclk {
0447 #clock-cells = <0>;
0448 compatible = "fixed-factor-clock";
0449 clock-output-names = "iva_dclk";
0450 clocks = <&dpll_iva_m2_ck>;
0451 clock-mult = <1>;
0452 clock-div = <1>;
0453 };
0454
0455 dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
0456 #clock-cells = <0>;
0457 compatible = "ti,mux-clock";
0458 clock-output-names = "dpll_gpu_byp_mux";
0459 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
0460 ti,bit-shift = <23>;
0461 reg = <0x02e4>;
0462 };
0463
0464 dpll_gpu_ck: clock@2d8 {
0465 #clock-cells = <0>;
0466 compatible = "ti,omap4-dpll-clock";
0467 clock-output-names = "dpll_gpu_ck";
0468 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
0469 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
0470 assigned-clocks = <&dpll_gpu_ck>;
0471 assigned-clock-rates = <1277000000>;
0472 };
0473
0474 dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
0475 #clock-cells = <0>;
0476 compatible = "ti,divider-clock";
0477 clock-output-names = "dpll_gpu_m2_ck";
0478 clocks = <&dpll_gpu_ck>;
0479 ti,max-div = <31>;
0480 ti,autoidle-shift = <8>;
0481 reg = <0x02e8>;
0482 ti,index-starts-at-one;
0483 ti,invert-autoidle-bit;
0484 assigned-clocks = <&dpll_gpu_m2_ck>;
0485 assigned-clock-rates = <425666667>;
0486 };
0487
0488 dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
0489 #clock-cells = <0>;
0490 compatible = "ti,divider-clock";
0491 clock-output-names = "dpll_core_m2_ck";
0492 clocks = <&dpll_core_ck>;
0493 ti,max-div = <31>;
0494 ti,autoidle-shift = <8>;
0495 reg = <0x0130>;
0496 ti,index-starts-at-one;
0497 ti,invert-autoidle-bit;
0498 };
0499
0500 core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
0501 #clock-cells = <0>;
0502 compatible = "fixed-factor-clock";
0503 clock-output-names = "core_dpll_out_dclk_div";
0504 clocks = <&dpll_core_m2_ck>;
0505 clock-mult = <1>;
0506 clock-div = <1>;
0507 };
0508
0509 dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
0510 #clock-cells = <0>;
0511 compatible = "ti,mux-clock";
0512 clock-output-names = "dpll_ddr_byp_mux";
0513 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
0514 ti,bit-shift = <23>;
0515 reg = <0x021c>;
0516 };
0517
0518 dpll_ddr_ck: clock@210 {
0519 #clock-cells = <0>;
0520 compatible = "ti,omap4-dpll-clock";
0521 clock-output-names = "dpll_ddr_ck";
0522 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
0523 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
0524 };
0525
0526 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
0527 #clock-cells = <0>;
0528 compatible = "ti,divider-clock";
0529 clock-output-names = "dpll_ddr_m2_ck";
0530 clocks = <&dpll_ddr_ck>;
0531 ti,max-div = <31>;
0532 ti,autoidle-shift = <8>;
0533 reg = <0x0220>;
0534 ti,index-starts-at-one;
0535 ti,invert-autoidle-bit;
0536 };
0537
0538 dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
0539 #clock-cells = <0>;
0540 compatible = "ti,mux-clock";
0541 clock-output-names = "dpll_gmac_byp_mux";
0542 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
0543 ti,bit-shift = <23>;
0544 reg = <0x02b4>;
0545 };
0546
0547 dpll_gmac_ck: clock@2a8 {
0548 #clock-cells = <0>;
0549 compatible = "ti,omap4-dpll-clock";
0550 clock-output-names = "dpll_gmac_ck";
0551 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
0552 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
0553 };
0554
0555 dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
0556 #clock-cells = <0>;
0557 compatible = "ti,divider-clock";
0558 clock-output-names = "dpll_gmac_m2_ck";
0559 clocks = <&dpll_gmac_ck>;
0560 ti,max-div = <31>;
0561 ti,autoidle-shift = <8>;
0562 reg = <0x02b8>;
0563 ti,index-starts-at-one;
0564 ti,invert-autoidle-bit;
0565 };
0566
0567 video2_dclk_div: clock-video2-dclk-div {
0568 #clock-cells = <0>;
0569 compatible = "fixed-factor-clock";
0570 clock-output-names = "video2_dclk_div";
0571 clocks = <&video2_m2_clkin_ck>;
0572 clock-mult = <1>;
0573 clock-div = <1>;
0574 };
0575
0576 video1_dclk_div: clock-video1-dclk-div {
0577 #clock-cells = <0>;
0578 compatible = "fixed-factor-clock";
0579 clock-output-names = "video1_dclk_div";
0580 clocks = <&video1_m2_clkin_ck>;
0581 clock-mult = <1>;
0582 clock-div = <1>;
0583 };
0584
0585 hdmi_dclk_div: clock-hdmi-dclk-div {
0586 #clock-cells = <0>;
0587 compatible = "fixed-factor-clock";
0588 clock-output-names = "hdmi_dclk_div";
0589 clocks = <&hdmi_clkin_ck>;
0590 clock-mult = <1>;
0591 clock-div = <1>;
0592 };
0593
0594 per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
0595 #clock-cells = <0>;
0596 compatible = "fixed-factor-clock";
0597 clock-output-names = "per_dpll_hs_clk_div";
0598 clocks = <&dpll_abe_m3x2_ck>;
0599 clock-mult = <1>;
0600 clock-div = <2>;
0601 };
0602
0603 usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
0604 #clock-cells = <0>;
0605 compatible = "fixed-factor-clock";
0606 clock-output-names = "usb_dpll_hs_clk_div";
0607 clocks = <&dpll_abe_m3x2_ck>;
0608 clock-mult = <1>;
0609 clock-div = <3>;
0610 };
0611
0612 eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
0613 #clock-cells = <0>;
0614 compatible = "fixed-factor-clock";
0615 clock-output-names = "eve_dpll_hs_clk_div";
0616 clocks = <&dpll_core_h12x2_ck>;
0617 clock-mult = <1>;
0618 clock-div = <1>;
0619 };
0620
0621 dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
0622 #clock-cells = <0>;
0623 compatible = "ti,mux-clock";
0624 clock-output-names = "dpll_eve_byp_mux";
0625 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
0626 ti,bit-shift = <23>;
0627 reg = <0x0290>;
0628 };
0629
0630 dpll_eve_ck: clock@284 {
0631 #clock-cells = <0>;
0632 compatible = "ti,omap4-dpll-clock";
0633 clock-output-names = "dpll_eve_ck";
0634 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
0635 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
0636 };
0637
0638 dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
0639 #clock-cells = <0>;
0640 compatible = "ti,divider-clock";
0641 clock-output-names = "dpll_eve_m2_ck";
0642 clocks = <&dpll_eve_ck>;
0643 ti,max-div = <31>;
0644 ti,autoidle-shift = <8>;
0645 reg = <0x0294>;
0646 ti,index-starts-at-one;
0647 ti,invert-autoidle-bit;
0648 };
0649
0650 eve_dclk_div: clock-eve-dclk-div {
0651 #clock-cells = <0>;
0652 compatible = "fixed-factor-clock";
0653 clock-output-names = "eve_dclk_div";
0654 clocks = <&dpll_eve_m2_ck>;
0655 clock-mult = <1>;
0656 clock-div = <1>;
0657 };
0658
0659 dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
0660 #clock-cells = <0>;
0661 compatible = "ti,divider-clock";
0662 clock-output-names = "dpll_core_h13x2_ck";
0663 clocks = <&dpll_core_x2_ck>;
0664 ti,max-div = <63>;
0665 ti,autoidle-shift = <8>;
0666 reg = <0x0140>;
0667 ti,index-starts-at-one;
0668 ti,invert-autoidle-bit;
0669 };
0670
0671 dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
0672 #clock-cells = <0>;
0673 compatible = "ti,divider-clock";
0674 clock-output-names = "dpll_core_h14x2_ck";
0675 clocks = <&dpll_core_x2_ck>;
0676 ti,max-div = <63>;
0677 ti,autoidle-shift = <8>;
0678 reg = <0x0144>;
0679 ti,index-starts-at-one;
0680 ti,invert-autoidle-bit;
0681 };
0682
0683 dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
0684 #clock-cells = <0>;
0685 compatible = "ti,divider-clock";
0686 clock-output-names = "dpll_core_h22x2_ck";
0687 clocks = <&dpll_core_x2_ck>;
0688 ti,max-div = <63>;
0689 ti,autoidle-shift = <8>;
0690 reg = <0x0154>;
0691 ti,index-starts-at-one;
0692 ti,invert-autoidle-bit;
0693 };
0694
0695 dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
0696 #clock-cells = <0>;
0697 compatible = "ti,divider-clock";
0698 clock-output-names = "dpll_core_h23x2_ck";
0699 clocks = <&dpll_core_x2_ck>;
0700 ti,max-div = <63>;
0701 ti,autoidle-shift = <8>;
0702 reg = <0x0158>;
0703 ti,index-starts-at-one;
0704 ti,invert-autoidle-bit;
0705 };
0706
0707 dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
0708 #clock-cells = <0>;
0709 compatible = "ti,divider-clock";
0710 clock-output-names = "dpll_core_h24x2_ck";
0711 clocks = <&dpll_core_x2_ck>;
0712 ti,max-div = <63>;
0713 ti,autoidle-shift = <8>;
0714 reg = <0x015c>;
0715 ti,index-starts-at-one;
0716 ti,invert-autoidle-bit;
0717 };
0718
0719 dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
0720 #clock-cells = <0>;
0721 compatible = "ti,omap4-dpll-x2-clock";
0722 clock-output-names = "dpll_ddr_x2_ck";
0723 clocks = <&dpll_ddr_ck>;
0724 };
0725
0726 dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
0727 #clock-cells = <0>;
0728 compatible = "ti,divider-clock";
0729 clock-output-names = "dpll_ddr_h11x2_ck";
0730 clocks = <&dpll_ddr_x2_ck>;
0731 ti,max-div = <63>;
0732 ti,autoidle-shift = <8>;
0733 reg = <0x0228>;
0734 ti,index-starts-at-one;
0735 ti,invert-autoidle-bit;
0736 };
0737
0738 dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
0739 #clock-cells = <0>;
0740 compatible = "ti,omap4-dpll-x2-clock";
0741 clock-output-names = "dpll_dsp_x2_ck";
0742 clocks = <&dpll_dsp_ck>;
0743 };
0744
0745 dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
0746 #clock-cells = <0>;
0747 compatible = "ti,divider-clock";
0748 clock-output-names = "dpll_dsp_m3x2_ck";
0749 clocks = <&dpll_dsp_x2_ck>;
0750 ti,max-div = <31>;
0751 ti,autoidle-shift = <8>;
0752 reg = <0x0248>;
0753 ti,index-starts-at-one;
0754 ti,invert-autoidle-bit;
0755 assigned-clocks = <&dpll_dsp_m3x2_ck>;
0756 assigned-clock-rates = <400000000>;
0757 };
0758
0759 dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
0760 #clock-cells = <0>;
0761 compatible = "ti,omap4-dpll-x2-clock";
0762 clock-output-names = "dpll_gmac_x2_ck";
0763 clocks = <&dpll_gmac_ck>;
0764 };
0765
0766 dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
0767 #clock-cells = <0>;
0768 compatible = "ti,divider-clock";
0769 clock-output-names = "dpll_gmac_h11x2_ck";
0770 clocks = <&dpll_gmac_x2_ck>;
0771 ti,max-div = <63>;
0772 ti,autoidle-shift = <8>;
0773 reg = <0x02c0>;
0774 ti,index-starts-at-one;
0775 ti,invert-autoidle-bit;
0776 };
0777
0778 dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
0779 #clock-cells = <0>;
0780 compatible = "ti,divider-clock";
0781 clock-output-names = "dpll_gmac_h12x2_ck";
0782 clocks = <&dpll_gmac_x2_ck>;
0783 ti,max-div = <63>;
0784 ti,autoidle-shift = <8>;
0785 reg = <0x02c4>;
0786 ti,index-starts-at-one;
0787 ti,invert-autoidle-bit;
0788 };
0789
0790 dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
0791 #clock-cells = <0>;
0792 compatible = "ti,divider-clock";
0793 clock-output-names = "dpll_gmac_h13x2_ck";
0794 clocks = <&dpll_gmac_x2_ck>;
0795 ti,max-div = <63>;
0796 ti,autoidle-shift = <8>;
0797 reg = <0x02c8>;
0798 ti,index-starts-at-one;
0799 ti,invert-autoidle-bit;
0800 };
0801
0802 dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
0803 #clock-cells = <0>;
0804 compatible = "ti,divider-clock";
0805 clock-output-names = "dpll_gmac_m3x2_ck";
0806 clocks = <&dpll_gmac_x2_ck>;
0807 ti,max-div = <31>;
0808 ti,autoidle-shift = <8>;
0809 reg = <0x02bc>;
0810 ti,index-starts-at-one;
0811 ti,invert-autoidle-bit;
0812 };
0813
0814 gmii_m_clk_div: clock-gmii-m-clk-div {
0815 #clock-cells = <0>;
0816 compatible = "fixed-factor-clock";
0817 clock-output-names = "gmii_m_clk_div";
0818 clocks = <&dpll_gmac_h11x2_ck>;
0819 clock-mult = <1>;
0820 clock-div = <2>;
0821 };
0822
0823 hdmi_clk2_div: clock-hdmi-clk2-div {
0824 #clock-cells = <0>;
0825 compatible = "fixed-factor-clock";
0826 clock-output-names = "hdmi_clk2_div";
0827 clocks = <&hdmi_clkin_ck>;
0828 clock-mult = <1>;
0829 clock-div = <1>;
0830 };
0831
0832 hdmi_div_clk: clock-hdmi-div {
0833 #clock-cells = <0>;
0834 compatible = "fixed-factor-clock";
0835 clock-output-names = "hdmi_div_clk";
0836 clocks = <&hdmi_clkin_ck>;
0837 clock-mult = <1>;
0838 clock-div = <1>;
0839 };
0840
0841 l3_iclk_div: clock-l3-iclk-div-4@100 {
0842 #clock-cells = <0>;
0843 compatible = "ti,divider-clock";
0844 clock-output-names = "l3_iclk_div";
0845 ti,max-div = <2>;
0846 ti,bit-shift = <4>;
0847 reg = <0x0100>;
0848 clocks = <&dpll_core_h12x2_ck>;
0849 ti,index-power-of-two;
0850 };
0851
0852 l4_root_clk_div: clock-l4-root-clk-div {
0853 #clock-cells = <0>;
0854 compatible = "fixed-factor-clock";
0855 clock-output-names = "l4_root_clk_div";
0856 clocks = <&l3_iclk_div>;
0857 clock-mult = <1>;
0858 clock-div = <2>;
0859 };
0860
0861 video1_clk2_div: clock-video1-clk2-div {
0862 #clock-cells = <0>;
0863 compatible = "fixed-factor-clock";
0864 clock-output-names = "video1_clk2_div";
0865 clocks = <&video1_clkin_ck>;
0866 clock-mult = <1>;
0867 clock-div = <1>;
0868 };
0869
0870 video1_div_clk: clock-video1-div {
0871 #clock-cells = <0>;
0872 compatible = "fixed-factor-clock";
0873 clock-output-names = "video1_div_clk";
0874 clocks = <&video1_clkin_ck>;
0875 clock-mult = <1>;
0876 clock-div = <1>;
0877 };
0878
0879 video2_clk2_div: clock-video2-clk2-div {
0880 #clock-cells = <0>;
0881 compatible = "fixed-factor-clock";
0882 clock-output-names = "video2_clk2_div";
0883 clocks = <&video2_clkin_ck>;
0884 clock-mult = <1>;
0885 clock-div = <1>;
0886 };
0887
0888 video2_div_clk: clock-video2-div {
0889 #clock-cells = <0>;
0890 compatible = "fixed-factor-clock";
0891 clock-output-names = "video2_div_clk";
0892 clocks = <&video2_clkin_ck>;
0893 clock-mult = <1>;
0894 clock-div = <1>;
0895 };
0896
0897 dummy_ck: clock-dummy {
0898 #clock-cells = <0>;
0899 compatible = "fixed-clock";
0900 clock-output-names = "dummy_ck";
0901 clock-frequency = <0>;
0902 };
0903 };
0904 &prm_clocks {
0905 sys_clkin1: clock-sys-clkin1@110 {
0906 #clock-cells = <0>;
0907 compatible = "ti,mux-clock";
0908 clock-output-names = "sys_clkin1";
0909 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
0910 reg = <0x0110>;
0911 ti,index-starts-at-one;
0912 };
0913
0914 abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
0915 #clock-cells = <0>;
0916 compatible = "ti,mux-clock";
0917 clock-output-names = "abe_dpll_sys_clk_mux";
0918 clocks = <&sys_clkin1>, <&sys_clkin2>;
0919 reg = <0x0118>;
0920 };
0921
0922 abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
0923 #clock-cells = <0>;
0924 compatible = "ti,mux-clock";
0925 clock-output-names = "abe_dpll_bypass_clk_mux";
0926 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
0927 reg = <0x0114>;
0928 };
0929
0930 abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
0931 #clock-cells = <0>;
0932 compatible = "ti,mux-clock";
0933 clock-output-names = "abe_dpll_clk_mux";
0934 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
0935 reg = <0x010c>;
0936 };
0937
0938 abe_24m_fclk: clock-abe-24m@11c {
0939 #clock-cells = <0>;
0940 compatible = "ti,divider-clock";
0941 clock-output-names = "abe_24m_fclk";
0942 clocks = <&dpll_abe_m2x2_ck>;
0943 reg = <0x011c>;
0944 ti,dividers = <8>, <16>;
0945 };
0946
0947 aess_fclk: clock-aess@178 {
0948 #clock-cells = <0>;
0949 compatible = "ti,divider-clock";
0950 clock-output-names = "aess_fclk";
0951 clocks = <&abe_clk>;
0952 reg = <0x0178>;
0953 ti,max-div = <2>;
0954 };
0955
0956 abe_giclk_div: clock-abe-giclk-div@174 {
0957 #clock-cells = <0>;
0958 compatible = "ti,divider-clock";
0959 clock-output-names = "abe_giclk_div";
0960 clocks = <&aess_fclk>;
0961 reg = <0x0174>;
0962 ti,max-div = <2>;
0963 };
0964
0965 abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
0966 #clock-cells = <0>;
0967 compatible = "ti,divider-clock";
0968 clock-output-names = "abe_lp_clk_div";
0969 clocks = <&dpll_abe_m2x2_ck>;
0970 reg = <0x01d8>;
0971 ti,dividers = <16>, <32>;
0972 };
0973
0974 abe_sys_clk_div: clock-abe-sys-clk-div@120 {
0975 #clock-cells = <0>;
0976 compatible = "ti,divider-clock";
0977 clock-output-names = "abe_sys_clk_div";
0978 clocks = <&sys_clkin1>;
0979 reg = <0x0120>;
0980 ti,max-div = <2>;
0981 };
0982
0983 adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
0984 #clock-cells = <0>;
0985 compatible = "ti,mux-clock";
0986 clock-output-names = "adc_gfclk_mux";
0987 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
0988 reg = <0x01dc>;
0989 };
0990
0991 sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
0992 #clock-cells = <0>;
0993 compatible = "ti,divider-clock";
0994 clock-output-names = "sys_clk1_dclk_div";
0995 clocks = <&sys_clkin1>;
0996 ti,max-div = <64>;
0997 reg = <0x01c8>;
0998 ti,index-power-of-two;
0999 };
1000
1001 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
1002 #clock-cells = <0>;
1003 compatible = "ti,divider-clock";
1004 clock-output-names = "sys_clk2_dclk_div";
1005 clocks = <&sys_clkin2>;
1006 ti,max-div = <64>;
1007 reg = <0x01cc>;
1008 ti,index-power-of-two;
1009 };
1010
1011 per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
1012 #clock-cells = <0>;
1013 compatible = "ti,divider-clock";
1014 clock-output-names = "per_abe_x1_dclk_div";
1015 clocks = <&dpll_abe_m2_ck>;
1016 ti,max-div = <64>;
1017 reg = <0x01bc>;
1018 ti,index-power-of-two;
1019 };
1020
1021 dsp_gclk_div: clock-dsp-gclk-div@18c {
1022 #clock-cells = <0>;
1023 compatible = "ti,divider-clock";
1024 clock-output-names = "dsp_gclk_div";
1025 clocks = <&dpll_dsp_m2_ck>;
1026 ti,max-div = <64>;
1027 reg = <0x018c>;
1028 ti,index-power-of-two;
1029 };
1030
1031 gpu_dclk: clock-gpu-dclk@1a0 {
1032 #clock-cells = <0>;
1033 compatible = "ti,divider-clock";
1034 clock-output-names = "gpu_dclk";
1035 clocks = <&dpll_gpu_m2_ck>;
1036 ti,max-div = <64>;
1037 reg = <0x01a0>;
1038 ti,index-power-of-two;
1039 };
1040
1041 emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
1042 #clock-cells = <0>;
1043 compatible = "ti,divider-clock";
1044 clock-output-names = "emif_phy_dclk_div";
1045 clocks = <&dpll_ddr_m2_ck>;
1046 ti,max-div = <64>;
1047 reg = <0x0190>;
1048 ti,index-power-of-two;
1049 };
1050
1051 gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
1052 #clock-cells = <0>;
1053 compatible = "ti,divider-clock";
1054 clock-output-names = "gmac_250m_dclk_div";
1055 clocks = <&dpll_gmac_m2_ck>;
1056 ti,max-div = <64>;
1057 reg = <0x019c>;
1058 ti,index-power-of-two;
1059 };
1060
1061 gmac_main_clk: clock-gmac-main {
1062 #clock-cells = <0>;
1063 compatible = "fixed-factor-clock";
1064 clock-output-names = "gmac_main_clk";
1065 clocks = <&gmac_250m_dclk_div>;
1066 clock-mult = <1>;
1067 clock-div = <2>;
1068 };
1069
1070 l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
1071 #clock-cells = <0>;
1072 compatible = "ti,divider-clock";
1073 clock-output-names = "l3init_480m_dclk_div";
1074 clocks = <&dpll_usb_m2_ck>;
1075 ti,max-div = <64>;
1076 reg = <0x01ac>;
1077 ti,index-power-of-two;
1078 };
1079
1080 usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
1081 #clock-cells = <0>;
1082 compatible = "ti,divider-clock";
1083 clock-output-names = "usb_otg_dclk_div";
1084 clocks = <&usb_otg_clkin_ck>;
1085 ti,max-div = <64>;
1086 reg = <0x0184>;
1087 ti,index-power-of-two;
1088 };
1089
1090 sata_dclk_div: clock-sata-dclk-div@1c0 {
1091 #clock-cells = <0>;
1092 compatible = "ti,divider-clock";
1093 clock-output-names = "sata_dclk_div";
1094 clocks = <&sys_clkin1>;
1095 ti,max-div = <64>;
1096 reg = <0x01c0>;
1097 ti,index-power-of-two;
1098 };
1099
1100 pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
1101 #clock-cells = <0>;
1102 compatible = "ti,divider-clock";
1103 clock-output-names = "pcie2_dclk_div";
1104 clocks = <&dpll_pcie_ref_m2_ck>;
1105 ti,max-div = <64>;
1106 reg = <0x01b8>;
1107 ti,index-power-of-two;
1108 };
1109
1110 pcie_dclk_div: clock-pcie-dclk-div@1b4 {
1111 #clock-cells = <0>;
1112 compatible = "ti,divider-clock";
1113 clock-output-names = "pcie_dclk_div";
1114 clocks = <&apll_pcie_m2_ck>;
1115 ti,max-div = <64>;
1116 reg = <0x01b4>;
1117 ti,index-power-of-two;
1118 };
1119
1120 emu_dclk_div: clock-emu-dclk-div@194 {
1121 #clock-cells = <0>;
1122 compatible = "ti,divider-clock";
1123 clock-output-names = "emu_dclk_div";
1124 clocks = <&sys_clkin1>;
1125 ti,max-div = <64>;
1126 reg = <0x0194>;
1127 ti,index-power-of-two;
1128 };
1129
1130 secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
1131 #clock-cells = <0>;
1132 compatible = "ti,divider-clock";
1133 clock-output-names = "secure_32k_dclk_div";
1134 clocks = <&secure_32k_clk_src_ck>;
1135 ti,max-div = <64>;
1136 reg = <0x01c4>;
1137 ti,index-power-of-two;
1138 };
1139
1140 clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
1141 #clock-cells = <0>;
1142 compatible = "ti,mux-clock";
1143 clock-output-names = "clkoutmux0_clk_mux";
1144 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1145 reg = <0x0158>;
1146 };
1147
1148 clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
1149 #clock-cells = <0>;
1150 compatible = "ti,mux-clock";
1151 clock-output-names = "clkoutmux1_clk_mux";
1152 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1153 reg = <0x015c>;
1154 };
1155
1156 clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
1157 #clock-cells = <0>;
1158 compatible = "ti,mux-clock";
1159 clock-output-names = "clkoutmux2_clk_mux";
1160 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1161 reg = <0x0160>;
1162 };
1163
1164 custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
1165 #clock-cells = <0>;
1166 compatible = "fixed-factor-clock";
1167 clock-output-names = "custefuse_sys_gfclk_div";
1168 clocks = <&sys_clkin1>;
1169 clock-mult = <1>;
1170 clock-div = <2>;
1171 };
1172
1173 eve_clk: clock-eve@180 {
1174 #clock-cells = <0>;
1175 compatible = "ti,mux-clock";
1176 clock-output-names = "eve_clk";
1177 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1178 reg = <0x0180>;
1179 };
1180
1181 hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
1182 #clock-cells = <0>;
1183 compatible = "ti,mux-clock";
1184 clock-output-names = "hdmi_dpll_clk_mux";
1185 clocks = <&sys_clkin1>, <&sys_clkin2>;
1186 reg = <0x0164>;
1187 };
1188
1189 mlb_clk: clock-mlb@134 {
1190 #clock-cells = <0>;
1191 compatible = "ti,divider-clock";
1192 clock-output-names = "mlb_clk";
1193 clocks = <&mlb_clkin_ck>;
1194 ti,max-div = <64>;
1195 reg = <0x0134>;
1196 ti,index-power-of-two;
1197 };
1198
1199 mlbp_clk: clock-mlbp@130 {
1200 #clock-cells = <0>;
1201 compatible = "ti,divider-clock";
1202 clock-output-names = "mlbp_clk";
1203 clocks = <&mlbp_clkin_ck>;
1204 ti,max-div = <64>;
1205 reg = <0x0130>;
1206 ti,index-power-of-two;
1207 };
1208
1209 per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
1210 #clock-cells = <0>;
1211 compatible = "ti,divider-clock";
1212 clock-output-names = "per_abe_x1_gfclk2_div";
1213 clocks = <&dpll_abe_m2_ck>;
1214 ti,max-div = <64>;
1215 reg = <0x0138>;
1216 ti,index-power-of-two;
1217 };
1218
1219 timer_sys_clk_div: clock-timer-sys-clk-div@144 {
1220 #clock-cells = <0>;
1221 compatible = "ti,divider-clock";
1222 clock-output-names = "timer_sys_clk_div";
1223 clocks = <&sys_clkin1>;
1224 reg = <0x0144>;
1225 ti,max-div = <2>;
1226 };
1227
1228 video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
1229 #clock-cells = <0>;
1230 compatible = "ti,mux-clock";
1231 clock-output-names = "video1_dpll_clk_mux";
1232 clocks = <&sys_clkin1>, <&sys_clkin2>;
1233 reg = <0x0168>;
1234 };
1235
1236 video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
1237 #clock-cells = <0>;
1238 compatible = "ti,mux-clock";
1239 clock-output-names = "video2_dpll_clk_mux";
1240 clocks = <&sys_clkin1>, <&sys_clkin2>;
1241 reg = <0x016c>;
1242 };
1243
1244 wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
1245 #clock-cells = <0>;
1246 compatible = "ti,mux-clock";
1247 clock-output-names = "wkupaon_iclk_mux";
1248 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1249 reg = <0x0108>;
1250 };
1251 };
1252
1253 &cm_core_clocks {
1254 dpll_pcie_ref_ck: clock@200 {
1255 #clock-cells = <0>;
1256 compatible = "ti,omap4-dpll-clock";
1257 clock-output-names = "dpll_pcie_ref_ck";
1258 clocks = <&sys_clkin1>, <&sys_clkin1>;
1259 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1260 };
1261
1262 dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
1263 #clock-cells = <0>;
1264 compatible = "ti,divider-clock";
1265 clock-output-names = "dpll_pcie_ref_m2ldo_ck";
1266 clocks = <&dpll_pcie_ref_ck>;
1267 ti,max-div = <31>;
1268 ti,autoidle-shift = <8>;
1269 reg = <0x0210>;
1270 ti,index-starts-at-one;
1271 ti,invert-autoidle-bit;
1272 };
1273
1274 apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
1275 compatible = "ti,mux-clock";
1276 clock-output-names = "apll_pcie_in_clk_mux";
1277 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1278 #clock-cells = <0>;
1279 reg = <0x021c 0x4>;
1280 ti,bit-shift = <7>;
1281 };
1282
1283 apll_pcie_ck: clock@21c {
1284 #clock-cells = <0>;
1285 compatible = "ti,dra7-apll-clock";
1286 clock-output-names = "apll_pcie_ck";
1287 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1288 reg = <0x021c>, <0x0220>;
1289 };
1290
1291 optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
1292 compatible = "ti,divider-clock";
1293 clock-output-names = "optfclk_pciephy_div";
1294 clocks = <&apll_pcie_ck>;
1295 #clock-cells = <0>;
1296 reg = <0x021c>;
1297 ti,dividers = <2>, <1>;
1298 ti,bit-shift = <8>;
1299 ti,max-div = <2>;
1300 };
1301
1302 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
1303 #clock-cells = <0>;
1304 compatible = "fixed-factor-clock";
1305 clock-output-names = "apll_pcie_clkvcoldo";
1306 clocks = <&apll_pcie_ck>;
1307 clock-mult = <1>;
1308 clock-div = <1>;
1309 };
1310
1311 apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
1312 #clock-cells = <0>;
1313 compatible = "fixed-factor-clock";
1314 clock-output-names = "apll_pcie_clkvcoldo_div";
1315 clocks = <&apll_pcie_ck>;
1316 clock-mult = <1>;
1317 clock-div = <1>;
1318 };
1319
1320 apll_pcie_m2_ck: clock-apll-pcie-m2 {
1321 #clock-cells = <0>;
1322 compatible = "fixed-factor-clock";
1323 clock-output-names = "apll_pcie_m2_ck";
1324 clocks = <&apll_pcie_ck>;
1325 clock-mult = <1>;
1326 clock-div = <1>;
1327 };
1328
1329 dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
1330 #clock-cells = <0>;
1331 compatible = "ti,mux-clock";
1332 clock-output-names = "dpll_per_byp_mux";
1333 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1334 ti,bit-shift = <23>;
1335 reg = <0x014c>;
1336 };
1337
1338 dpll_per_ck: clock@140 {
1339 #clock-cells = <0>;
1340 compatible = "ti,omap4-dpll-clock";
1341 clock-output-names = "dpll_per_ck";
1342 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1343 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1344 };
1345
1346 dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
1347 #clock-cells = <0>;
1348 compatible = "ti,divider-clock";
1349 clock-output-names = "dpll_per_m2_ck";
1350 clocks = <&dpll_per_ck>;
1351 ti,max-div = <31>;
1352 ti,autoidle-shift = <8>;
1353 reg = <0x0150>;
1354 ti,index-starts-at-one;
1355 ti,invert-autoidle-bit;
1356 };
1357
1358 func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
1359 #clock-cells = <0>;
1360 compatible = "fixed-factor-clock";
1361 clock-output-names = "func_96m_aon_dclk_div";
1362 clocks = <&dpll_per_m2_ck>;
1363 clock-mult = <1>;
1364 clock-div = <1>;
1365 };
1366
1367 dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
1368 #clock-cells = <0>;
1369 compatible = "ti,mux-clock";
1370 clock-output-names = "dpll_usb_byp_mux";
1371 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1372 ti,bit-shift = <23>;
1373 reg = <0x018c>;
1374 };
1375
1376 dpll_usb_ck: clock@180 {
1377 #clock-cells = <0>;
1378 compatible = "ti,omap4-dpll-j-type-clock";
1379 clock-output-names = "dpll_usb_ck";
1380 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1381 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1382 };
1383
1384 dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
1385 #clock-cells = <0>;
1386 compatible = "ti,divider-clock";
1387 clock-output-names = "dpll_usb_m2_ck";
1388 clocks = <&dpll_usb_ck>;
1389 ti,max-div = <127>;
1390 ti,autoidle-shift = <8>;
1391 reg = <0x0190>;
1392 ti,index-starts-at-one;
1393 ti,invert-autoidle-bit;
1394 };
1395
1396 dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
1397 #clock-cells = <0>;
1398 compatible = "ti,divider-clock";
1399 clock-output-names = "dpll_pcie_ref_m2_ck";
1400 clocks = <&dpll_pcie_ref_ck>;
1401 ti,max-div = <127>;
1402 ti,autoidle-shift = <8>;
1403 reg = <0x0210>;
1404 ti,index-starts-at-one;
1405 ti,invert-autoidle-bit;
1406 };
1407
1408 dpll_per_x2_ck: clock-dpll-per-x2 {
1409 #clock-cells = <0>;
1410 compatible = "ti,omap4-dpll-x2-clock";
1411 clock-output-names = "dpll_per_x2_ck";
1412 clocks = <&dpll_per_ck>;
1413 };
1414
1415 dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
1416 #clock-cells = <0>;
1417 compatible = "ti,divider-clock";
1418 clock-output-names = "dpll_per_h11x2_ck";
1419 clocks = <&dpll_per_x2_ck>;
1420 ti,max-div = <63>;
1421 ti,autoidle-shift = <8>;
1422 reg = <0x0158>;
1423 ti,index-starts-at-one;
1424 ti,invert-autoidle-bit;
1425 };
1426
1427 dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
1428 #clock-cells = <0>;
1429 compatible = "ti,divider-clock";
1430 clock-output-names = "dpll_per_h12x2_ck";
1431 clocks = <&dpll_per_x2_ck>;
1432 ti,max-div = <63>;
1433 ti,autoidle-shift = <8>;
1434 reg = <0x015c>;
1435 ti,index-starts-at-one;
1436 ti,invert-autoidle-bit;
1437 };
1438
1439 dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
1440 #clock-cells = <0>;
1441 compatible = "ti,divider-clock";
1442 clock-output-names = "dpll_per_h13x2_ck";
1443 clocks = <&dpll_per_x2_ck>;
1444 ti,max-div = <63>;
1445 ti,autoidle-shift = <8>;
1446 reg = <0x0160>;
1447 ti,index-starts-at-one;
1448 ti,invert-autoidle-bit;
1449 };
1450
1451 dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
1452 #clock-cells = <0>;
1453 compatible = "ti,divider-clock";
1454 clock-output-names = "dpll_per_h14x2_ck";
1455 clocks = <&dpll_per_x2_ck>;
1456 ti,max-div = <63>;
1457 ti,autoidle-shift = <8>;
1458 reg = <0x0164>;
1459 ti,index-starts-at-one;
1460 ti,invert-autoidle-bit;
1461 };
1462
1463 dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
1464 #clock-cells = <0>;
1465 compatible = "ti,divider-clock";
1466 clock-output-names = "dpll_per_m2x2_ck";
1467 clocks = <&dpll_per_x2_ck>;
1468 ti,max-div = <31>;
1469 ti,autoidle-shift = <8>;
1470 reg = <0x0150>;
1471 ti,index-starts-at-one;
1472 ti,invert-autoidle-bit;
1473 };
1474
1475 dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
1476 #clock-cells = <0>;
1477 compatible = "fixed-factor-clock";
1478 clock-output-names = "dpll_usb_clkdcoldo";
1479 clocks = <&dpll_usb_ck>;
1480 clock-mult = <1>;
1481 clock-div = <1>;
1482 };
1483
1484 func_128m_clk: clock-func-128m {
1485 #clock-cells = <0>;
1486 compatible = "fixed-factor-clock";
1487 clock-output-names = "func_128m_clk";
1488 clocks = <&dpll_per_h11x2_ck>;
1489 clock-mult = <1>;
1490 clock-div = <2>;
1491 };
1492
1493 func_12m_fclk: clock-func-12m-fclk {
1494 #clock-cells = <0>;
1495 compatible = "fixed-factor-clock";
1496 clock-output-names = "func_12m_fclk";
1497 clocks = <&dpll_per_m2x2_ck>;
1498 clock-mult = <1>;
1499 clock-div = <16>;
1500 };
1501
1502 func_24m_clk: clock-func-24m {
1503 #clock-cells = <0>;
1504 compatible = "fixed-factor-clock";
1505 clock-output-names = "func_24m_clk";
1506 clocks = <&dpll_per_m2_ck>;
1507 clock-mult = <1>;
1508 clock-div = <4>;
1509 };
1510
1511 func_48m_fclk: clock-func-48m-fclk {
1512 #clock-cells = <0>;
1513 compatible = "fixed-factor-clock";
1514 clock-output-names = "func_48m_fclk";
1515 clocks = <&dpll_per_m2x2_ck>;
1516 clock-mult = <1>;
1517 clock-div = <4>;
1518 };
1519
1520 func_96m_fclk: clock-func-96m-fclk {
1521 #clock-cells = <0>;
1522 compatible = "fixed-factor-clock";
1523 clock-output-names = "func_96m_fclk";
1524 clocks = <&dpll_per_m2x2_ck>;
1525 clock-mult = <1>;
1526 clock-div = <2>;
1527 };
1528
1529 l3init_60m_fclk: clock-l3init-60m@104 {
1530 #clock-cells = <0>;
1531 compatible = "ti,divider-clock";
1532 clock-output-names = "l3init_60m_fclk";
1533 clocks = <&dpll_usb_m2_ck>;
1534 reg = <0x0104>;
1535 ti,dividers = <1>, <8>;
1536 };
1537
1538 clkout2_clk: clock-clkout2-8@6b0 {
1539 #clock-cells = <0>;
1540 compatible = "ti,gate-clock";
1541 clock-output-names = "clkout2_clk";
1542 clocks = <&clkoutmux2_clk_mux>;
1543 ti,bit-shift = <8>;
1544 reg = <0x06b0>;
1545 };
1546
1547 l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
1548 #clock-cells = <0>;
1549 compatible = "ti,gate-clock";
1550 clock-output-names = "l3init_960m_gfclk";
1551 clocks = <&dpll_usb_clkdcoldo>;
1552 ti,bit-shift = <8>;
1553 reg = <0x06c0>;
1554 };
1555
1556 usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
1557 #clock-cells = <0>;
1558 compatible = "ti,gate-clock";
1559 clock-output-names = "usb_phy1_always_on_clk32k";
1560 clocks = <&sys_32k_ck>;
1561 ti,bit-shift = <8>;
1562 reg = <0x0640>;
1563 };
1564
1565 usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
1566 #clock-cells = <0>;
1567 compatible = "ti,gate-clock";
1568 clock-output-names = "usb_phy2_always_on_clk32k";
1569 clocks = <&sys_32k_ck>;
1570 ti,bit-shift = <8>;
1571 reg = <0x0688>;
1572 };
1573
1574 usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
1575 #clock-cells = <0>;
1576 compatible = "ti,gate-clock";
1577 clock-output-names = "usb_phy3_always_on_clk32k";
1578 clocks = <&sys_32k_ck>;
1579 ti,bit-shift = <8>;
1580 reg = <0x0698>;
1581 };
1582
1583 gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
1584 #clock-cells = <0>;
1585 compatible = "ti,mux-clock";
1586 clock-output-names = "gpu_core_gclk_mux";
1587 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1588 ti,bit-shift = <24>;
1589 reg = <0x1220>;
1590 assigned-clocks = <&gpu_core_gclk_mux>;
1591 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1592 };
1593
1594 gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
1595 #clock-cells = <0>;
1596 compatible = "ti,mux-clock";
1597 clock-output-names = "gpu_hyd_gclk_mux";
1598 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1599 ti,bit-shift = <26>;
1600 reg = <0x1220>;
1601 assigned-clocks = <&gpu_hyd_gclk_mux>;
1602 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1603 };
1604
1605 l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
1606 #clock-cells = <0>;
1607 compatible = "ti,divider-clock";
1608 clock-output-names = "l3instr_ts_gclk_div";
1609 clocks = <&wkupaon_iclk_mux>;
1610 ti,bit-shift = <24>;
1611 reg = <0x0e50>;
1612 ti,dividers = <8>, <16>, <32>;
1613 };
1614
1615 vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
1616 #clock-cells = <0>;
1617 compatible = "ti,mux-clock";
1618 clock-output-names = "vip1_gclk_mux";
1619 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1620 ti,bit-shift = <24>;
1621 reg = <0x1020>;
1622 };
1623
1624 vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
1625 #clock-cells = <0>;
1626 compatible = "ti,mux-clock";
1627 clock-output-names = "vip2_gclk_mux";
1628 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1629 ti,bit-shift = <24>;
1630 reg = <0x1028>;
1631 };
1632
1633 vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
1634 #clock-cells = <0>;
1635 compatible = "ti,mux-clock";
1636 clock-output-names = "vip3_gclk_mux";
1637 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1638 ti,bit-shift = <24>;
1639 reg = <0x1030>;
1640 };
1641 };
1642
1643 &cm_core_clockdomains {
1644 coreaon_clkdm: clock-coreaon-clkdm {
1645 compatible = "ti,clockdomain";
1646 clock-output-names = "coreaon_clkdm";
1647 clocks = <&dpll_usb_ck>;
1648 };
1649 };
1650
1651 &scm_conf_clocks {
1652 dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
1653 #clock-cells = <0>;
1654 compatible = "ti,gate-clock";
1655 clock-output-names = "dss_deshdcp_clk";
1656 clocks = <&l3_iclk_div>;
1657 ti,bit-shift = <0>;
1658 reg = <0x558>;
1659 };
1660
1661 ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
1662 #clock-cells = <0>;
1663 compatible = "ti,gate-clock";
1664 clock-output-names = "ehrpwm0_tbclk";
1665 clocks = <&l4_root_clk_div>;
1666 ti,bit-shift = <20>;
1667 reg = <0x0558>;
1668 };
1669
1670 ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
1671 #clock-cells = <0>;
1672 compatible = "ti,gate-clock";
1673 clock-output-names = "ehrpwm1_tbclk";
1674 clocks = <&l4_root_clk_div>;
1675 ti,bit-shift = <21>;
1676 reg = <0x0558>;
1677 };
1678
1679 ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
1680 #clock-cells = <0>;
1681 compatible = "ti,gate-clock";
1682 clock-output-names = "ehrpwm2_tbclk";
1683 clocks = <&l4_root_clk_div>;
1684 ti,bit-shift = <22>;
1685 reg = <0x0558>;
1686 };
1687
1688 sys_32k_ck: clock-sys-32k {
1689 #clock-cells = <0>;
1690 compatible = "ti,mux-clock";
1691 clock-output-names = "sys_32k_ck";
1692 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1693 ti,bit-shift = <8>;
1694 reg = <0x6c4>;
1695 };
1696 };
1697
1698 &cm_core_aon {
1699 mpu_cm: clock@300 {
1700 compatible = "ti,omap4-cm";
1701 clock-output-names = "mpu_cm";
1702 reg = <0x300 0x100>;
1703 #address-cells = <1>;
1704 #size-cells = <1>;
1705 ranges = <0 0x300 0x100>;
1706
1707 mpu_clkctrl: clock@20 {
1708 compatible = "ti,clkctrl";
1709 clock-output-names = "mpu_clkctrl";
1710 reg = <0x20 0x4>;
1711 #clock-cells = <2>;
1712 };
1713
1714 };
1715
1716 dsp1_cm: clock@400 {
1717 compatible = "ti,omap4-cm";
1718 clock-output-names = "dsp1_cm";
1719 reg = <0x400 0x100>;
1720 #address-cells = <1>;
1721 #size-cells = <1>;
1722 ranges = <0 0x400 0x100>;
1723
1724 dsp1_clkctrl: clock@20 {
1725 compatible = "ti,clkctrl";
1726 clock-output-names = "dsp1_clkctrl";
1727 reg = <0x20 0x4>;
1728 #clock-cells = <2>;
1729 };
1730
1731 };
1732
1733 ipu_cm: clock@500 {
1734 compatible = "ti,omap4-cm";
1735 clock-output-names = "ipu_cm";
1736 reg = <0x500 0x100>;
1737 #address-cells = <1>;
1738 #size-cells = <1>;
1739 ranges = <0 0x500 0x100>;
1740
1741 ipu1_clkctrl: clock@20 {
1742 compatible = "ti,clkctrl";
1743 clock-output-names = "ipu1_clkctrl";
1744 reg = <0x20 0x4>;
1745 #clock-cells = <2>;
1746 assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
1747 assigned-clock-parents = <&dpll_core_h22x2_ck>;
1748 };
1749
1750 ipu_clkctrl: clock@50 {
1751 compatible = "ti,clkctrl";
1752 clock-output-names = "ipu_clkctrl";
1753 reg = <0x50 0x34>;
1754 #clock-cells = <2>;
1755 };
1756
1757 };
1758
1759 dsp2_cm: clock@600 {
1760 compatible = "ti,omap4-cm";
1761 clock-output-names = "dsp2_cm";
1762 reg = <0x600 0x100>;
1763 #address-cells = <1>;
1764 #size-cells = <1>;
1765 ranges = <0 0x600 0x100>;
1766
1767 dsp2_clkctrl: clock@20 {
1768 compatible = "ti,clkctrl";
1769 clock-output-names = "dsp2_clkctrl";
1770 reg = <0x20 0x4>;
1771 #clock-cells = <2>;
1772 };
1773
1774 };
1775
1776 rtc_cm: clock@700 {
1777 compatible = "ti,omap4-cm";
1778 clock-output-names = "rtc_cm";
1779 reg = <0x700 0x60>;
1780 #address-cells = <1>;
1781 #size-cells = <1>;
1782 ranges = <0 0x700 0x60>;
1783
1784 rtc_clkctrl: clock@20 {
1785 compatible = "ti,clkctrl";
1786 clock-output-names = "rtc_clkctrl";
1787 reg = <0x20 0x28>;
1788 #clock-cells = <2>;
1789 };
1790 };
1791
1792 vpe_cm: clock@760 {
1793 compatible = "ti,omap4-cm";
1794 clock-output-names = "vpe_cm";
1795 reg = <0x760 0xc>;
1796 #address-cells = <1>;
1797 #size-cells = <1>;
1798 ranges = <0 0x760 0xc>;
1799
1800 vpe_clkctrl: clock@0 {
1801 compatible = "ti,clkctrl";
1802 clock-output-names = "vpe_clkctrl";
1803 reg = <0x0 0xc>;
1804 #clock-cells = <2>;
1805 };
1806 };
1807
1808 };
1809
1810 &cm_core {
1811 coreaon_cm: clock@600 {
1812 compatible = "ti,omap4-cm";
1813 clock-output-names = "coreaon_cm";
1814 reg = <0x600 0x100>;
1815 #address-cells = <1>;
1816 #size-cells = <1>;
1817 ranges = <0 0x600 0x100>;
1818
1819 coreaon_clkctrl: clock@20 {
1820 compatible = "ti,clkctrl";
1821 clock-output-names = "coreaon_clkctrl";
1822 reg = <0x20 0x1c>;
1823 #clock-cells = <2>;
1824 };
1825 };
1826
1827 l3main1_cm: clock@700 {
1828 compatible = "ti,omap4-cm";
1829 clock-output-names = "l3main1_cm";
1830 reg = <0x700 0x100>;
1831 #address-cells = <1>;
1832 #size-cells = <1>;
1833 ranges = <0 0x700 0x100>;
1834
1835 l3main1_clkctrl: clock@20 {
1836 compatible = "ti,clkctrl";
1837 clock-output-names = "l3main1_clkctrl";
1838 reg = <0x20 0x74>;
1839 #clock-cells = <2>;
1840 };
1841
1842 };
1843
1844 ipu2_cm: clock@900 {
1845 compatible = "ti,omap4-cm";
1846 clock-output-names = "ipu2_cm";
1847 reg = <0x900 0x100>;
1848 #address-cells = <1>;
1849 #size-cells = <1>;
1850 ranges = <0 0x900 0x100>;
1851
1852 ipu2_clkctrl: clock@20 {
1853 compatible = "ti,clkctrl";
1854 clock-output-names = "ipu2_clkctrl";
1855 reg = <0x20 0x4>;
1856 #clock-cells = <2>;
1857 };
1858
1859 };
1860
1861 dma_cm: clock@a00 {
1862 compatible = "ti,omap4-cm";
1863 clock-output-names = "dma_cm";
1864 reg = <0xa00 0x100>;
1865 #address-cells = <1>;
1866 #size-cells = <1>;
1867 ranges = <0 0xa00 0x100>;
1868
1869 dma_clkctrl: clock@20 {
1870 compatible = "ti,clkctrl";
1871 clock-output-names = "dma_clkctrl";
1872 reg = <0x20 0x4>;
1873 #clock-cells = <2>;
1874 };
1875 };
1876
1877 emif_cm: clock@b00 {
1878 compatible = "ti,omap4-cm";
1879 clock-output-names = "emif_cm";
1880 reg = <0xb00 0x100>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0 0xb00 0x100>;
1884
1885 emif_clkctrl: clock@20 {
1886 compatible = "ti,clkctrl";
1887 clock-output-names = "emif_clkctrl";
1888 reg = <0x20 0x4>;
1889 #clock-cells = <2>;
1890 };
1891 };
1892
1893 atl_cm: clock@c00 {
1894 compatible = "ti,omap4-cm";
1895 clock-output-names = "atl_cm";
1896 reg = <0xc00 0x100>;
1897 #address-cells = <1>;
1898 #size-cells = <1>;
1899 ranges = <0 0xc00 0x100>;
1900
1901 atl_clkctrl: clock@0 {
1902 compatible = "ti,clkctrl";
1903 clock-output-names = "atl_clkctrl";
1904 reg = <0x0 0x4>;
1905 #clock-cells = <2>;
1906 };
1907 };
1908
1909 l4cfg_cm: clock@d00 {
1910 compatible = "ti,omap4-cm";
1911 clock-output-names = "l4cfg_cm";
1912 reg = <0xd00 0x100>;
1913 #address-cells = <1>;
1914 #size-cells = <1>;
1915 ranges = <0 0xd00 0x100>;
1916
1917 l4cfg_clkctrl: clock@20 {
1918 compatible = "ti,clkctrl";
1919 clock-output-names = "l4cfg_clkctrl";
1920 reg = <0x20 0x84>;
1921 #clock-cells = <2>;
1922 };
1923 };
1924
1925 l3instr_cm: clock@e00 {
1926 compatible = "ti,omap4-cm";
1927 clock-output-names = "l3instr_cm";
1928 reg = <0xe00 0x100>;
1929 #address-cells = <1>;
1930 #size-cells = <1>;
1931 ranges = <0 0xe00 0x100>;
1932
1933 l3instr_clkctrl: clock@20 {
1934 compatible = "ti,clkctrl";
1935 clock-output-names = "l3instr_clkctrl";
1936 reg = <0x20 0xc>;
1937 #clock-cells = <2>;
1938 };
1939 };
1940
1941 iva_cm: clock@f00 {
1942 compatible = "ti,omap4-cm";
1943 clock-output-names = "iva_cm";
1944 reg = <0xf00 0x100>;
1945 #address-cells = <1>;
1946 #size-cells = <1>;
1947 ranges = <0 0xf00 0x100>;
1948
1949 iva_clkctrl: clock@20 {
1950 compatible = "ti,clkctrl";
1951 clock-output-names = "iva_clkctrl";
1952 reg = <0x20 0xc>;
1953 #clock-cells = <2>;
1954 };
1955 };
1956
1957 cam_cm: clock@1000 {
1958 compatible = "ti,omap4-cm";
1959 clock-output-names = "cam_cm";
1960 reg = <0x1000 0x100>;
1961 #address-cells = <1>;
1962 #size-cells = <1>;
1963 ranges = <0 0x1000 0x100>;
1964
1965 cam_clkctrl: clock@20 {
1966 compatible = "ti,clkctrl";
1967 clock-output-names = "cam_clkctrl";
1968 reg = <0x20 0x2c>;
1969 #clock-cells = <2>;
1970 };
1971 };
1972
1973 dss_cm: clock@1100 {
1974 compatible = "ti,omap4-cm";
1975 clock-output-names = "dss_cm";
1976 reg = <0x1100 0x100>;
1977 #address-cells = <1>;
1978 #size-cells = <1>;
1979 ranges = <0 0x1100 0x100>;
1980
1981 dss_clkctrl: clock@20 {
1982 compatible = "ti,clkctrl";
1983 clock-output-names = "dss_clkctrl";
1984 reg = <0x20 0x14>;
1985 #clock-cells = <2>;
1986 };
1987 };
1988
1989 gpu_cm: clock@1200 {
1990 compatible = "ti,omap4-cm";
1991 clock-output-names = "gpu_cm";
1992 reg = <0x1200 0x100>;
1993 #address-cells = <1>;
1994 #size-cells = <1>;
1995 ranges = <0 0x1200 0x100>;
1996
1997 gpu_clkctrl: clock@20 {
1998 compatible = "ti,clkctrl";
1999 clock-output-names = "gpu_clkctrl";
2000 reg = <0x20 0x4>;
2001 #clock-cells = <2>;
2002 };
2003 };
2004
2005 l3init_cm: clock@1300 {
2006 compatible = "ti,omap4-cm";
2007 clock-output-names = "l3init_cm";
2008 reg = <0x1300 0x100>;
2009 #address-cells = <1>;
2010 #size-cells = <1>;
2011 ranges = <0 0x1300 0x100>;
2012
2013 l3init_clkctrl: clock@20 {
2014 compatible = "ti,clkctrl";
2015 clock-output-names = "l3init_clkctrl";
2016 reg = <0x20 0x6c>, <0xe0 0x14>;
2017 #clock-cells = <2>;
2018 };
2019
2020 pcie_clkctrl: clock@b0 {
2021 compatible = "ti,clkctrl";
2022 clock-output-names = "pcie_clkctrl";
2023 reg = <0xb0 0xc>;
2024 #clock-cells = <2>;
2025 };
2026
2027 gmac_clkctrl: clock@d0 {
2028 compatible = "ti,clkctrl";
2029 clock-output-names = "gmac_clkctrl";
2030 reg = <0xd0 0x4>;
2031 #clock-cells = <2>;
2032 };
2033
2034 };
2035
2036 l4per_cm: clock@1700 {
2037 compatible = "ti,omap4-cm";
2038 clock-output-names = "l4per_cm";
2039 reg = <0x1700 0x300>;
2040 #address-cells = <1>;
2041 #size-cells = <1>;
2042 ranges = <0 0x1700 0x300>;
2043
2044 l4per_clkctrl: clock@28 {
2045 compatible = "ti,clkctrl";
2046 clock-output-names = "l4per_clkctrl";
2047 reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
2048 #clock-cells = <2>;
2049
2050 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2051 assigned-clock-parents = <&abe_24m_fclk>;
2052 };
2053
2054 l4sec_clkctrl: clock@1a0 {
2055 compatible = "ti,clkctrl";
2056 clock-output-names = "l4sec_clkctrl";
2057 reg = <0x1a0 0x2c>;
2058 #clock-cells = <2>;
2059 };
2060
2061 l4per2_clkctrl: clock@c {
2062 compatible = "ti,clkctrl";
2063 clock-output-names = "l4per2_clkctrl";
2064 reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
2065 #clock-cells = <2>;
2066 };
2067
2068 l4per3_clkctrl: clock@14 {
2069 compatible = "ti,clkctrl";
2070 clock-output-names = "l4per3_clkctrl";
2071 reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
2072 #clock-cells = <2>;
2073 };
2074 };
2075
2076 };
2077
2078 &prm {
2079 wkupaon_cm: clock@1800 {
2080 compatible = "ti,omap4-cm";
2081 clock-output-names = "wkupaon_cm";
2082 reg = <0x1800 0x100>;
2083 #address-cells = <1>;
2084 #size-cells = <1>;
2085 ranges = <0 0x1800 0x100>;
2086
2087 wkupaon_clkctrl: clock@20 {
2088 compatible = "ti,clkctrl";
2089 clock-output-names = "wkupaon_clkctrl";
2090 reg = <0x20 0x6c>;
2091 #clock-cells = <2>;
2092 };
2093 };
2094 };
