0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 #include "dra74x.dtsi"
0007
0008 / {
0009 compatible = "ti,dra762", "ti,dra7";
0010
0011 ocp {
0012 target-module@42c01900 {
0013 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
0014 ranges = <0x0 0x42c00000 0x2000>;
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017 reg = <0x42c01900 0x4>,
0018 <0x42c01904 0x4>,
0019 <0x42c01908 0x4>;
0020 reg-names = "rev", "sysc", "syss";
0021 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
0022 SYSC_DRA7_MCAN_ENAWAKEUP)>;
0023 ti,syss-mask = <1>;
0024 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
0025 clock-names = "fck";
0026
0027 m_can0: mcan@1a00 {
0028 compatible = "bosch,m_can";
0029 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
0030 reg-names = "m_can", "message_ram";
0031 interrupt-parent = <&gic>;
0032 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
0033 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0034 interrupt-names = "int0", "int1";
0035 clocks = <&l3_iclk_div>, <&mcan_clk>;
0036 clock-names = "hclk", "cclk";
0037 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
0038 };
0039 };
0040 };
0041
0042 };
0043
0044 &l4_per3 {
0045 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
0046 compatible = "ti,sysc-omap4", "ti,sysc";
0047 reg = <0x1b0000 0x4>,
0048 <0x1b0010 0x4>;
0049 reg-names = "rev", "sysc";
0050 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0051 <SYSC_IDLE_NO>;
0052 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0053 <SYSC_IDLE_NO>;
0054 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
0055 clock-names = "fck";
0056 #address-cells = <1>;
0057 #size-cells = <1>;
0058 ranges = <0x0 0x1b0000 0x10000>;
0059
0060 cal: cal@0 {
0061 compatible = "ti,dra76-cal";
0062 reg = <0x0000 0x400>,
0063 <0x0800 0x40>,
0064 <0x0900 0x40>;
0065 reg-names = "cal_top",
0066 "cal_rx_core0",
0067 "cal_rx_core1";
0068 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
0069 ti,camerrx-control = <&scm_conf 0x6dc>;
0070
0071 ports {
0072 #address-cells = <1>;
0073 #size-cells = <0>;
0074
0075 csi2_0: port@0 {
0076 reg = <0>;
0077 };
0078 csi2_1: port@1 {
0079 reg = <1>;
0080 };
0081 };
0082 };
0083 };
0084 };
0085
0086 &scm_conf_clocks {
0087 dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
0088 #clock-cells = <0>;
0089 compatible = "ti,divider-clock";
0090 clocks = <&dpll_gmac_x2_ck>;
0091 ti,max-div = <63>;
0092 reg = <0x03fc>;
0093 ti,bit-shift = <20>;
0094 ti,latch-bit = <26>;
0095 assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
0096 assigned-clock-rates = <80000000>;
0097 };
0098
0099 dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
0100 #clock-cells = <0>;
0101 compatible = "ti,mux-clock";
0102 clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
0103 reg = <0x3fc>;
0104 ti,bit-shift = <29>;
0105 ti,latch-bit = <26>;
0106 assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
0107 assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
0108 };
0109
0110 mcan_clk: mcan_clk@3fc {
0111 #clock-cells = <0>;
0112 compatible = "ti,gate-clock";
0113 clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
0114 ti,bit-shift = <27>;
0115 reg = <0x3fc>;
0116 };
0117 };
0118
0119 &rtctarget {
0120 status = "disabled";
0121 };
0122
0123 &usb4_tm {
0124 status = "disabled";
0125 };
0126
0127 &mmc3 {
0128 /* dra76x is not affected by i887 */
0129 max-frequency = <96000000>;
0130 };
0131
0132 &cpu0_opp_table {
0133 opp_plus@1800000000 {
0134 opp-hz = /bits/ 64 <1800000000>;
0135 opp-microvolt = <1250000 950000 1250000>,
0136 <1250000 950000 1250000>;
0137 opp-supported-hw = <0xFF 0x08>;
0138 };
0139 };
0140
0141 &opp_supply_mpu {
0142 ti,efuse-settings = <
0143 /* uV offset */
0144 1060000 0x0
0145 1160000 0x4
0146 1210000 0x8
0147 1250000 0xC
0148 >;
0149 };
0150
0151 &abb_mpu {
0152 ti,abb_info = <
0153 /*uV ABB efuse rbb_m fbb_m vset_m*/
0154 1060000 0 0x0 0 0x02000000 0x01F00000
0155 1160000 0 0x4 0 0x02000000 0x01F00000
0156 1210000 0 0x8 0 0x02000000 0x01F00000
0157 1250000 0 0xC 0 0x02000000 0x01F00000
0158 >;
0159 };
