0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
0004 *
0005 * Based on "omap4.dtsi"
0006 */
0007
0008 #include "dra7.dtsi"
0009
0010 / {
0011 compatible = "ti,dra742", "ti,dra74", "ti,dra7";
0012
0013 cpus {
0014 cpu@1 {
0015 device_type = "cpu";
0016 compatible = "arm,cortex-a15";
0017 reg = <1>;
0018 operating-points-v2 = <&cpu0_opp_table>;
0019
0020 clocks = <&dpll_mpu_ck>;
0021 clock-names = "cpu";
0022
0023 clock-latency = <300000>; /* From omap-cpufreq driver */
0024
0025 /* cooling options */
0026 #cooling-cells = <2>; /* min followed by max */
0027
0028 vbb-supply = <&abb_mpu>;
0029 };
0030 };
0031
0032 aliases {
0033 rproc0 = &ipu1;
0034 rproc1 = &ipu2;
0035 rproc2 = &dsp1;
0036 rproc3 = &dsp2;
0037 };
0038
0039 pmu {
0040 compatible = "arm,cortex-a15-pmu";
0041 interrupt-parent = <&wakeupgen>;
0042 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0043 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
0044 };
0045
0046 ocp {
0047 dsp2_system: dsp_system@41500000 {
0048 compatible = "syscon";
0049 reg = <0x41500000 0x100>;
0050 };
0051
0052
0053 target-module@41501000 {
0054 compatible = "ti,sysc-omap2", "ti,sysc";
0055 reg = <0x41501000 0x4>,
0056 <0x41501010 0x4>,
0057 <0x41501014 0x4>;
0058 reg-names = "rev", "sysc", "syss";
0059 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0060 <SYSC_IDLE_NO>,
0061 <SYSC_IDLE_SMART>;
0062 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0063 SYSC_OMAP2_SOFTRESET |
0064 SYSC_OMAP2_AUTOIDLE)>;
0065 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
0066 clock-names = "fck";
0067 resets = <&prm_dsp2 1>;
0068 reset-names = "rstctrl";
0069 ranges = <0x0 0x41501000 0x1000>;
0070 #size-cells = <1>;
0071 #address-cells = <1>;
0072
0073 mmu0_dsp2: mmu@0 {
0074 compatible = "ti,dra7-dsp-iommu";
0075 reg = <0x0 0x100>;
0076 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0077 #iommu-cells = <0>;
0078 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
0079 };
0080 };
0081
0082 target-module@41502000 {
0083 compatible = "ti,sysc-omap2", "ti,sysc";
0084 reg = <0x41502000 0x4>,
0085 <0x41502010 0x4>,
0086 <0x41502014 0x4>;
0087 reg-names = "rev", "sysc", "syss";
0088 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0089 <SYSC_IDLE_NO>,
0090 <SYSC_IDLE_SMART>;
0091 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0092 SYSC_OMAP2_SOFTRESET |
0093 SYSC_OMAP2_AUTOIDLE)>;
0094
0095 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
0096 clock-names = "fck";
0097 resets = <&prm_dsp2 1>;
0098 reset-names = "rstctrl";
0099 ranges = <0x0 0x41502000 0x1000>;
0100 #size-cells = <1>;
0101 #address-cells = <1>;
0102
0103 mmu1_dsp2: mmu@0 {
0104 compatible = "ti,dra7-dsp-iommu";
0105 reg = <0x0 0x100>;
0106 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0107 #iommu-cells = <0>;
0108 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
0109 };
0110 };
0111
0112 dsp2: dsp@41000000 {
0113 compatible = "ti,dra7-dsp";
0114 reg = <0x41000000 0x48000>,
0115 <0x41600000 0x8000>,
0116 <0x41700000 0x8000>;
0117 reg-names = "l2ram", "l1pram", "l1dram";
0118 ti,bootreg = <&scm_conf 0x560 10>;
0119 iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
0120 status = "disabled";
0121 resets = <&prm_dsp2 0>;
0122 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
0123 firmware-name = "dra7-dsp2-fw.xe66";
0124 };
0125 };
0126 };
0127
0128 &cpu0_opp_table {
0129 opp-shared;
0130 };
0131
0132 &dss {
0133 reg = <0 0x80>,
0134 <0x4054 0x4>,
0135 <0x4300 0x20>,
0136 <0x9054 0x4>,
0137 <0x9300 0x20>;
0138 reg-names = "dss", "pll1_clkctrl", "pll1",
0139 "pll2_clkctrl", "pll2";
0140
0141 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
0142 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
0143 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
0144 clock-names = "fck", "video1_clk", "video2_clk";
0145 };
0146
0147 &mailbox5 {
0148 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
0149 ti,mbox-tx = <6 2 2>;
0150 ti,mbox-rx = <4 2 2>;
0151 status = "disabled";
0152 };
0153 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
0154 ti,mbox-tx = <5 2 2>;
0155 ti,mbox-rx = <1 2 2>;
0156 status = "disabled";
0157 };
0158 };
0159
0160 &mailbox6 {
0161 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
0162 ti,mbox-tx = <6 2 2>;
0163 ti,mbox-rx = <4 2 2>;
0164 status = "disabled";
0165 };
0166 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
0167 ti,mbox-tx = <5 2 2>;
0168 ti,mbox-rx = <1 2 2>;
0169 status = "disabled";
0170 };
0171 };
0172
0173 &pcie1_rc {
0174 compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
0175 };
0176
0177 &pcie1_ep {
0178 compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
0179 };
0180
0181 &pcie2_rc {
0182 compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
0183 };
0184
0185 &l4_per3 {
0186 segment@0 {
0187 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
0188 compatible = "ti,sysc-omap4", "ti,sysc";
0189 reg = <0x140000 0x4>,
0190 <0x140010 0x4>;
0191 reg-names = "rev", "sysc";
0192 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
0193 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0194 <SYSC_IDLE_NO>,
0195 <SYSC_IDLE_SMART>,
0196 <SYSC_IDLE_SMART_WKUP>;
0197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0198 <SYSC_IDLE_NO>,
0199 <SYSC_IDLE_SMART>,
0200 <SYSC_IDLE_SMART_WKUP>;
0201 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
0202 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
0203 clock-names = "fck";
0204 #address-cells = <1>;
0205 #size-cells = <1>;
0206 ranges = <0x0 0x140000 0x20000>;
0207
0208 omap_dwc3_4: omap_dwc3_4@0 {
0209 compatible = "ti,dwc3";
0210 reg = <0 0x10000>;
0211 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 utmi-mode = <2>;
0215 ranges;
0216 status = "disabled";
0217 usb4: usb@10000 {
0218 compatible = "snps,dwc3";
0219 reg = <0x10000 0x17000>;
0220 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
0221 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
0222 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
0223 interrupt-names = "peripheral",
0224 "host",
0225 "otg";
0226 maximum-speed = "high-speed";
0227 dr_mode = "otg";
0228 };
0229 };
0230 };
0231 };
0232 };
