boot/dts/dra72x.dtsi

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
0004  *
0005  * Based on "omap4.dtsi"
0006  */
0007
0008 #include "dra7.dtsi"
0009
0010 / {
0011         compatible = "ti,dra722", "ti,dra72", "ti,dra7";
0012
0013         aliases {
0014                 rproc0 = &ipu1;
0015                 rproc1 = &ipu2;
0016                 rproc2 = &dsp1;
0017         };
0018
0019         pmu {
0020                 compatible = "arm,cortex-a15-pmu";
0021                 interrupt-parent = <&wakeupgen>;
0022                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0023         };
0024 };
0025
0026 &l4_per2 {
0027         target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
0028                 compatible = "ti,sysc-omap4", "ti,sysc";
0029                 reg = <0x5b000 0x4>,
0030                       <0x5b010 0x4>;
0031                 reg-names = "rev", "sysc";
0032                 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0033                                 <SYSC_IDLE_NO>;
0034                 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0035                                 <SYSC_IDLE_NO>;
0036                 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
0037                 clock-names = "fck";
0038                 #address-cells = <1>;
0039                 #size-cells = <1>;
0040                 ranges = <0x0 0x5b000 0x1000>;
0041
0042                 cal: cal@0 {
0043                         compatible = "ti,dra72-cal";
0044                         reg = <0x0000 0x400>,
0045                               <0x0800 0x40>,
0046                               <0x0900 0x40>;
0047                         reg-names = "cal_top",
0048                                     "cal_rx_core0",
0049                                     "cal_rx_core1";
0050                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0051                         ti,camerrx-control = <&scm_conf 0xE94>;
0052
0053                         ports {
0054                                 #address-cells = <1>;
0055                                 #size-cells = <0>;
0056
0057                                 csi2_0: port@0 {
0058                                         reg = <0>;
0059                                 };
0060                                 csi2_1: port@1 {
0061                                         reg = <1>;
0062                                 };
0063                         };
0064                 };
0065         };
0066 };
0067
0068 &dss {
0069         reg = <0 0x80>,
0070               <0x4054 0x4>,
0071               <0x4300 0x20>;
0072         reg-names = "dss", "pll1_clkctrl", "pll1";
0073
0074         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
0075                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
0076         clock-names = "fck", "video1_clk";
0077 };
0078
0079 &mailbox5 {
0080         mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
0081                 ti,mbox-tx = <6 2 2>;
0082                 ti,mbox-rx = <4 2 2>;
0083                 status = "disabled";
0084         };
0085         mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
0086                 ti,mbox-tx = <5 2 2>;
0087                 ti,mbox-rx = <1 2 2>;
0088                 status = "disabled";
0089         };
0090 };
0091
0092 &mailbox6 {
0093         mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
0094                 ti,mbox-tx = <6 2 2>;
0095                 ti,mbox-rx = <4 2 2>;
0096                 status = "disabled";
0097         };
0098 };
0099
0100 &pcie1_rc {
0101         compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
0102 };
0103
0104 &pcie1_ep {
0105         compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
0106 };
0107
0108 &pcie2_rc {
0109         compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
0110 };