boot/dts/dra72-evm.dts

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
0004  */
0005 #include "dra72-evm-common.dtsi"
0006 #include "dra72x-mmc-iodelay.dtsi"
0007 / {
0008         model = "TI DRA722";
0009
0010         memory@0 {
0011                 device_type = "memory";
0012                 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
0013         };
0014
0015         reserved-memory {
0016                 #address-cells = <2>;
0017                 #size-cells = <2>;
0018                 ranges;
0019
0020                 ipu2_memory_region: ipu2-memory@95800000 {
0021                         compatible = "shared-dma-pool";
0022                         reg = <0x0 0x95800000 0x0 0x3800000>;
0023                         reusable;
0024                         status = "okay";
0025                 };
0026
0027                 dsp1_memory_region: dsp1-memory@99000000 {
0028                         compatible = "shared-dma-pool";
0029                         reg = <0x0 0x99000000 0x0 0x4000000>;
0030                         reusable;
0031                         status = "okay";
0032                 };
0033
0034                 ipu1_memory_region: ipu1-memory@9d000000 {
0035                         compatible = "shared-dma-pool";
0036                         reg = <0x0 0x9d000000 0x0 0x2000000>;
0037                         reusable;
0038                         status = "okay";
0039                 };
0040         };
0041
0042         evm_1v8_sw: fixedregulator-evm_1v8 {
0043                 compatible = "regulator-fixed";
0044                 regulator-name = "evm_1v8";
0045                 regulator-min-microvolt = <1800000>;
0046                 regulator-max-microvolt = <1800000>;
0047                 vin-supply = <&smps4_reg>;
0048                 regulator-always-on;
0049                 regulator-boot-on;
0050         };
0051 };
0052
0053 &i2c1 {
0054         tps65917: tps65917@58 {
0055                 reg = <0x58>;
0056
0057                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
0058         };
0059 };
0060
0061 #include "dra72-evm-tps65917.dtsi"
0062
0063 &hdmi {
0064         vdda-supply = <&ldo3_reg>;
0065 };
0066
0067 &pcf_gpio_21 {
0068         interrupt-parent = <&gpio6>;
0069         interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
0070 };
0071
0072 &mac_sw {
0073         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
0074         status = "okay";
0075 };
0076
0077 &cpsw_port1 {
0078         phy-handle = <&ethphy0>;
0079         phy-mode = "rgmii";
0080         ti,dual-emac-pvid = <1>;
0081 };
0082
0083 &cpsw_port2 {
0084         status = "disabled";
0085 };
0086
0087 &davinci_mdio_sw {
0088         ethphy0: ethernet-phy@3 {
0089                 reg = <3>;
0090         };
0091 };
0092
0093 &mmc1 {
0094         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
0095         pinctrl-0 = <&mmc1_pins_default>;
0096         pinctrl-1 = <&mmc1_pins_hs>;
0097         pinctrl-2 = <&mmc1_pins_sdr12>;
0098         pinctrl-3 = <&mmc1_pins_sdr25>;
0099         pinctrl-4 = <&mmc1_pins_sdr50>;
0100         pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
0101         pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
0102         vqmmc-supply = <&ldo1_reg>;
0103 };
0104
0105 &mmc2 {
0106         pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
0107         pinctrl-0 = <&mmc2_pins_default>;
0108         pinctrl-1 = <&mmc2_pins_hs>;
0109         pinctrl-2 = <&mmc2_pins_ddr_rev10>;
0110         pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
0111         vmmc-supply = <&evm_1v8_sw>;
0112 };
0113
0114 &ipu2 {
0115         status = "okay";
0116         memory-region = <&ipu2_memory_region>;
0117 };
0118
0119 &ipu1 {
0120         status = "okay";
0121         memory-region = <&ipu1_memory_region>;
0122 };
0123
0124 &dsp1 {
0125         status = "okay";
0126         memory-region = <&dsp1_memory_region>;
0127 };