0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005 #include "dra72-evm-common.dtsi"
0006 #include "dra72x-mmc-iodelay.dtsi"
0007 #include <dt-bindings/net/ti-dp83867.h>
0008
0009 / {
0010 model = "TI DRA722 Rev C EVM";
0011
0012 memory@0 {
0013 device_type = "memory";
0014 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
0015 };
0016
0017 reserved-memory {
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020 ranges;
0021
0022 ipu2_cma_pool: ipu2_cma@95800000 {
0023 compatible = "shared-dma-pool";
0024 reg = <0x0 0x95800000 0x0 0x3800000>;
0025 reusable;
0026 status = "okay";
0027 };
0028
0029 dsp1_cma_pool: dsp1_cma@99000000 {
0030 compatible = "shared-dma-pool";
0031 reg = <0x0 0x99000000 0x0 0x4000000>;
0032 reusable;
0033 status = "okay";
0034 };
0035
0036 ipu1_cma_pool: ipu1_cma@9d000000 {
0037 compatible = "shared-dma-pool";
0038 reg = <0x0 0x9d000000 0x0 0x2000000>;
0039 reusable;
0040 status = "okay";
0041 };
0042 };
0043
0044 evm_1v8_sw: fixedregulator-evm_1v8 {
0045 compatible = "regulator-fixed";
0046 regulator-name = "evm_1v8";
0047 regulator-min-microvolt = <1800000>;
0048 regulator-max-microvolt = <1800000>;
0049 vin-supply = <&smps4_reg>;
0050 regulator-always-on;
0051 regulator-boot-on;
0052 };
0053 };
0054
0055 &i2c1 {
0056 tps65917: tps65917@58 {
0057 reg = <0x58>;
0058
0059 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
0060 };
0061 };
0062
0063 #include "dra72-evm-tps65917.dtsi"
0064
0065 &ldo2_reg {
0066 /* LDO2_OUT --> VDDA_1V8_PHY2 */
0067 regulator-always-on;
0068 regulator-boot-on;
0069 };
0070
0071 &hdmi {
0072 vdda-supply = <&ldo2_reg>;
0073 };
0074
0075 &pcf_gpio_21 {
0076 interrupt-parent = <&gpio3>;
0077 interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
0078 };
0079
0080 &mac_sw {
0081 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
0082 <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
0083 <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
0084 status = "okay";
0085 };
0086
0087 &cpsw_port1 {
0088 phy-handle = <&dp83867_0>;
0089 phy-mode = "rgmii-id";
0090 ti,dual-emac-pvid = <1>;
0091 };
0092
0093 &cpsw_port2 {
0094 phy-handle = <&dp83867_1>;
0095 phy-mode = "rgmii-id";
0096 ti,dual-emac-pvid = <2>;
0097 };
0098
0099 &davinci_mdio_sw {
0100 dp83867_0: ethernet-phy@2 {
0101 reg = <2>;
0102 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0103 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
0104 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
0105 ti,min-output-impedance;
0106 interrupt-parent = <&gpio6>;
0107 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
0108 ti,dp83867-rxctrl-strap-quirk;
0109 };
0110
0111 dp83867_1: ethernet-phy@3 {
0112 reg = <3>;
0113 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0114 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
0115 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
0116 ti,min-output-impedance;
0117 interrupt-parent = <&gpio6>;
0118 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
0119 ti,dp83867-rxctrl-strap-quirk;
0120 };
0121 };
0122
0123 &mmc1 {
0124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
0125 pinctrl-0 = <&mmc1_pins_default>;
0126 pinctrl-1 = <&mmc1_pins_hs>;
0127 pinctrl-2 = <&mmc1_pins_sdr12>;
0128 pinctrl-3 = <&mmc1_pins_sdr25>;
0129 pinctrl-4 = <&mmc1_pins_sdr50>;
0130 pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
0131 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
0132 vqmmc-supply = <&ldo1_reg>;
0133 };
0134
0135 &mmc2 {
0136 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
0137 pinctrl-0 = <&mmc2_pins_default>;
0138 pinctrl-1 = <&mmc2_pins_hs>;
0139 pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
0140 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
0141 vmmc-supply = <&evm_1v8_sw>;
0142 };
0143
0144 &ipu2 {
0145 status = "okay";
0146 memory-region = <&ipu2_cma_pool>;
0147 };
0148
0149 &ipu1 {
0150 status = "okay";
0151 memory-region = <&ipu1_cma_pool>;
0152 };
0153
0154 &dsp1 {
0155 status = "okay";
0156 memory-region = <&dsp1_cma_pool>;
0157 };
