0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005 /dts-v1/;
0006
0007 #include "dra72x.dtsi"
0008 #include "dra7-ipu-dsp-common.dtsi"
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/clock/ti-dra7-atl.h>
0011
0012 / {
0013 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
0014
0015 aliases {
0016 display0 = &hdmi0;
0017 };
0018
0019 chosen {
0020 stdout-path = &uart1;
0021 };
0022
0023 evm_12v0: fixedregulator-evm12v0 {
0024 /* main supply */
0025 compatible = "regulator-fixed";
0026 regulator-name = "evm_12v0";
0027 regulator-min-microvolt = <12000000>;
0028 regulator-max-microvolt = <12000000>;
0029 regulator-always-on;
0030 regulator-boot-on;
0031 };
0032
0033 evm_5v0: fixedregulator-evm5v0 {
0034 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
0035 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
0036 compatible = "regulator-fixed";
0037 regulator-name = "evm_5v0";
0038 regulator-min-microvolt = <5000000>;
0039 regulator-max-microvolt = <5000000>;
0040 vin-supply = <&evm_12v0>;
0041 regulator-always-on;
0042 regulator-boot-on;
0043 };
0044
0045 evm_3v6: fixedregulator-evm_3v6 {
0046 compatible = "regulator-fixed";
0047 regulator-name = "evm_3v6";
0048 regulator-min-microvolt = <3600000>;
0049 regulator-max-microvolt = <3600000>;
0050 vin-supply = <&evm_5v0>;
0051 regulator-always-on;
0052 regulator-boot-on;
0053 };
0054
0055 vsys_3v3: fixedregulator-vsys3v3 {
0056 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
0057 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
0058 compatible = "regulator-fixed";
0059 regulator-name = "vsys_3v3";
0060 regulator-min-microvolt = <3300000>;
0061 regulator-max-microvolt = <3300000>;
0062 vin-supply = <&evm_12v0>;
0063 regulator-always-on;
0064 regulator-boot-on;
0065 };
0066
0067 evm_3v3_sw: fixedregulator-evm_3v3 {
0068 /* TPS22965DSG */
0069 compatible = "regulator-fixed";
0070 regulator-name = "evm_3v3";
0071 regulator-min-microvolt = <3300000>;
0072 regulator-max-microvolt = <3300000>;
0073 vin-supply = <&vsys_3v3>;
0074 regulator-always-on;
0075 regulator-boot-on;
0076 };
0077
0078 aic_dvdd: fixedregulator-aic_dvdd {
0079 /* TPS77018DBVT */
0080 compatible = "regulator-fixed";
0081 regulator-name = "aic_dvdd";
0082 vin-supply = <&evm_3v3_sw>;
0083 regulator-min-microvolt = <1800000>;
0084 regulator-max-microvolt = <1800000>;
0085 };
0086
0087 evm_3v3_sd: fixedregulator-sd {
0088 compatible = "regulator-fixed";
0089 regulator-name = "evm_3v3_sd";
0090 regulator-min-microvolt = <3300000>;
0091 regulator-max-microvolt = <3300000>;
0092 vin-supply = <&evm_3v3_sw>;
0093 enable-active-high;
0094 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
0095 };
0096
0097 extcon_usb1: extcon_usb1 {
0098 compatible = "linux,extcon-usb-gpio";
0099 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
0100 };
0101
0102 extcon_usb2: extcon_usb2 {
0103 compatible = "linux,extcon-usb-gpio";
0104 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
0105 };
0106
0107 hdmi0: connector {
0108 compatible = "hdmi-connector";
0109 label = "hdmi";
0110
0111 type = "a";
0112
0113 port {
0114 hdmi_connector_in: endpoint {
0115 remote-endpoint = <&tpd12s015_out>;
0116 };
0117 };
0118 };
0119
0120 tpd12s015: encoder {
0121 compatible = "ti,tpd12s015";
0122
0123 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
0124 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
0125 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
0126
0127 ports {
0128 #address-cells = <1>;
0129 #size-cells = <0>;
0130
0131 port@0 {
0132 reg = <0>;
0133
0134 tpd12s015_in: endpoint {
0135 remote-endpoint = <&hdmi_out>;
0136 };
0137 };
0138
0139 port@1 {
0140 reg = <1>;
0141
0142 tpd12s015_out: endpoint {
0143 remote-endpoint = <&hdmi_connector_in>;
0144 };
0145 };
0146 };
0147 };
0148
0149 sound0: sound0 {
0150 compatible = "simple-audio-card";
0151 simple-audio-card,name = "DRA7xx-EVM";
0152 simple-audio-card,widgets =
0153 "Headphone", "Headphone Jack",
0154 "Line", "Line Out",
0155 "Microphone", "Mic Jack",
0156 "Line", "Line In";
0157 simple-audio-card,routing =
0158 "Headphone Jack", "HPLOUT",
0159 "Headphone Jack", "HPROUT",
0160 "Line Out", "LLOUT",
0161 "Line Out", "RLOUT",
0162 "MIC3L", "Mic Jack",
0163 "MIC3R", "Mic Jack",
0164 "Mic Jack", "Mic Bias",
0165 "LINE1L", "Line In",
0166 "LINE1R", "Line In";
0167 simple-audio-card,format = "dsp_b";
0168 simple-audio-card,bitclock-master = <&sound0_master>;
0169 simple-audio-card,frame-master = <&sound0_master>;
0170 simple-audio-card,bitclock-inversion;
0171
0172 sound0_master: simple-audio-card,cpu {
0173 sound-dai = <&mcasp3>;
0174 system-clock-frequency = <5644800>;
0175 };
0176
0177 simple-audio-card,codec {
0178 sound-dai = <&tlv320aic3106>;
0179 clocks = <&atl_clkin2_ck>;
0180 };
0181 };
0182
0183 vmmcwl_fixed: fixedregulator-mmcwl {
0184 compatible = "regulator-fixed";
0185 regulator-name = "vmmcwl_fixed";
0186 regulator-min-microvolt = <1800000>;
0187 regulator-max-microvolt = <1800000>;
0188 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
0189 enable-active-high;
0190 };
0191
0192 clk_ov5640_fixed: clock {
0193 compatible = "fixed-clock";
0194 #clock-cells = <0>;
0195 clock-frequency = <24000000>;
0196 };
0197 };
0198
0199 &dra7_pmx_core {
0200 dcan1_pins_default: dcan1_pins_default {
0201 pinctrl-single,pins = <
0202 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0203 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
0204 >;
0205 };
0206
0207 dcan1_pins_sleep: dcan1_pins_sleep {
0208 pinctrl-single,pins = <
0209 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0210 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
0211 >;
0212 };
0213 };
0214
0215 &i2c1 {
0216 status = "okay";
0217 clock-frequency = <400000>;
0218
0219 pcf_lcd: gpio@20 {
0220 compatible = "nxp,pcf8575";
0221 reg = <0x20>;
0222 gpio-controller;
0223 #gpio-cells = <2>;
0224 interrupt-controller;
0225 #interrupt-cells = <2>;
0226 };
0227
0228 pcf_gpio_21: gpio@21 {
0229 compatible = "nxp,pcf8575";
0230 reg = <0x21>;
0231 lines-initial-states = <0x1408>;
0232 gpio-controller;
0233 #gpio-cells = <2>;
0234 interrupt-controller;
0235 #interrupt-cells = <2>;
0236 };
0237
0238 tlv320aic3106: tlv320aic3106@19 {
0239 #sound-dai-cells = <0>;
0240 compatible = "ti,tlv320aic3106";
0241 reg = <0x19>;
0242 adc-settle-ms = <40>;
0243 ai3x-micbias-vg = <1>; /* 2.0V */
0244 status = "okay";
0245
0246 /* Regulators */
0247 AVDD-supply = <&evm_3v3_sw>;
0248 IOVDD-supply = <&evm_3v3_sw>;
0249 DRVDD-supply = <&evm_3v3_sw>;
0250 DVDD-supply = <&aic_dvdd>;
0251 };
0252 };
0253
0254 &i2c5 {
0255 status = "okay";
0256 clock-frequency = <400000>;
0257
0258 pcf_hdmi: pcf8575@26 {
0259 compatible = "nxp,pcf8575";
0260 reg = <0x26>;
0261 gpio-controller;
0262 #gpio-cells = <2>;
0263 /*
0264 * initial state is used here to keep the mdio interface
0265 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
0266 * VIN2_S0 driven high otherwise Ethernet stops working
0267 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
0268 */
0269 lines-initial-states = <0x0f2b>;
0270
0271 hdmi-audio-hog {
0272 /* vin6_sel_s0: high: VIN6, low: audio */
0273 gpio-hog;
0274 gpios = <1 GPIO_ACTIVE_HIGH>;
0275 output-low;
0276 line-name = "vin6_sel_s0";
0277 };
0278 };
0279
0280 ov5640@3c {
0281 compatible = "ovti,ov5640";
0282 reg = <0x3c>;
0283
0284 clocks = <&clk_ov5640_fixed>;
0285 clock-names = "xclk";
0286
0287 port {
0288 csi2_cam0: endpoint {
0289 remote-endpoint = <&csi2_phy0>;
0290 clock-lanes = <0>;
0291 data-lanes = <1 2>;
0292 };
0293 };
0294 };
0295
0296 };
0297
0298 &uart1 {
0299 status = "okay";
0300 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
0301 <&dra7_pmx_core 0x3e0>;
0302 };
0303
0304 &elm {
0305 status = "okay";
0306 };
0307
0308 &gpmc {
0309 /*
0310 * For the existing IOdelay configuration via U-Boot we don't
0311 * support NAND on dra72-evm. Keep it disabled. Enabling it
0312 * requires a different configuration by U-Boot.
0313 */
0314 status = "disabled";
0315 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
0316 nand@0,0 {
0317 /* To use NAND, DIP switch SW5 must be set like so:
0318 * SW5.1 (NAND_SELn) = ON (LOW)
0319 * SW5.9 (GPMC_WPN) = OFF (HIGH)
0320 */
0321 compatible = "ti,omap2-nand";
0322 reg = <0 0 4>; /* device IO registers */
0323 interrupt-parent = <&gpmc>;
0324 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0325 <1 IRQ_TYPE_NONE>; /* termcount */
0326 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
0327 ti,nand-xfer-type = "prefetch-dma";
0328 ti,nand-ecc-opt = "bch8";
0329 ti,elm-id = <&elm>;
0330 nand-bus-width = <16>;
0331 gpmc,device-width = <2>;
0332 gpmc,sync-clk-ps = <0>;
0333 gpmc,cs-on-ns = <0>;
0334 gpmc,cs-rd-off-ns = <80>;
0335 gpmc,cs-wr-off-ns = <80>;
0336 gpmc,adv-on-ns = <0>;
0337 gpmc,adv-rd-off-ns = <60>;
0338 gpmc,adv-wr-off-ns = <60>;
0339 gpmc,we-on-ns = <10>;
0340 gpmc,we-off-ns = <50>;
0341 gpmc,oe-on-ns = <4>;
0342 gpmc,oe-off-ns = <40>;
0343 gpmc,access-ns = <40>;
0344 gpmc,wr-access-ns = <80>;
0345 gpmc,rd-cycle-ns = <80>;
0346 gpmc,wr-cycle-ns = <80>;
0347 gpmc,bus-turnaround-ns = <0>;
0348 gpmc,cycle2cycle-delay-ns = <0>;
0349 gpmc,clk-activation-ns = <0>;
0350 gpmc,wr-data-mux-bus-ns = <0>;
0351 /* MTD partition table */
0352 /* All SPL-* partitions are sized to minimal length
0353 * which can be independently programmable. For
0354 * NAND flash this is equal to size of erase-block */
0355 #address-cells = <1>;
0356 #size-cells = <1>;
0357 partition@0 {
0358 label = "NAND.SPL";
0359 reg = <0x00000000 0x000020000>;
0360 };
0361 partition@1 {
0362 label = "NAND.SPL.backup1";
0363 reg = <0x00020000 0x00020000>;
0364 };
0365 partition@2 {
0366 label = "NAND.SPL.backup2";
0367 reg = <0x00040000 0x00020000>;
0368 };
0369 partition@3 {
0370 label = "NAND.SPL.backup3";
0371 reg = <0x00060000 0x00020000>;
0372 };
0373 partition@4 {
0374 label = "NAND.u-boot-spl-os";
0375 reg = <0x00080000 0x00040000>;
0376 };
0377 partition@5 {
0378 label = "NAND.u-boot";
0379 reg = <0x000c0000 0x00100000>;
0380 };
0381 partition@6 {
0382 label = "NAND.u-boot-env";
0383 reg = <0x001c0000 0x00020000>;
0384 };
0385 partition@7 {
0386 label = "NAND.u-boot-env.backup1";
0387 reg = <0x001e0000 0x00020000>;
0388 };
0389 partition@8 {
0390 label = "NAND.kernel";
0391 reg = <0x00200000 0x00800000>;
0392 };
0393 partition@9 {
0394 label = "NAND.file-system";
0395 reg = <0x00a00000 0x0f600000>;
0396 };
0397 };
0398 };
0399
0400 &omap_dwc3_1 {
0401 extcon = <&extcon_usb1>;
0402 };
0403
0404 &omap_dwc3_2 {
0405 extcon = <&extcon_usb2>;
0406 };
0407
0408 &usb1 {
0409 dr_mode = "otg";
0410 extcon = <&extcon_usb1>;
0411 };
0412
0413 &usb2 {
0414 dr_mode = "host";
0415 extcon = <&extcon_usb2>;
0416 };
0417
0418 &mmc1 {
0419 status = "okay";
0420 pinctrl-names = "default";
0421 pinctrl-0 = <&mmc1_pins_default>;
0422 vmmc-supply = <&evm_3v3_sd>;
0423 bus-width = <4>;
0424 /*
0425 * SDCD signal is not being used here - using the fact that GPIO mode
0426 * is a viable alternative
0427 */
0428 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
0429 max-frequency = <192000000>;
0430 };
0431
0432 &mmc2 {
0433 /* SW5-3 in ON position */
0434 status = "okay";
0435 pinctrl-names = "default";
0436 pinctrl-0 = <&mmc2_pins_default>;
0437 bus-width = <8>;
0438 non-removable;
0439 max-frequency = <192000000>;
0440 };
0441
0442 &mmc4 {
0443 status = "okay";
0444 vmmc-supply = <&evm_3v6>;
0445 vqmmc-supply = <&vmmcwl_fixed>;
0446 bus-width = <4>;
0447 cap-power-off-card;
0448 keep-power-in-suspend;
0449 non-removable;
0450 pinctrl-names = "default", "hs", "sdr12", "sdr25";
0451 pinctrl-0 = <&mmc4_pins_default>;
0452 pinctrl-1 = <&mmc4_pins_default>;
0453 pinctrl-2 = <&mmc4_pins_default>;
0454 pinctrl-3 = <&mmc4_pins_default>;
0455 #address-cells = <1>;
0456 #size-cells = <0>;
0457 wifi@2 {
0458 compatible = "ti,wl1835";
0459 reg = <2>;
0460 interrupt-parent = <&gpio5>;
0461 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
0462 };
0463 };
0464
0465 &dcan1 {
0466 status = "okay";
0467 pinctrl-names = "default", "sleep", "active";
0468 pinctrl-0 = <&dcan1_pins_sleep>;
0469 pinctrl-1 = <&dcan1_pins_sleep>;
0470 pinctrl-2 = <&dcan1_pins_default>;
0471 };
0472
0473 &qspi {
0474 status = "okay";
0475
0476 spi-max-frequency = <76800000>;
0477 flash@0 {
0478 compatible = "s25fl256s1";
0479 spi-max-frequency = <76800000>;
0480 reg = <0>;
0481 spi-tx-bus-width = <1>;
0482 spi-rx-bus-width = <4>;
0483 #address-cells = <1>;
0484 #size-cells = <1>;
0485
0486 /* MTD partition table.
0487 * The ROM checks the first four physical blocks
0488 * for a valid file to boot and the flash here is
0489 * 64KiB block size.
0490 */
0491 partition@0 {
0492 label = "QSPI.SPL";
0493 reg = <0x00000000 0x000010000>;
0494 };
0495 partition@1 {
0496 label = "QSPI.SPL.backup1";
0497 reg = <0x00010000 0x00010000>;
0498 };
0499 partition@2 {
0500 label = "QSPI.SPL.backup2";
0501 reg = <0x00020000 0x00010000>;
0502 };
0503 partition@3 {
0504 label = "QSPI.SPL.backup3";
0505 reg = <0x00030000 0x00010000>;
0506 };
0507 partition@4 {
0508 label = "QSPI.u-boot";
0509 reg = <0x00040000 0x00100000>;
0510 };
0511 partition@5 {
0512 label = "QSPI.u-boot-spl-os";
0513 reg = <0x00140000 0x00080000>;
0514 };
0515 partition@6 {
0516 label = "QSPI.u-boot-env";
0517 reg = <0x001c0000 0x00010000>;
0518 };
0519 partition@7 {
0520 label = "QSPI.u-boot-env.backup1";
0521 reg = <0x001d0000 0x0010000>;
0522 };
0523 partition@8 {
0524 label = "QSPI.kernel";
0525 reg = <0x001e0000 0x0800000>;
0526 };
0527 partition@9 {
0528 label = "QSPI.file-system";
0529 reg = <0x009e0000 0x01620000>;
0530 };
0531 };
0532 };
0533
0534 &dss {
0535 status = "okay";
0536 };
0537
0538 &hdmi {
0539 status = "okay";
0540
0541 port {
0542 hdmi_out: endpoint {
0543 remote-endpoint = <&tpd12s015_in>;
0544 };
0545 };
0546 };
0547
0548 &atl {
0549 assigned-clocks = <&abe_dpll_sys_clk_mux>,
0550 <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
0551 <&dpll_abe_ck>,
0552 <&dpll_abe_m2x2_ck>,
0553 <&atl_clkin2_ck>;
0554 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
0555 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
0556
0557 status = "okay";
0558
0559 atl2 {
0560 bws = <DRA7_ATL_WS_MCASP2_FSX>;
0561 aws = <DRA7_ATL_WS_MCASP3_FSX>;
0562 };
0563 };
0564
0565 &mcasp3 {
0566 #sound-dai-cells = <0>;
0567
0568 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
0569 assigned-clock-parents = <&atl_clkin2_ck>;
0570
0571 status = "okay";
0572
0573 op-mode = <0>; /* MCASP_IIS_MODE */
0574 tdm-slots = <2>;
0575 /* 4 serializer */
0576 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0577 1 2 0 0
0578 >;
0579 tx-num-evt = <32>;
0580 rx-num-evt = <32>;
0581 };
0582
0583 &pcie1_rc {
0584 status = "okay";
0585 };
0586
0587 &csi2_0 {
0588 csi2_phy0: endpoint {
0589 remote-endpoint = <&csi2_cam0>;
0590 clock-lanes = <0>;
0591 data-lanes = <1 2>;
0592 };
0593 };
