0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0004 *
0005 * Based on "omap4.dtsi"
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/clock/dra7.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/pinctrl/dra.h>
0012 #include <dt-bindings/clock/dra7.h>
0013
0014 #define MAX_SOURCES 400
0015
0016 / {
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 compatible = "ti,dra7xx";
0021 interrupt-parent = <&crossbar_mpu>;
0022 chosen { };
0023
0024 aliases {
0025 i2c0 = &i2c1;
0026 i2c1 = &i2c2;
0027 i2c2 = &i2c3;
0028 i2c3 = &i2c4;
0029 i2c4 = &i2c5;
0030 serial0 = &uart1;
0031 serial1 = &uart2;
0032 serial2 = &uart3;
0033 serial3 = &uart4;
0034 serial4 = &uart5;
0035 serial5 = &uart6;
0036 serial6 = &uart7;
0037 serial7 = &uart8;
0038 serial8 = &uart9;
0039 serial9 = &uart10;
0040 ethernet0 = &cpsw_port1;
0041 ethernet1 = &cpsw_port2;
0042 d_can0 = &dcan1;
0043 d_can1 = &dcan2;
0044 spi0 = &qspi;
0045 };
0046
0047 timer {
0048 compatible = "arm,armv7-timer";
0049 status = "disabled"; /* See ARM architected timer wrap erratum i940 */
0050 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0051 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0052 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0053 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0054 interrupt-parent = <&gic>;
0055 };
0056
0057 gic: interrupt-controller@48211000 {
0058 compatible = "arm,cortex-a15-gic";
0059 interrupt-controller;
0060 #interrupt-cells = <3>;
0061 reg = <0x0 0x48211000 0x0 0x1000>,
0062 <0x0 0x48212000 0x0 0x2000>,
0063 <0x0 0x48214000 0x0 0x2000>,
0064 <0x0 0x48216000 0x0 0x2000>;
0065 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0066 interrupt-parent = <&gic>;
0067 };
0068
0069 wakeupgen: interrupt-controller@48281000 {
0070 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
0071 interrupt-controller;
0072 #interrupt-cells = <3>;
0073 reg = <0x0 0x48281000 0x0 0x1000>;
0074 interrupt-parent = <&gic>;
0075 };
0076
0077 cpus {
0078 #address-cells = <1>;
0079 #size-cells = <0>;
0080
0081 cpu0: cpu@0 {
0082 device_type = "cpu";
0083 compatible = "arm,cortex-a15";
0084 reg = <0>;
0085
0086 operating-points-v2 = <&cpu0_opp_table>;
0087
0088 clocks = <&dpll_mpu_ck>;
0089 clock-names = "cpu";
0090
0091 clock-latency = <300000>; /* From omap-cpufreq driver */
0092
0093 /* cooling options */
0094 #cooling-cells = <2>; /* min followed by max */
0095
0096 vbb-supply = <&abb_mpu>;
0097 };
0098 };
0099
0100 cpu0_opp_table: opp-table {
0101 compatible = "operating-points-v2-ti-cpu";
0102 syscon = <&scm_wkup>;
0103
0104 opp_nom-1000000000 {
0105 opp-hz = /bits/ 64 <1000000000>;
0106 opp-microvolt = <1060000 850000 1150000>,
0107 <1060000 850000 1150000>;
0108 opp-supported-hw = <0xFF 0x01>;
0109 opp-suspend;
0110 };
0111
0112 opp_od-1176000000 {
0113 opp-hz = /bits/ 64 <1176000000>;
0114 opp-microvolt = <1160000 885000 1160000>,
0115 <1160000 885000 1160000>;
0116
0117 opp-supported-hw = <0xFF 0x02>;
0118 };
0119
0120 opp_high@1500000000 {
0121 opp-hz = /bits/ 64 <1500000000>;
0122 opp-microvolt = <1210000 950000 1250000>,
0123 <1210000 950000 1250000>;
0124 opp-supported-hw = <0xFF 0x04>;
0125 };
0126 };
0127
0128 /*
0129 * XXX: Use a flat representation of the SOC interconnect.
0130 * The real OMAP interconnect network is quite complex.
0131 * Since it will not bring real advantage to represent that in DT for
0132 * the moment, just use a fake OCP bus entry to represent the whole bus
0133 * hierarchy.
0134 */
0135 ocp: ocp {
0136 compatible = "simple-pm-bus";
0137 power-domains = <&prm_core>;
0138 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
0139 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 ranges = <0x0 0x0 0x0 0xc0000000>;
0143 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
0144
0145 l3-noc@44000000 {
0146 compatible = "ti,dra7-l3-noc";
0147 reg = <0x44000000 0x1000>,
0148 <0x45000000 0x1000>;
0149 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0150 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0151 };
0152
0153 l4_cfg: interconnect@4a000000 {
0154 };
0155 l4_wkup: interconnect@4ae00000 {
0156 };
0157 l4_per1: interconnect@48000000 {
0158 };
0159
0160 target-module@48210000 {
0161 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0162 power-domains = <&prm_mpu>;
0163 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
0164 clock-names = "fck";
0165 #address-cells = <1>;
0166 #size-cells = <1>;
0167 ranges = <0 0x48210000 0x1f0000>;
0168
0169 mpu {
0170 compatible = "ti,omap5-mpu";
0171 };
0172 };
0173
0174 l4_per2: interconnect@48400000 {
0175 };
0176 l4_per3: interconnect@48800000 {
0177 };
0178
0179 /*
0180 * Register access seems to have complex dependencies and also
0181 * seems to need an enabled phy. See the TRM chapter for "Table
0182 * 26-678. Main Sequence PCIe Controller Global Initialization"
0183 * and also dra7xx_pcie_probe().
0184 */
0185 axi0: target-module@51000000 {
0186 compatible = "ti,sysc-omap4", "ti,sysc";
0187 power-domains = <&prm_l3init>;
0188 resets = <&prm_l3init 0>;
0189 reset-names = "rstctrl";
0190 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
0191 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
0192 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
0193 clock-names = "fck", "phy-clk", "phy-clk-div";
0194 #size-cells = <1>;
0195 #address-cells = <1>;
0196 ranges = <0x51000000 0x51000000 0x3000>,
0197 <0x20000000 0x20000000 0x10000000>;
0198 dma-ranges;
0199 /**
0200 * To enable PCI endpoint mode, disable the pcie1_rc
0201 * node and enable pcie1_ep mode.
0202 */
0203 pcie1_rc: pcie@51000000 {
0204 reg = <0x51000000 0x2000>,
0205 <0x51002000 0x14c>,
0206 <0x20001000 0x2000>;
0207 reg-names = "rc_dbics", "ti_conf", "config";
0208 interrupts = <0 232 0x4>, <0 233 0x4>;
0209 #address-cells = <3>;
0210 #size-cells = <2>;
0211 device_type = "pci";
0212 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
0213 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
0214 bus-range = <0x00 0xff>;
0215 #interrupt-cells = <1>;
0216 num-lanes = <1>;
0217 linux,pci-domain = <0>;
0218 phys = <&pcie1_phy>;
0219 phy-names = "pcie-phy0";
0220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
0221 interrupt-map-mask = <0 0 0 7>;
0222 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
0223 <0 0 0 2 &pcie1_intc 2>,
0224 <0 0 0 3 &pcie1_intc 3>,
0225 <0 0 0 4 &pcie1_intc 4>;
0226 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
0227 status = "disabled";
0228 pcie1_intc: interrupt-controller {
0229 interrupt-controller;
0230 #address-cells = <0>;
0231 #interrupt-cells = <1>;
0232 };
0233 };
0234
0235 pcie1_ep: pcie_ep@51000000 {
0236 reg = <0x51000000 0x28>,
0237 <0x51002000 0x14c>,
0238 <0x51001000 0x28>,
0239 <0x20001000 0x10000000>;
0240 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
0241 interrupts = <0 232 0x4>;
0242 num-lanes = <1>;
0243 num-ib-windows = <4>;
0244 num-ob-windows = <16>;
0245 phys = <&pcie1_phy>;
0246 phy-names = "pcie-phy0";
0247 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
0248 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
0249 status = "disabled";
0250 };
0251 };
0252
0253 /*
0254 * Register access seems to have complex dependencies and also
0255 * seems to need an enabled phy. See the TRM chapter for "Table
0256 * 26-678. Main Sequence PCIe Controller Global Initialization"
0257 * and also dra7xx_pcie_probe().
0258 */
0259 axi1: target-module@51800000 {
0260 compatible = "ti,sysc-omap4", "ti,sysc";
0261 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
0262 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
0263 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
0264 clock-names = "fck", "phy-clk", "phy-clk-div";
0265 power-domains = <&prm_l3init>;
0266 resets = <&prm_l3init 1>;
0267 reset-names = "rstctrl";
0268 #size-cells = <1>;
0269 #address-cells = <1>;
0270 ranges = <0x51800000 0x51800000 0x3000>,
0271 <0x30000000 0x30000000 0x10000000>;
0272 dma-ranges;
0273 status = "disabled";
0274 pcie2_rc: pcie@51800000 {
0275 reg = <0x51800000 0x2000>,
0276 <0x51802000 0x14c>,
0277 <0x30001000 0x2000>;
0278 reg-names = "rc_dbics", "ti_conf", "config";
0279 interrupts = <0 355 0x4>, <0 356 0x4>;
0280 #address-cells = <3>;
0281 #size-cells = <2>;
0282 device_type = "pci";
0283 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
0284 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
0285 bus-range = <0x00 0xff>;
0286 #interrupt-cells = <1>;
0287 num-lanes = <1>;
0288 linux,pci-domain = <1>;
0289 phys = <&pcie2_phy>;
0290 phy-names = "pcie-phy0";
0291 interrupt-map-mask = <0 0 0 7>;
0292 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
0293 <0 0 0 2 &pcie2_intc 2>,
0294 <0 0 0 3 &pcie2_intc 3>,
0295 <0 0 0 4 &pcie2_intc 4>;
0296 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
0297 pcie2_intc: interrupt-controller {
0298 interrupt-controller;
0299 #address-cells = <0>;
0300 #interrupt-cells = <1>;
0301 };
0302 };
0303 };
0304
0305 ocmcram1: ocmcram@40300000 {
0306 compatible = "mmio-sram";
0307 reg = <0x40300000 0x80000>;
0308 ranges = <0x0 0x40300000 0x80000>;
0309 #address-cells = <1>;
0310 #size-cells = <1>;
0311 /*
0312 * This is a placeholder for an optional reserved
0313 * region for use by secure software. The size
0314 * of this region is not known until runtime so it
0315 * is set as zero to either be updated to reserve
0316 * space or left unchanged to leave all SRAM for use.
0317 * On HS parts that that require the reserved region
0318 * either the bootloader can update the size to
0319 * the required amount or the node can be overridden
0320 * from the board dts file for the secure platform.
0321 */
0322 sram-hs@0 {
0323 compatible = "ti,secure-ram";
0324 reg = <0x0 0x0>;
0325 };
0326 };
0327
0328 /*
0329 * NOTE: ocmcram2 and ocmcram3 are not available on all
0330 * DRA7xx and AM57xx variants. Confirm availability in
0331 * the data manual for the exact part number in use
0332 * before enabling these nodes in the board dts file.
0333 */
0334 ocmcram2: ocmcram@40400000 {
0335 status = "disabled";
0336 compatible = "mmio-sram";
0337 reg = <0x40400000 0x100000>;
0338 ranges = <0x0 0x40400000 0x100000>;
0339 #address-cells = <1>;
0340 #size-cells = <1>;
0341 };
0342
0343 ocmcram3: ocmcram@40500000 {
0344 status = "disabled";
0345 compatible = "mmio-sram";
0346 reg = <0x40500000 0x100000>;
0347 ranges = <0x0 0x40500000 0x100000>;
0348 #address-cells = <1>;
0349 #size-cells = <1>;
0350 };
0351
0352 bandgap: bandgap@4a0021e0 {
0353 reg = <0x4a0021e0 0xc
0354 0x4a00232c 0xc
0355 0x4a002380 0x2c
0356 0x4a0023C0 0x3c
0357 0x4a002564 0x8
0358 0x4a002574 0x50>;
0359 compatible = "ti,dra752-bandgap";
0360 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0361 #thermal-sensor-cells = <1>;
0362 };
0363
0364 dsp1_system: dsp_system@40d00000 {
0365 compatible = "syscon";
0366 reg = <0x40d00000 0x100>;
0367 };
0368
0369 dra7_iodelay_core: padconf@4844a000 {
0370 compatible = "ti,dra7-iodelay";
0371 reg = <0x4844a000 0x0d1c>;
0372 #address-cells = <1>;
0373 #size-cells = <0>;
0374 #pinctrl-cells = <2>;
0375 };
0376
0377 target-module@43300000 {
0378 compatible = "ti,sysc-omap4", "ti,sysc";
0379 reg = <0x43300000 0x4>,
0380 <0x43300010 0x4>;
0381 reg-names = "rev", "sysc";
0382 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0383 <SYSC_IDLE_NO>,
0384 <SYSC_IDLE_SMART>;
0385 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0386 <SYSC_IDLE_NO>,
0387 <SYSC_IDLE_SMART>;
0388 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
0389 clock-names = "fck";
0390 #address-cells = <1>;
0391 #size-cells = <1>;
0392 ranges = <0x0 0x43300000 0x100000>;
0393
0394 edma: dma@0 {
0395 compatible = "ti,edma3-tpcc";
0396 reg = <0 0x100000>;
0397 reg-names = "edma3_cc";
0398 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
0399 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
0400 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
0401 interrupt-names = "edma3_ccint", "edma3_mperr",
0402 "edma3_ccerrint";
0403 dma-requests = <64>;
0404 #dma-cells = <2>;
0405
0406 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
0407
0408 /*
0409 * memcpy is disabled, can be enabled with:
0410 * ti,edma-memcpy-channels = <20 21>;
0411 * for example. Note that these channels need to be
0412 * masked in the xbar as well.
0413 */
0414 };
0415 };
0416
0417 target-module@43400000 {
0418 compatible = "ti,sysc-omap4", "ti,sysc";
0419 reg = <0x43400000 0x4>,
0420 <0x43400010 0x4>;
0421 reg-names = "rev", "sysc";
0422 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0423 <SYSC_IDLE_NO>,
0424 <SYSC_IDLE_SMART>;
0425 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0426 <SYSC_IDLE_NO>,
0427 <SYSC_IDLE_SMART>;
0428 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
0429 clock-names = "fck";
0430 #address-cells = <1>;
0431 #size-cells = <1>;
0432 ranges = <0x0 0x43400000 0x100000>;
0433
0434 edma_tptc0: dma@0 {
0435 compatible = "ti,edma3-tptc";
0436 reg = <0 0x100000>;
0437 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
0438 interrupt-names = "edma3_tcerrint";
0439 };
0440 };
0441
0442 target-module@43500000 {
0443 compatible = "ti,sysc-omap4", "ti,sysc";
0444 reg = <0x43500000 0x4>,
0445 <0x43500010 0x4>;
0446 reg-names = "rev", "sysc";
0447 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0448 <SYSC_IDLE_NO>,
0449 <SYSC_IDLE_SMART>;
0450 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0451 <SYSC_IDLE_NO>,
0452 <SYSC_IDLE_SMART>;
0453 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
0454 clock-names = "fck";
0455 #address-cells = <1>;
0456 #size-cells = <1>;
0457 ranges = <0x0 0x43500000 0x100000>;
0458
0459 edma_tptc1: dma@0 {
0460 compatible = "ti,edma3-tptc";
0461 reg = <0 0x100000>;
0462 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
0463 interrupt-names = "edma3_tcerrint";
0464 };
0465 };
0466
0467 target-module@4e000000 {
0468 compatible = "ti,sysc-omap2", "ti,sysc";
0469 reg = <0x4e000000 0x4>,
0470 <0x4e000010 0x4>;
0471 reg-names = "rev", "sysc";
0472 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0473 <SYSC_IDLE_NO>,
0474 <SYSC_IDLE_SMART>;
0475 ranges = <0x0 0x4e000000 0x2000000>;
0476 #size-cells = <1>;
0477 #address-cells = <1>;
0478
0479 dmm@0 {
0480 compatible = "ti,omap5-dmm";
0481 reg = <0 0x800>;
0482 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0483 };
0484 };
0485
0486 ipu1: ipu@58820000 {
0487 compatible = "ti,dra7-ipu";
0488 reg = <0x58820000 0x10000>;
0489 reg-names = "l2ram";
0490 iommus = <&mmu_ipu1>;
0491 status = "disabled";
0492 resets = <&prm_ipu 0>, <&prm_ipu 1>;
0493 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
0494 firmware-name = "dra7-ipu1-fw.xem4";
0495 };
0496
0497 ipu2: ipu@55020000 {
0498 compatible = "ti,dra7-ipu";
0499 reg = <0x55020000 0x10000>;
0500 reg-names = "l2ram";
0501 iommus = <&mmu_ipu2>;
0502 status = "disabled";
0503 resets = <&prm_core 0>, <&prm_core 1>;
0504 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
0505 firmware-name = "dra7-ipu2-fw.xem4";
0506 };
0507
0508 dsp1: dsp@40800000 {
0509 compatible = "ti,dra7-dsp";
0510 reg = <0x40800000 0x48000>,
0511 <0x40e00000 0x8000>,
0512 <0x40f00000 0x8000>;
0513 reg-names = "l2ram", "l1pram", "l1dram";
0514 ti,bootreg = <&scm_conf 0x55c 10>;
0515 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
0516 status = "disabled";
0517 resets = <&prm_dsp1 0>;
0518 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
0519 firmware-name = "dra7-dsp1-fw.xe66";
0520 };
0521
0522 target-module@40d01000 {
0523 compatible = "ti,sysc-omap2", "ti,sysc";
0524 reg = <0x40d01000 0x4>,
0525 <0x40d01010 0x4>,
0526 <0x40d01014 0x4>;
0527 reg-names = "rev", "sysc", "syss";
0528 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0529 <SYSC_IDLE_NO>,
0530 <SYSC_IDLE_SMART>;
0531 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0532 SYSC_OMAP2_SOFTRESET |
0533 SYSC_OMAP2_AUTOIDLE)>;
0534 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
0535 clock-names = "fck";
0536 resets = <&prm_dsp1 1>;
0537 reset-names = "rstctrl";
0538 ranges = <0x0 0x40d01000 0x1000>;
0539 #size-cells = <1>;
0540 #address-cells = <1>;
0541
0542 mmu0_dsp1: mmu@0 {
0543 compatible = "ti,dra7-dsp-iommu";
0544 reg = <0x0 0x100>;
0545 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0546 #iommu-cells = <0>;
0547 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
0548 };
0549 };
0550
0551 target-module@40d02000 {
0552 compatible = "ti,sysc-omap2", "ti,sysc";
0553 reg = <0x40d02000 0x4>,
0554 <0x40d02010 0x4>,
0555 <0x40d02014 0x4>;
0556 reg-names = "rev", "sysc", "syss";
0557 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0558 <SYSC_IDLE_NO>,
0559 <SYSC_IDLE_SMART>;
0560 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0561 SYSC_OMAP2_SOFTRESET |
0562 SYSC_OMAP2_AUTOIDLE)>;
0563 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
0564 clock-names = "fck";
0565 resets = <&prm_dsp1 1>;
0566 reset-names = "rstctrl";
0567 ranges = <0x0 0x40d02000 0x1000>;
0568 #size-cells = <1>;
0569 #address-cells = <1>;
0570
0571 mmu1_dsp1: mmu@0 {
0572 compatible = "ti,dra7-dsp-iommu";
0573 reg = <0x0 0x100>;
0574 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0575 #iommu-cells = <0>;
0576 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
0577 };
0578 };
0579
0580 target-module@58882000 {
0581 compatible = "ti,sysc-omap2", "ti,sysc";
0582 reg = <0x58882000 0x4>,
0583 <0x58882010 0x4>,
0584 <0x58882014 0x4>;
0585 reg-names = "rev", "sysc", "syss";
0586 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0587 <SYSC_IDLE_NO>,
0588 <SYSC_IDLE_SMART>;
0589 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0590 SYSC_OMAP2_SOFTRESET |
0591 SYSC_OMAP2_AUTOIDLE)>;
0592 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
0593 clock-names = "fck";
0594 resets = <&prm_ipu 2>;
0595 reset-names = "rstctrl";
0596 #address-cells = <1>;
0597 #size-cells = <1>;
0598 ranges = <0x0 0x58882000 0x100>;
0599
0600 mmu_ipu1: mmu@0 {
0601 compatible = "ti,dra7-iommu";
0602 reg = <0x0 0x100>;
0603 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
0604 #iommu-cells = <0>;
0605 ti,iommu-bus-err-back;
0606 };
0607 };
0608
0609 target-module@55082000 {
0610 compatible = "ti,sysc-omap2", "ti,sysc";
0611 reg = <0x55082000 0x4>,
0612 <0x55082010 0x4>,
0613 <0x55082014 0x4>;
0614 reg-names = "rev", "sysc", "syss";
0615 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0616 <SYSC_IDLE_NO>,
0617 <SYSC_IDLE_SMART>;
0618 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0619 SYSC_OMAP2_SOFTRESET |
0620 SYSC_OMAP2_AUTOIDLE)>;
0621 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
0622 clock-names = "fck";
0623 resets = <&prm_core 2>;
0624 reset-names = "rstctrl";
0625 #address-cells = <1>;
0626 #size-cells = <1>;
0627 ranges = <0x0 0x55082000 0x100>;
0628
0629 mmu_ipu2: mmu@0 {
0630 compatible = "ti,dra7-iommu";
0631 reg = <0x0 0x100>;
0632 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
0633 #iommu-cells = <0>;
0634 ti,iommu-bus-err-back;
0635 };
0636 };
0637
0638 abb_mpu: regulator-abb-mpu {
0639 compatible = "ti,abb-v3";
0640 regulator-name = "abb_mpu";
0641 #address-cells = <0>;
0642 #size-cells = <0>;
0643 clocks = <&sys_clkin1>;
0644 ti,settling-time = <50>;
0645 ti,clock-cycles = <16>;
0646
0647 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
0648 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
0649 <0x4ae0c158 0x4>;
0650 reg-names = "setup-address", "control-address",
0651 "int-address", "efuse-address",
0652 "ldo-address";
0653 ti,tranxdone-status-mask = <0x80>;
0654 /* LDOVBBMPU_FBB_MUX_CTRL */
0655 ti,ldovbb-override-mask = <0x400>;
0656 /* LDOVBBMPU_FBB_VSET_OUT */
0657 ti,ldovbb-vset-mask = <0x1F>;
0658
0659 /*
0660 * NOTE: only FBB mode used but actual vset will
0661 * determine final biasing
0662 */
0663 ti,abb_info = <
0664 /*uV ABB efuse rbb_m fbb_m vset_m*/
0665 1060000 0 0x0 0 0x02000000 0x01F00000
0666 1160000 0 0x4 0 0x02000000 0x01F00000
0667 1210000 0 0x8 0 0x02000000 0x01F00000
0668 >;
0669 };
0670
0671 abb_ivahd: regulator-abb-ivahd {
0672 compatible = "ti,abb-v3";
0673 regulator-name = "abb_ivahd";
0674 #address-cells = <0>;
0675 #size-cells = <0>;
0676 clocks = <&sys_clkin1>;
0677 ti,settling-time = <50>;
0678 ti,clock-cycles = <16>;
0679
0680 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
0681 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
0682 <0x4a002470 0x4>;
0683 reg-names = "setup-address", "control-address",
0684 "int-address", "efuse-address",
0685 "ldo-address";
0686 ti,tranxdone-status-mask = <0x40000000>;
0687 /* LDOVBBIVA_FBB_MUX_CTRL */
0688 ti,ldovbb-override-mask = <0x400>;
0689 /* LDOVBBIVA_FBB_VSET_OUT */
0690 ti,ldovbb-vset-mask = <0x1F>;
0691
0692 /*
0693 * NOTE: only FBB mode used but actual vset will
0694 * determine final biasing
0695 */
0696 ti,abb_info = <
0697 /*uV ABB efuse rbb_m fbb_m vset_m*/
0698 1055000 0 0x0 0 0x02000000 0x01F00000
0699 1150000 0 0x4 0 0x02000000 0x01F00000
0700 1250000 0 0x8 0 0x02000000 0x01F00000
0701 >;
0702 };
0703
0704 abb_dspeve: regulator-abb-dspeve {
0705 compatible = "ti,abb-v3";
0706 regulator-name = "abb_dspeve";
0707 #address-cells = <0>;
0708 #size-cells = <0>;
0709 clocks = <&sys_clkin1>;
0710 ti,settling-time = <50>;
0711 ti,clock-cycles = <16>;
0712
0713 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
0714 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
0715 <0x4a00246c 0x4>;
0716 reg-names = "setup-address", "control-address",
0717 "int-address", "efuse-address",
0718 "ldo-address";
0719 ti,tranxdone-status-mask = <0x20000000>;
0720 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
0721 ti,ldovbb-override-mask = <0x400>;
0722 /* LDOVBBDSPEVE_FBB_VSET_OUT */
0723 ti,ldovbb-vset-mask = <0x1F>;
0724
0725 /*
0726 * NOTE: only FBB mode used but actual vset will
0727 * determine final biasing
0728 */
0729 ti,abb_info = <
0730 /*uV ABB efuse rbb_m fbb_m vset_m*/
0731 1055000 0 0x0 0 0x02000000 0x01F00000
0732 1150000 0 0x4 0 0x02000000 0x01F00000
0733 1250000 0 0x8 0 0x02000000 0x01F00000
0734 >;
0735 };
0736
0737 abb_gpu: regulator-abb-gpu {
0738 compatible = "ti,abb-v3";
0739 regulator-name = "abb_gpu";
0740 #address-cells = <0>;
0741 #size-cells = <0>;
0742 clocks = <&sys_clkin1>;
0743 ti,settling-time = <50>;
0744 ti,clock-cycles = <16>;
0745
0746 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
0747 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
0748 <0x4ae0c154 0x4>;
0749 reg-names = "setup-address", "control-address",
0750 "int-address", "efuse-address",
0751 "ldo-address";
0752 ti,tranxdone-status-mask = <0x10000000>;
0753 /* LDOVBBGPU_FBB_MUX_CTRL */
0754 ti,ldovbb-override-mask = <0x400>;
0755 /* LDOVBBGPU_FBB_VSET_OUT */
0756 ti,ldovbb-vset-mask = <0x1F>;
0757
0758 /*
0759 * NOTE: only FBB mode used but actual vset will
0760 * determine final biasing
0761 */
0762 ti,abb_info = <
0763 /*uV ABB efuse rbb_m fbb_m vset_m*/
0764 1090000 0 0x0 0 0x02000000 0x01F00000
0765 1210000 0 0x4 0 0x02000000 0x01F00000
0766 1280000 0 0x8 0 0x02000000 0x01F00000
0767 >;
0768 };
0769
0770 target-module@4b300000 {
0771 compatible = "ti,sysc-omap4", "ti,sysc";
0772 reg = <0x4b300000 0x4>,
0773 <0x4b300010 0x4>;
0774 reg-names = "rev", "sysc";
0775 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0776 <SYSC_IDLE_NO>,
0777 <SYSC_IDLE_SMART>,
0778 <SYSC_IDLE_SMART_WKUP>;
0779 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
0780 clock-names = "fck";
0781 #address-cells = <1>;
0782 #size-cells = <1>;
0783 ranges = <0x0 0x4b300000 0x1000>,
0784 <0x5c000000 0x5c000000 0x4000000>;
0785
0786 qspi: spi@0 {
0787 compatible = "ti,dra7xxx-qspi";
0788 reg = <0 0x100>,
0789 <0x5c000000 0x4000000>;
0790 reg-names = "qspi_base", "qspi_mmap";
0791 syscon-chipselects = <&scm_conf 0x558>;
0792 #address-cells = <1>;
0793 #size-cells = <0>;
0794 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
0795 clock-names = "fck";
0796 num-cs = <4>;
0797 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
0798 status = "disabled";
0799 };
0800 };
0801
0802 /* OCP2SCP1 */
0803 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
0804
0805 target-module@50000000 {
0806 compatible = "ti,sysc-omap2", "ti,sysc";
0807 reg = <0x50000000 4>,
0808 <0x50000010 4>,
0809 <0x50000014 4>;
0810 reg-names = "rev", "sysc", "syss";
0811 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0812 <SYSC_IDLE_NO>,
0813 <SYSC_IDLE_SMART>;
0814 ti,syss-mask = <1>;
0815 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
0816 clock-names = "fck";
0817 #address-cells = <1>;
0818 #size-cells = <1>;
0819 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
0820 <0x00000000 0x00000000 0x40000000>; /* data */
0821
0822 gpmc: gpmc@50000000 {
0823 compatible = "ti,am3352-gpmc";
0824 reg = <0x50000000 0x37c>; /* device IO registers */
0825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0826 dmas = <&edma_xbar 4 0>;
0827 dma-names = "rxtx";
0828 gpmc,num-cs = <8>;
0829 gpmc,num-waitpins = <2>;
0830 #address-cells = <2>;
0831 #size-cells = <1>;
0832 interrupt-controller;
0833 #interrupt-cells = <2>;
0834 gpio-controller;
0835 #gpio-cells = <2>;
0836 status = "disabled";
0837 };
0838 };
0839
0840 target-module@56000000 {
0841 compatible = "ti,sysc-omap4", "ti,sysc";
0842 reg = <0x5600fe00 0x4>,
0843 <0x5600fe10 0x4>;
0844 reg-names = "rev", "sysc";
0845 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0846 <SYSC_IDLE_NO>,
0847 <SYSC_IDLE_SMART>;
0848 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0849 <SYSC_IDLE_NO>,
0850 <SYSC_IDLE_SMART>;
0851 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
0852 clock-names = "fck";
0853 #address-cells = <1>;
0854 #size-cells = <1>;
0855 ranges = <0 0x56000000 0x2000000>;
0856 };
0857
0858 crossbar_mpu: crossbar@4a002a48 {
0859 compatible = "ti,irq-crossbar";
0860 reg = <0x4a002a48 0x130>;
0861 interrupt-controller;
0862 interrupt-parent = <&wakeupgen>;
0863 #interrupt-cells = <3>;
0864 ti,max-irqs = <160>;
0865 ti,max-crossbar-sources = <MAX_SOURCES>;
0866 ti,reg-size = <2>;
0867 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
0868 ti,irqs-skip = <10 133 139 140>;
0869 ti,irqs-safe-map = <0>;
0870 };
0871
0872 target-module@58000000 {
0873 compatible = "ti,sysc-omap2", "ti,sysc";
0874 reg = <0x58000000 4>,
0875 <0x58000014 4>;
0876 reg-names = "rev", "syss";
0877 ti,syss-mask = <1>;
0878 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
0879 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
0880 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
0881 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
0882 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
0883 #address-cells = <1>;
0884 #size-cells = <1>;
0885 ranges = <0 0x58000000 0x800000>;
0886
0887 dss: dss@0 {
0888 compatible = "ti,dra7-dss";
0889 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
0890 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
0891 status = "disabled";
0892 /* CTRL_CORE_DSS_PLL_CONTROL */
0893 syscon-pll-ctrl = <&scm_conf 0x538>;
0894 #address-cells = <1>;
0895 #size-cells = <1>;
0896 ranges = <0 0 0x800000>;
0897
0898 target-module@1000 {
0899 compatible = "ti,sysc-omap2", "ti,sysc";
0900 reg = <0x1000 0x4>,
0901 <0x1010 0x4>,
0902 <0x1014 0x4>;
0903 reg-names = "rev", "sysc", "syss";
0904 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0905 <SYSC_IDLE_NO>,
0906 <SYSC_IDLE_SMART>;
0907 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0908 <SYSC_IDLE_NO>,
0909 <SYSC_IDLE_SMART>;
0910 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0911 SYSC_OMAP2_ENAWAKEUP |
0912 SYSC_OMAP2_SOFTRESET |
0913 SYSC_OMAP2_AUTOIDLE)>;
0914 ti,syss-mask = <1>;
0915 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
0916 clock-names = "fck";
0917 #address-cells = <1>;
0918 #size-cells = <1>;
0919 ranges = <0 0x1000 0x1000>;
0920
0921 dispc@0 {
0922 compatible = "ti,dra7-dispc";
0923 reg = <0 0x1000>;
0924 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0925 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
0926 clock-names = "fck";
0927 /* CTRL_CORE_SMA_SW_1 */
0928 syscon-pol = <&scm_conf 0x534>;
0929 };
0930 };
0931
0932 target-module@40000 {
0933 compatible = "ti,sysc-omap4", "ti,sysc";
0934 reg = <0x40000 0x4>,
0935 <0x40010 0x4>;
0936 reg-names = "rev", "sysc";
0937 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0938 <SYSC_IDLE_NO>,
0939 <SYSC_IDLE_SMART>,
0940 <SYSC_IDLE_SMART_WKUP>;
0941 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
0942 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
0943 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
0944 clock-names = "fck", "dss_clk";
0945 #address-cells = <1>;
0946 #size-cells = <1>;
0947 ranges = <0 0x40000 0x40000>;
0948
0949 hdmi: encoder@0 {
0950 compatible = "ti,dra7-hdmi";
0951 reg = <0 0x200>,
0952 <0x200 0x80>,
0953 <0x300 0x80>,
0954 <0x20000 0x19000>;
0955 reg-names = "wp", "pll", "phy", "core";
0956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0957 status = "disabled";
0958 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
0959 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
0960 clock-names = "fck", "sys_clk";
0961 dmas = <&sdma_xbar 76>;
0962 dma-names = "audio_tx";
0963 };
0964 };
0965 };
0966 };
0967
0968 target-module@59000000 {
0969 compatible = "ti,sysc-omap4", "ti,sysc";
0970 reg = <0x59000020 0x4>;
0971 reg-names = "rev";
0972 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
0973 clock-names = "fck";
0974 #address-cells = <1>;
0975 #size-cells = <1>;
0976 ranges = <0x0 0x59000000 0x1000>;
0977
0978 bb2d: gpu@0 {
0979 compatible = "vivante,gc";
0980 reg = <0x0 0x700>;
0981 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0982 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
0983 clock-names = "core";
0984 };
0985 };
0986
0987 aes1_target: target-module@4b500000 {
0988 compatible = "ti,sysc-omap2", "ti,sysc";
0989 reg = <0x4b500080 0x4>,
0990 <0x4b500084 0x4>,
0991 <0x4b500088 0x4>;
0992 reg-names = "rev", "sysc", "syss";
0993 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0994 SYSC_OMAP2_AUTOIDLE)>;
0995 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0996 <SYSC_IDLE_NO>,
0997 <SYSC_IDLE_SMART>,
0998 <SYSC_IDLE_SMART_WKUP>;
0999 ti,syss-mask = <1>;
1000 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1001 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
1002 clock-names = "fck";
1003 #address-cells = <1>;
1004 #size-cells = <1>;
1005 ranges = <0x0 0x4b500000 0x1000>;
1006
1007 aes1: aes@0 {
1008 compatible = "ti,omap4-aes";
1009 reg = <0 0xa0>;
1010 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1011 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1012 dma-names = "tx", "rx";
1013 clocks = <&l3_iclk_div>;
1014 clock-names = "fck";
1015 };
1016 };
1017
1018 aes2_target: target-module@4b700000 {
1019 compatible = "ti,sysc-omap2", "ti,sysc";
1020 reg = <0x4b700080 0x4>,
1021 <0x4b700084 0x4>,
1022 <0x4b700088 0x4>;
1023 reg-names = "rev", "sysc", "syss";
1024 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1025 SYSC_OMAP2_AUTOIDLE)>;
1026 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1027 <SYSC_IDLE_NO>,
1028 <SYSC_IDLE_SMART>,
1029 <SYSC_IDLE_SMART_WKUP>;
1030 ti,syss-mask = <1>;
1031 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1032 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1033 clock-names = "fck";
1034 #address-cells = <1>;
1035 #size-cells = <1>;
1036 ranges = <0x0 0x4b700000 0x1000>;
1037
1038 aes2: aes@0 {
1039 compatible = "ti,omap4-aes";
1040 reg = <0 0xa0>;
1041 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1042 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1043 dma-names = "tx", "rx";
1044 clocks = <&l3_iclk_div>;
1045 clock-names = "fck";
1046 };
1047 };
1048
1049 sham1_target: target-module@4b101000 {
1050 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1051 reg = <0x4b101100 0x4>,
1052 <0x4b101110 0x4>,
1053 <0x4b101114 0x4>;
1054 reg-names = "rev", "sysc", "syss";
1055 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1056 SYSC_OMAP2_AUTOIDLE)>;
1057 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1058 <SYSC_IDLE_NO>,
1059 <SYSC_IDLE_SMART>;
1060 ti,syss-mask = <1>;
1061 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1062 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1063 clock-names = "fck";
1064 #address-cells = <1>;
1065 #size-cells = <1>;
1066 ranges = <0x0 0x4b101000 0x1000>;
1067
1068 sham1: sham@0 {
1069 compatible = "ti,omap5-sham";
1070 reg = <0 0x300>;
1071 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1072 dmas = <&edma_xbar 119 0>;
1073 dma-names = "rx";
1074 clocks = <&l3_iclk_div>;
1075 clock-names = "fck";
1076 };
1077 };
1078
1079 sham2_target: target-module@42701000 {
1080 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1081 reg = <0x42701100 0x4>,
1082 <0x42701110 0x4>,
1083 <0x42701114 0x4>;
1084 reg-names = "rev", "sysc", "syss";
1085 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1086 SYSC_OMAP2_AUTOIDLE)>;
1087 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1088 <SYSC_IDLE_NO>,
1089 <SYSC_IDLE_SMART>;
1090 ti,syss-mask = <1>;
1091 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1092 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1093 clock-names = "fck";
1094 #address-cells = <1>;
1095 #size-cells = <1>;
1096 ranges = <0x0 0x42701000 0x1000>;
1097
1098 sham2: sham@0 {
1099 compatible = "ti,omap5-sham";
1100 reg = <0 0x300>;
1101 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
1102 dmas = <&edma_xbar 165 0>;
1103 dma-names = "rx";
1104 clocks = <&l3_iclk_div>;
1105 clock-names = "fck";
1106 };
1107 };
1108
1109 iva_hd_target: target-module@5a000000 {
1110 compatible = "ti,sysc-omap4", "ti,sysc";
1111 reg = <0x5a05a400 0x4>,
1112 <0x5a05a410 0x4>;
1113 reg-names = "rev", "sysc";
1114 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1115 <SYSC_IDLE_NO>,
1116 <SYSC_IDLE_SMART>;
1117 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1118 <SYSC_IDLE_NO>,
1119 <SYSC_IDLE_SMART>;
1120 power-domains = <&prm_iva>;
1121 resets = <&prm_iva 2>;
1122 reset-names = "rstctrl";
1123 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1124 clock-names = "fck";
1125 #address-cells = <1>;
1126 #size-cells = <1>;
1127 ranges = <0x5a000000 0x5a000000 0x1000000>,
1128 <0x5b000000 0x5b000000 0x1000000>;
1129
1130 iva {
1131 compatible = "ti,ivahd";
1132 };
1133 };
1134
1135 opp_supply_mpu: opp-supply@4a003b20 {
1136 compatible = "ti,omap5-opp-supply";
1137 reg = <0x4a003b20 0xc>;
1138 ti,efuse-settings = <
1139 /* uV offset */
1140 1060000 0x0
1141 1160000 0x4
1142 1210000 0x8
1143 >;
1144 ti,absolute-max-voltage-uv = <1500000>;
1145 };
1146
1147 };
1148
1149 thermal_zones: thermal-zones {
1150 #include "omap4-cpu-thermal.dtsi"
1151 #include "omap5-gpu-thermal.dtsi"
1152 #include "omap5-core-thermal.dtsi"
1153 #include "dra7-dspeve-thermal.dtsi"
1154 #include "dra7-iva-thermal.dtsi"
1155 };
1156
1157 };
1158
1159 &cpu_thermal {
1160 polling-delay = <500>; /* milliseconds */
1161 coefficients = <0 2000>;
1162 };
1163
1164 &gpu_thermal {
1165 coefficients = <0 2000>;
1166 };
1167
1168 &core_thermal {
1169 coefficients = <0 2000>;
1170 };
1171
1172 &dspeve_thermal {
1173 coefficients = <0 2000>;
1174 };
1175
1176 &iva_thermal {
1177 coefficients = <0 2000>;
1178 };
1179
1180 &cpu_crit {
1181 temperature = <120000>; /* milli Celsius */
1182 };
1183
1184 &core_crit {
1185 temperature = <120000>; /* milli Celsius */
1186 };
1187
1188 &gpu_crit {
1189 temperature = <120000>; /* milli Celsius */
1190 };
1191
1192 &dspeve_crit {
1193 temperature = <120000>; /* milli Celsius */
1194 };
1195
1196 &iva_crit {
1197 temperature = <120000>; /* milli Celsius */
1198 };
1199
1200 #include "dra7-l4.dtsi"
1201 #include "dra7xx-clocks.dtsi"
1202
1203 &prm {
1204 prm_mpu: prm@300 {
1205 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1206 reg = <0x300 0x100>;
1207 #power-domain-cells = <0>;
1208 };
1209
1210 prm_dsp1: prm@400 {
1211 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1212 reg = <0x400 0x100>;
1213 #reset-cells = <1>;
1214 #power-domain-cells = <0>;
1215 };
1216
1217 prm_ipu: prm@500 {
1218 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1219 reg = <0x500 0x100>;
1220 #reset-cells = <1>;
1221 #power-domain-cells = <0>;
1222 };
1223
1224 prm_coreaon: prm@628 {
1225 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1226 reg = <0x628 0xd8>;
1227 #power-domain-cells = <0>;
1228 };
1229
1230 prm_core: prm@700 {
1231 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1232 reg = <0x700 0x100>;
1233 #reset-cells = <1>;
1234 #power-domain-cells = <0>;
1235 };
1236
1237 prm_iva: prm@f00 {
1238 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1239 reg = <0xf00 0x100>;
1240 #reset-cells = <1>;
1241 #power-domain-cells = <0>;
1242 };
1243
1244 prm_cam: prm@1000 {
1245 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1246 reg = <0x1000 0x100>;
1247 #power-domain-cells = <0>;
1248 };
1249
1250 prm_dss: prm@1100 {
1251 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1252 reg = <0x1100 0x100>;
1253 #power-domain-cells = <0>;
1254 };
1255
1256 prm_gpu: prm@1200 {
1257 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1258 reg = <0x1200 0x100>;
1259 #power-domain-cells = <0>;
1260 };
1261
1262 prm_l3init: prm@1300 {
1263 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1264 reg = <0x1300 0x100>;
1265 #reset-cells = <1>;
1266 #power-domain-cells = <0>;
1267 };
1268
1269 prm_l4per: prm@1400 {
1270 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1271 reg = <0x1400 0x100>;
1272 #power-domain-cells = <0>;
1273 };
1274
1275 prm_custefuse: prm@1600 {
1276 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1277 reg = <0x1600 0x100>;
1278 #power-domain-cells = <0>;
1279 };
1280
1281 prm_wkupaon: prm@1724 {
1282 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1283 reg = <0x1724 0x100>;
1284 #power-domain-cells = <0>;
1285 };
1286
1287 prm_dsp2: prm@1b00 {
1288 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1289 reg = <0x1b00 0x40>;
1290 #reset-cells = <1>;
1291 #power-domain-cells = <0>;
1292 };
1293
1294 prm_eve1: prm@1b40 {
1295 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1296 reg = <0x1b40 0x40>;
1297 #power-domain-cells = <0>;
1298 };
1299
1300 prm_eve2: prm@1b80 {
1301 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1302 reg = <0x1b80 0x40>;
1303 #power-domain-cells = <0>;
1304 };
1305
1306 prm_eve3: prm@1bc0 {
1307 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1308 reg = <0x1bc0 0x40>;
1309 #power-domain-cells = <0>;
1310 };
1311
1312 prm_eve4: prm@1c00 {
1313 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1314 reg = <0x1c00 0x60>;
1315 #power-domain-cells = <0>;
1316 };
1317
1318 prm_rtc: prm@1c60 {
1319 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1320 reg = <0x1c60 0x20>;
1321 #power-domain-cells = <0>;
1322 };
1323
1324 prm_vpe: prm@1c80 {
1325 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1326 reg = <0x1c80 0x80>;
1327 #power-domain-cells = <0>;
1328 };
1329 };
1330
1331 /* Preferred always-on timer for clockevent */
1332 &timer1_target {
1333 ti,no-reset-on-init;
1334 ti,no-idle;
1335 timer@0 {
1336 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1337 assigned-clock-parents = <&sys_32k_ck>;
1338 };
1339 };
1340
1341 /* Local timers, see ARM architected timer wrap erratum i940 */
1342 &timer15_target {
1343 ti,no-reset-on-init;
1344 ti,no-idle;
1345 timer@0 {
1346 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1347 assigned-clock-parents = <&timer_sys_clk_div>;
1348 };
1349 };
1350
1351 &timer16_target {
1352 ti,no-reset-on-init;
1353 ti,no-idle;
1354 timer@0 {
1355 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1356 assigned-clock-parents = <&timer_sys_clk_div>;
1357 };
1358 };
