0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005 /dts-v1/;
0006
0007 #include "dra74x.dtsi"
0008 #include "dra7-evm-common.dtsi"
0009 #include "dra74x-mmc-iodelay.dtsi"
0010
0011 / {
0012 model = "TI DRA742";
0013 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
0014
0015 memory@0 {
0016 device_type = "memory";
0017 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
0018 };
0019
0020 evm_12v0: fixedregulator-evm_12v0 {
0021 /* main supply */
0022 compatible = "regulator-fixed";
0023 regulator-name = "evm_12v0";
0024 regulator-min-microvolt = <12000000>;
0025 regulator-max-microvolt = <12000000>;
0026 regulator-always-on;
0027 regulator-boot-on;
0028 };
0029
0030 evm_1v8_sw: fixedregulator-evm_1v8 {
0031 compatible = "regulator-fixed";
0032 regulator-name = "evm_1v8";
0033 vin-supply = <&smps9_reg>;
0034 regulator-min-microvolt = <1800000>;
0035 regulator-max-microvolt = <1800000>;
0036 };
0037
0038 reserved-memory {
0039 #address-cells = <2>;
0040 #size-cells = <2>;
0041 ranges;
0042
0043 ipu2_memory_region: ipu2-memory@95800000 {
0044 compatible = "shared-dma-pool";
0045 reg = <0x0 0x95800000 0x0 0x3800000>;
0046 reusable;
0047 status = "okay";
0048 };
0049
0050 dsp1_memory_region: dsp1-memory@99000000 {
0051 compatible = "shared-dma-pool";
0052 reg = <0x0 0x99000000 0x0 0x4000000>;
0053 reusable;
0054 status = "okay";
0055 };
0056
0057 ipu1_memory_region: ipu1-memory@9d000000 {
0058 compatible = "shared-dma-pool";
0059 reg = <0x0 0x9d000000 0x0 0x2000000>;
0060 reusable;
0061 status = "okay";
0062 };
0063
0064 dsp2_memory_region: dsp2-memory@9f000000 {
0065 compatible = "shared-dma-pool";
0066 reg = <0x0 0x9f000000 0x0 0x800000>;
0067 reusable;
0068 status = "okay";
0069 };
0070 };
0071
0072 evm_3v3_sd: fixedregulator-sd {
0073 compatible = "regulator-fixed";
0074 regulator-name = "evm_3v3_sd";
0075 regulator-min-microvolt = <3300000>;
0076 regulator-max-microvolt = <3300000>;
0077 enable-active-high;
0078 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
0079 };
0080
0081 evm_3v3_sw: fixedregulator-evm_3v3_sw {
0082 compatible = "regulator-fixed";
0083 regulator-name = "evm_3v3_sw";
0084 vin-supply = <&sysen1>;
0085 regulator-min-microvolt = <3300000>;
0086 regulator-max-microvolt = <3300000>;
0087 };
0088
0089 aic_dvdd: fixedregulator-aic_dvdd {
0090 /* TPS77018DBVT */
0091 compatible = "regulator-fixed";
0092 regulator-name = "aic_dvdd";
0093 vin-supply = <&evm_3v3_sw>;
0094 regulator-min-microvolt = <1800000>;
0095 regulator-max-microvolt = <1800000>;
0096 };
0097
0098 vsys_3v3: fixedregulator-vsys3v3 {
0099 /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
0100 compatible = "regulator-fixed";
0101 regulator-name = "vsys_3v3";
0102 regulator-min-microvolt = <3300000>;
0103 regulator-max-microvolt = <3300000>;
0104 vin-supply = <&evm_12v0>;
0105 regulator-always-on;
0106 regulator-boot-on;
0107 };
0108
0109 evm_5v0: fixedregulator-evm_5v0 {
0110 /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */
0111 compatible = "regulator-fixed";
0112 regulator-name = "evm_5v0";
0113 regulator-min-microvolt = <5000000>;
0114 regulator-max-microvolt = <5000000>;
0115 vin-supply = <&evm_12v0>;
0116 regulator-always-on;
0117 regulator-boot-on;
0118 };
0119
0120 evm_3v6: fixedregulator-evm_3v6 {
0121 compatible = "regulator-fixed";
0122 regulator-name = "evm_3v6";
0123 regulator-min-microvolt = <3600000>;
0124 regulator-max-microvolt = <3600000>;
0125 vin-supply = <&evm_5v0>;
0126 regulator-always-on;
0127 regulator-boot-on;
0128 };
0129
0130 vmmcwl_fixed: fixedregulator-mmcwl {
0131 compatible = "regulator-fixed";
0132 regulator-name = "vmmcwl_fixed";
0133 regulator-min-microvolt = <1800000>;
0134 regulator-max-microvolt = <1800000>;
0135 gpio = <&gpio5 8 0>;
0136 startup-delay-us = <70000>;
0137 enable-active-high;
0138 };
0139
0140 vtt_fixed: fixedregulator-vtt {
0141 compatible = "regulator-fixed";
0142 regulator-name = "vtt_fixed";
0143 regulator-min-microvolt = <1350000>;
0144 regulator-max-microvolt = <1350000>;
0145 regulator-always-on;
0146 regulator-boot-on;
0147 enable-active-high;
0148 vin-supply = <&sysen2>;
0149 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
0150 };
0151
0152 };
0153
0154 &dra7_pmx_core {
0155 dcan1_pins_default: dcan1_pins_default {
0156 pinctrl-single,pins = <
0157 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0158 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
0159 >;
0160 };
0161
0162 dcan1_pins_sleep: dcan1_pins_sleep {
0163 pinctrl-single,pins = <
0164 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0165 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
0166 >;
0167 };
0168 };
0169
0170 &i2c1 {
0171 status = "okay";
0172 clock-frequency = <400000>;
0173
0174 tps659038: tps659038@58 {
0175 compatible = "ti,tps659038";
0176 reg = <0x58>;
0177 ti,palmas-override-powerhold;
0178 ti,system-power-controller;
0179
0180 tps659038_pmic {
0181 compatible = "ti,tps659038-pmic";
0182
0183 regulators {
0184 smps123_reg: smps123 {
0185 /* VDD_MPU */
0186 regulator-name = "smps123";
0187 regulator-min-microvolt = < 850000>;
0188 regulator-max-microvolt = <1250000>;
0189 regulator-always-on;
0190 regulator-boot-on;
0191 };
0192
0193 smps45_reg: smps45 {
0194 /* VDD_DSPEVE */
0195 regulator-name = "smps45";
0196 regulator-min-microvolt = < 850000>;
0197 regulator-max-microvolt = <1250000>;
0198 regulator-always-on;
0199 regulator-boot-on;
0200 };
0201
0202 smps6_reg: smps6 {
0203 /* VDD_GPU - over VDD_SMPS6 */
0204 regulator-name = "smps6";
0205 regulator-min-microvolt = <850000>;
0206 regulator-max-microvolt = <1250000>;
0207 regulator-always-on;
0208 regulator-boot-on;
0209 };
0210
0211 smps7_reg: smps7 {
0212 /* CORE_VDD */
0213 regulator-name = "smps7";
0214 regulator-min-microvolt = <850000>;
0215 regulator-max-microvolt = <1150000>;
0216 regulator-always-on;
0217 regulator-boot-on;
0218 };
0219
0220 smps8_reg: smps8 {
0221 /* VDD_IVAHD */
0222 regulator-name = "smps8";
0223 regulator-min-microvolt = < 850000>;
0224 regulator-max-microvolt = <1250000>;
0225 regulator-always-on;
0226 regulator-boot-on;
0227 };
0228
0229 smps9_reg: smps9 {
0230 /* VDDS1V8 */
0231 regulator-name = "smps9";
0232 regulator-min-microvolt = <1800000>;
0233 regulator-max-microvolt = <1800000>;
0234 regulator-always-on;
0235 regulator-boot-on;
0236 };
0237
0238 ldo1_reg: ldo1 {
0239 /* LDO1_OUT --> SDIO */
0240 regulator-name = "ldo1";
0241 regulator-min-microvolt = <1800000>;
0242 regulator-max-microvolt = <3300000>;
0243 regulator-always-on;
0244 regulator-boot-on;
0245 };
0246
0247 ldo2_reg: ldo2 {
0248 /* VDD_RTCIO */
0249 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
0250 regulator-name = "ldo2";
0251 regulator-min-microvolt = <3300000>;
0252 regulator-max-microvolt = <3300000>;
0253 regulator-always-on;
0254 regulator-boot-on;
0255 };
0256
0257 ldo3_reg: ldo3 {
0258 /* VDDA_1V8_PHY */
0259 regulator-name = "ldo3";
0260 regulator-min-microvolt = <1800000>;
0261 regulator-max-microvolt = <1800000>;
0262 regulator-always-on;
0263 regulator-boot-on;
0264 };
0265
0266 ldo9_reg: ldo9 {
0267 /* VDD_RTC */
0268 regulator-name = "ldo9";
0269 regulator-min-microvolt = <1050000>;
0270 regulator-max-microvolt = <1050000>;
0271 regulator-always-on;
0272 regulator-boot-on;
0273 regulator-allow-bypass;
0274 };
0275
0276 ldoln_reg: ldoln {
0277 /* VDDA_1V8_PLL */
0278 regulator-name = "ldoln";
0279 regulator-min-microvolt = <1800000>;
0280 regulator-max-microvolt = <1800000>;
0281 regulator-always-on;
0282 regulator-boot-on;
0283 };
0284
0285 ldousb_reg: ldousb {
0286 /* VDDA_3V_USB: VDDA_USBHS33 */
0287 regulator-name = "ldousb";
0288 regulator-min-microvolt = <3300000>;
0289 regulator-max-microvolt = <3300000>;
0290 regulator-boot-on;
0291 };
0292
0293 /* REGEN1 is unused */
0294
0295 regen2: regen2 {
0296 /* Needed for PMIC internal resources */
0297 regulator-name = "regen2";
0298 regulator-boot-on;
0299 regulator-always-on;
0300 };
0301
0302 /* REGEN3 is unused */
0303
0304 sysen1: sysen1 {
0305 /* PMIC_REGEN_3V3 */
0306 regulator-name = "sysen1";
0307 regulator-boot-on;
0308 regulator-always-on;
0309 };
0310
0311 sysen2: sysen2 {
0312 /* PMIC_REGEN_DDR */
0313 regulator-name = "sysen2";
0314 regulator-boot-on;
0315 regulator-always-on;
0316 };
0317 };
0318 };
0319 };
0320
0321 pcf_lcd: gpio@20 {
0322 compatible = "nxp,pcf8575";
0323 reg = <0x20>;
0324 gpio-controller;
0325 #gpio-cells = <2>;
0326 interrupt-parent = <&gpio6>;
0327 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
0328 interrupt-controller;
0329 #interrupt-cells = <2>;
0330 };
0331
0332 pcf_gpio_21: gpio@21 {
0333 compatible = "nxp,pcf8575";
0334 reg = <0x21>;
0335 lines-initial-states = <0x1408>;
0336 gpio-controller;
0337 #gpio-cells = <2>;
0338 interrupt-parent = <&gpio6>;
0339 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
0340 interrupt-controller;
0341 #interrupt-cells = <2>;
0342 };
0343
0344 tlv320aic3106: tlv320aic3106@19 {
0345 #sound-dai-cells = <0>;
0346 compatible = "ti,tlv320aic3106";
0347 reg = <0x19>;
0348 adc-settle-ms = <40>;
0349 ai3x-micbias-vg = <1>; /* 2.0V */
0350 status = "okay";
0351
0352 /* Regulators */
0353 AVDD-supply = <&evm_3v3_sw>;
0354 IOVDD-supply = <&evm_3v3_sw>;
0355 DRVDD-supply = <&evm_3v3_sw>;
0356 DVDD-supply = <&aic_dvdd>;
0357 };
0358 };
0359
0360 &i2c2 {
0361 status = "okay";
0362 clock-frequency = <400000>;
0363
0364 pcf_hdmi: gpio@26 {
0365 compatible = "nxp,pcf8575";
0366 reg = <0x26>;
0367 gpio-controller;
0368 #gpio-cells = <2>;
0369 hdmi-audio-hog {
0370 /* vin6_sel_s0: high: VIN6, low: audio */
0371 gpio-hog;
0372 gpios = <1 GPIO_ACTIVE_HIGH>;
0373 output-low;
0374 line-name = "vin6_sel_s0";
0375 };
0376 };
0377 };
0378
0379 &mmc1 {
0380 status = "okay";
0381 vmmc-supply = <&evm_3v3_sd>;
0382 vqmmc-supply = <&ldo1_reg>;
0383 bus-width = <4>;
0384 /*
0385 * SDCD signal is not being used here - using the fact that GPIO mode
0386 * is always hardwired.
0387 */
0388 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
0389 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
0390 pinctrl-0 = <&mmc1_pins_default>;
0391 pinctrl-1 = <&mmc1_pins_hs>;
0392 pinctrl-2 = <&mmc1_pins_sdr12>;
0393 pinctrl-3 = <&mmc1_pins_sdr25>;
0394 pinctrl-4 = <&mmc1_pins_sdr50>;
0395 pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
0396 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
0397 pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
0398 pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
0399 };
0400
0401 &mmc2 {
0402 status = "okay";
0403 vmmc-supply = <&evm_1v8_sw>;
0404 vqmmc-supply = <&evm_1v8_sw>;
0405 bus-width = <8>;
0406 non-removable;
0407 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
0408 pinctrl-0 = <&mmc2_pins_default>;
0409 pinctrl-1 = <&mmc2_pins_hs>;
0410 pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
0411 pinctrl-3 = <&mmc2_pins_ddr_rev20>;
0412 pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
0413 pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
0414 };
0415
0416 &mmc4 {
0417 status = "okay";
0418 vmmc-supply = <&evm_3v6>;
0419 vqmmc-supply = <&vmmcwl_fixed>;
0420 pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
0421 pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
0422 pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
0423 pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
0424 pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
0425 pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
0426 pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
0427 pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
0428 pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
0429 };
0430
0431 &cpu0 {
0432 vdd-supply = <&smps123_reg>;
0433 };
0434
0435 &elm {
0436 status = "okay";
0437 };
0438
0439 &gpmc {
0440 /*
0441 * For the existing IOdelay configuration via U-Boot we don't
0442 * support NAND on dra7-evm. Keep it disabled. Enabling it
0443 * requires a different configuration by U-Boot.
0444 */
0445 status = "disabled";
0446 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
0447 nand@0,0 {
0448 compatible = "ti,omap2-nand";
0449 reg = <0 0 4>; /* device IO registers */
0450 interrupt-parent = <&gpmc>;
0451 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0452 <1 IRQ_TYPE_NONE>; /* termcount */
0453 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
0454 ti,nand-xfer-type = "prefetch-dma";
0455 ti,nand-ecc-opt = "bch8";
0456 ti,elm-id = <&elm>;
0457 nand-bus-width = <16>;
0458 gpmc,device-width = <2>;
0459 gpmc,sync-clk-ps = <0>;
0460 gpmc,cs-on-ns = <0>;
0461 gpmc,cs-rd-off-ns = <80>;
0462 gpmc,cs-wr-off-ns = <80>;
0463 gpmc,adv-on-ns = <0>;
0464 gpmc,adv-rd-off-ns = <60>;
0465 gpmc,adv-wr-off-ns = <60>;
0466 gpmc,we-on-ns = <10>;
0467 gpmc,we-off-ns = <50>;
0468 gpmc,oe-on-ns = <4>;
0469 gpmc,oe-off-ns = <40>;
0470 gpmc,access-ns = <40>;
0471 gpmc,wr-access-ns = <80>;
0472 gpmc,rd-cycle-ns = <80>;
0473 gpmc,wr-cycle-ns = <80>;
0474 gpmc,bus-turnaround-ns = <0>;
0475 gpmc,cycle2cycle-delay-ns = <0>;
0476 gpmc,clk-activation-ns = <0>;
0477 gpmc,wr-data-mux-bus-ns = <0>;
0478 /* MTD partition table */
0479 /* All SPL-* partitions are sized to minimal length
0480 * which can be independently programmable. For
0481 * NAND flash this is equal to size of erase-block */
0482 #address-cells = <1>;
0483 #size-cells = <1>;
0484 partition@0 {
0485 label = "NAND.SPL";
0486 reg = <0x00000000 0x000020000>;
0487 };
0488 partition@1 {
0489 label = "NAND.SPL.backup1";
0490 reg = <0x00020000 0x00020000>;
0491 };
0492 partition@2 {
0493 label = "NAND.SPL.backup2";
0494 reg = <0x00040000 0x00020000>;
0495 };
0496 partition@3 {
0497 label = "NAND.SPL.backup3";
0498 reg = <0x00060000 0x00020000>;
0499 };
0500 partition@4 {
0501 label = "NAND.u-boot-spl-os";
0502 reg = <0x00080000 0x00040000>;
0503 };
0504 partition@5 {
0505 label = "NAND.u-boot";
0506 reg = <0x000c0000 0x00100000>;
0507 };
0508 partition@6 {
0509 label = "NAND.u-boot-env";
0510 reg = <0x001c0000 0x00020000>;
0511 };
0512 partition@7 {
0513 label = "NAND.u-boot-env.backup1";
0514 reg = <0x001e0000 0x00020000>;
0515 };
0516 partition@8 {
0517 label = "NAND.kernel";
0518 reg = <0x00200000 0x00800000>;
0519 };
0520 partition@9 {
0521 label = "NAND.file-system";
0522 reg = <0x00a00000 0x0f600000>;
0523 };
0524 };
0525 };
0526
0527 &usb2_phy1 {
0528 phy-supply = <&ldousb_reg>;
0529 };
0530
0531 &usb2_phy2 {
0532 phy-supply = <&ldousb_reg>;
0533 };
0534
0535 &gpio7_target {
0536 ti,no-reset-on-init;
0537 ti,no-idle-on-init;
0538 };
0539
0540 &mac_sw {
0541 status = "okay";
0542 };
0543
0544 &cpsw_port1 {
0545 phy-handle = <ðphy0>;
0546 phy-mode = "rgmii";
0547 ti,dual-emac-pvid = <1>;
0548 };
0549
0550 &cpsw_port2 {
0551 phy-handle = <ðphy1>;
0552 phy-mode = "rgmii";
0553 ti,dual-emac-pvid = <2>;
0554 };
0555
0556 &davinci_mdio_sw {
0557 ethphy0: ethernet-phy@2 {
0558 reg = <2>;
0559 };
0560
0561 ethphy1: ethernet-phy@3 {
0562 reg = <3>;
0563 };
0564 };
0565
0566 &dcan1 {
0567 status = "okay";
0568 pinctrl-names = "default", "sleep", "active";
0569 pinctrl-0 = <&dcan1_pins_sleep>;
0570 pinctrl-1 = <&dcan1_pins_sleep>;
0571 pinctrl-2 = <&dcan1_pins_default>;
0572 };
0573
0574 &ipu2 {
0575 status = "okay";
0576 memory-region = <&ipu2_memory_region>;
0577 };
0578
0579 &ipu1 {
0580 status = "okay";
0581 memory-region = <&ipu1_memory_region>;
0582 };
0583
0584 &dsp1 {
0585 status = "okay";
0586 memory-region = <&dsp1_memory_region>;
0587 };
0588
0589 &dsp2 {
0590 status = "okay";
0591 memory-region = <&dsp2_memory_region>;
0592 };
