OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/gpio/gpio.h>
0003 #include <dt-bindings/interrupt-controller/irq.h>
0004
0005 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0006
0007 / {
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 compatible = "marvell,dove";
0011 model = "Marvell Armada 88AP510 SoC";
0012 interrupt-parent = <&intc>;
0013
0014 aliases {
0015 gpio0 = &gpio0;
0016 gpio1 = &gpio1;
0017 gpio2 = &gpio2;
0018 };
0019
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 cpu0: cpu@0 {
0025 compatible = "marvell,pj4a", "marvell,sheeva-v7";
0026 device_type = "cpu";
0027 next-level-cache = <&l2>;
0028 reg = <0>;
0029 };
0030 };
0031
0032 l2: l2-cache {
0033 compatible = "marvell,tauros2-cache";
0034 marvell,tauros2-cache-features = <0>;
0035 };
0036
0037 gpu-subsystem {
0038 compatible = "marvell,dove-gpu-subsystem";
0039 cores = <&gpu>;
0040 status = "disabled";
0041 };
0042
0043 i2c-mux {
0044 compatible = "i2c-mux-pinctrl";
0045 #address-cells = <1>;
0046 #size-cells = <0>;
0047
0048 i2c-parent = <&i2c>;
0049
0050 pinctrl-names = "i2c0", "i2c1", "i2c2";
0051 pinctrl-0 = <&pmx_i2cmux_0>;
0052 pinctrl-1 = <&pmx_i2cmux_1>;
0053 pinctrl-2 = <&pmx_i2cmux_2>;
0054
0055 i2c0: i2c@0 {
0056 reg = <0>;
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059 status = "okay";
0060 };
0061
0062 i2c1: i2c@1 {
0063 reg = <1>;
0064 #address-cells = <1>;
0065 #size-cells = <0>;
0066 /* Requires pmx_i2c1 on i2c controller node */
0067 status = "disabled";
0068 };
0069
0070 i2c2: i2c@2 {
0071 reg = <2>;
0072 #address-cells = <1>;
0073 #size-cells = <0>;
0074 /* Requires pmx_i2c2 on i2c controller node */
0075 status = "disabled";
0076 };
0077 };
0078
0079 mbus {
0080 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
0081 #address-cells = <2>;
0082 #size-cells = <1>;
0083 controller = <&mbusc>;
0084 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
0085 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
0086
0087 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
0088 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
0089 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
0090 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
0091 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
0092
0093 pcie: pcie {
0094 compatible = "marvell,dove-pcie";
0095 status = "disabled";
0096 device_type = "pci";
0097 #address-cells = <3>;
0098 #size-cells = <2>;
0099
0100 msi-parent = <&intc>;
0101 bus-range = <0x00 0xff>;
0102
0103 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
0104 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
0105 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
0106 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
0107 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
0108 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
0109
0110 pcie0: pcie@1 {
0111 device_type = "pci";
0112 status = "disabled";
0113 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0114 reg = <0x0800 0 0 0 0>;
0115 clocks = <&gate_clk 4>;
0116 marvell,pcie-port = <0>;
0117
0118 #address-cells = <3>;
0119 #size-cells = <2>;
0120 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0121 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0122 bus-range = <0x00 0xff>;
0123
0124 #interrupt-cells = <1>;
0125 interrupt-map-mask = <0 0 0 0>;
0126 interrupt-map = <0 0 0 0 &intc 16>;
0127 };
0128
0129 pcie1: pcie@2 {
0130 device_type = "pci";
0131 status = "disabled";
0132 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
0133 reg = <0x1000 0 0 0 0>;
0134 clocks = <&gate_clk 5>;
0135 marvell,pcie-port = <1>;
0136
0137 #address-cells = <3>;
0138 #size-cells = <2>;
0139 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0140 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0141 bus-range = <0x00 0xff>;
0142
0143 #interrupt-cells = <1>;
0144 interrupt-map-mask = <0 0 0 0>;
0145 interrupt-map = <0 0 0 0 &intc 18>;
0146 };
0147 };
0148
0149 internal-regs {
0150 compatible = "simple-bus";
0151 #address-cells = <1>;
0152 #size-cells = <1>;
0153 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
0154 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
0155 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
0156 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
0157
0158 spi0: spi@10600 {
0159 compatible = "marvell,orion-spi";
0160 #address-cells = <1>;
0161 #size-cells = <0>;
0162 cell-index = <0>;
0163 interrupts = <6>;
0164 reg = <0x10600 0x28>;
0165 clocks = <&core_clk 0>;
0166 pinctrl-0 = <&pmx_spi0>;
0167 pinctrl-names = "default";
0168 status = "disabled";
0169 };
0170
0171 i2c: i2c@11000 {
0172 compatible = "marvell,mv64xxx-i2c";
0173 reg = <0x11000 0x20>;
0174 #address-cells = <1>;
0175 #size-cells = <0>;
0176 interrupts = <11>;
0177 clock-frequency = <400000>;
0178 clocks = <&core_clk 0>;
0179 status = "okay";
0180 };
0181
0182 uart0: serial@12000 {
0183 compatible = "ns16550a";
0184 reg = <0x12000 0x100>;
0185 reg-shift = <2>;
0186 interrupts = <7>;
0187 clocks = <&core_clk 0>;
0188 status = "disabled";
0189 };
0190
0191 uart1: serial@12100 {
0192 compatible = "ns16550a";
0193 reg = <0x12100 0x100>;
0194 reg-shift = <2>;
0195 interrupts = <8>;
0196 clocks = <&core_clk 0>;
0197 pinctrl-0 = <&pmx_uart1>;
0198 pinctrl-names = "default";
0199 status = "disabled";
0200 };
0201
0202 uart2: serial@12200 {
0203 compatible = "ns16550a";
0204 reg = <0x12200 0x100>;
0205 reg-shift = <2>;
0206 interrupts = <9>;
0207 clocks = <&core_clk 0>;
0208 status = "disabled";
0209 };
0210
0211 uart3: serial@12300 {
0212 compatible = "ns16550a";
0213 reg = <0x12300 0x100>;
0214 reg-shift = <2>;
0215 interrupts = <10>;
0216 clocks = <&core_clk 0>;
0217 status = "disabled";
0218 };
0219
0220 spi1: spi@14600 {
0221 compatible = "marvell,orion-spi";
0222 #address-cells = <1>;
0223 #size-cells = <0>;
0224 cell-index = <1>;
0225 interrupts = <5>;
0226 reg = <0x14600 0x28>;
0227 clocks = <&core_clk 0>;
0228 status = "disabled";
0229 };
0230
0231 mbusc: mbus-ctrl@20000 {
0232 compatible = "marvell,mbus-controller";
0233 reg = <0x20000 0x80>, <0x800100 0x8>;
0234 };
0235
0236 sysc: system-ctrl@20000 {
0237 compatible = "marvell,orion-system-controller";
0238 reg = <0x20000 0x110>;
0239 };
0240
0241 bridge_intc: bridge-interrupt-ctrl@20110 {
0242 compatible = "marvell,orion-bridge-intc";
0243 interrupt-controller;
0244 #interrupt-cells = <1>;
0245 reg = <0x20110 0x8>;
0246 interrupts = <0>;
0247 marvell,#interrupts = <5>;
0248 };
0249
0250 intc: interrupt-controller@20200 {
0251 compatible = "marvell,orion-intc";
0252 interrupt-controller;
0253 #interrupt-cells = <1>;
0254 reg = <0x20200 0x10>, <0x20210 0x10>;
0255 };
0256
0257 timer: timer@20300 {
0258 compatible = "marvell,orion-timer";
0259 reg = <0x20300 0x20>;
0260 interrupt-parent = <&bridge_intc>;
0261 interrupts = <1>, <2>;
0262 clocks = <&core_clk 0>;
0263 };
0264
0265 watchdog@20300 {
0266 compatible = "marvell,orion-wdt";
0267 reg = <0x20300 0x28>, <0x20108 0x4>;
0268 interrupt-parent = <&bridge_intc>;
0269 interrupts = <3>;
0270 clocks = <&core_clk 0>;
0271 };
0272
0273 crypto: crypto-engine@30000 {
0274 compatible = "marvell,dove-crypto";
0275 reg = <0x30000 0x10000>;
0276 reg-names = "regs";
0277 interrupts = <31>;
0278 clocks = <&gate_clk 15>;
0279 marvell,crypto-srams = <&crypto_sram>;
0280 marvell,crypto-sram-size = <0x800>;
0281 status = "okay";
0282 };
0283
0284 ehci0: usb-host@50000 {
0285 compatible = "marvell,orion-ehci";
0286 reg = <0x50000 0x1000>;
0287 interrupts = <24>;
0288 clocks = <&gate_clk 0>;
0289 status = "okay";
0290 };
0291
0292 ehci1: usb-host@51000 {
0293 compatible = "marvell,orion-ehci";
0294 reg = <0x51000 0x1000>;
0295 interrupts = <25>;
0296 clocks = <&gate_clk 1>;
0297 status = "okay";
0298 };
0299
0300 xor0: dma-engine@60800 {
0301 compatible = "marvell,orion-xor";
0302 reg = <0x60800 0x100
0303 0x60a00 0x100>;
0304 clocks = <&gate_clk 23>;
0305 status = "okay";
0306
0307 channel0 {
0308 interrupts = <39>;
0309 dmacap,memcpy;
0310 dmacap,xor;
0311 };
0312
0313 channel1 {
0314 interrupts = <40>;
0315 dmacap,memcpy;
0316 dmacap,xor;
0317 };
0318 };
0319
0320 xor1: dma-engine@60900 {
0321 compatible = "marvell,orion-xor";
0322 reg = <0x60900 0x100
0323 0x60b00 0x100>;
0324 clocks = <&gate_clk 24>;
0325 status = "okay";
0326
0327 channel0 {
0328 interrupts = <42>;
0329 dmacap,memcpy;
0330 dmacap,xor;
0331 };
0332
0333 channel1 {
0334 interrupts = <43>;
0335 dmacap,memcpy;
0336 dmacap,xor;
0337 };
0338 };
0339
0340 sdio1: sdio-host@90000 {
0341 compatible = "marvell,dove-sdhci";
0342 reg = <0x90000 0x100>;
0343 interrupts = <36>, <38>;
0344 clocks = <&gate_clk 9>;
0345 pinctrl-0 = <&pmx_sdio1>;
0346 pinctrl-names = "default";
0347 status = "disabled";
0348 };
0349
0350 eth: ethernet-ctrl@72000 {
0351 compatible = "marvell,orion-eth";
0352 #address-cells = <1>;
0353 #size-cells = <0>;
0354 reg = <0x72000 0x4000>;
0355 clocks = <&gate_clk 2>;
0356 marvell,tx-checksum-limit = <1600>;
0357 status = "disabled";
0358
0359 ethernet-port@0 {
0360 compatible = "marvell,orion-eth-port";
0361 reg = <0>;
0362 interrupts = <29>;
0363 /* overwrite MAC address in bootloader */
0364 local-mac-address = [00 00 00 00 00 00];
0365 phy-handle = <ðphy>;
0366 };
0367 };
0368
0369 mdio: mdio-bus@72004 {
0370 compatible = "marvell,orion-mdio";
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373 reg = <0x72004 0x84>;
0374 interrupts = <30>;
0375 clocks = <&gate_clk 2>;
0376 status = "disabled";
0377
0378 ethphy: ethernet-phy {
0379 /* set phy address in board file */
0380 };
0381 };
0382
0383 sdio0: sdio-host@92000 {
0384 compatible = "marvell,dove-sdhci";
0385 reg = <0x92000 0x100>;
0386 interrupts = <35>, <37>;
0387 clocks = <&gate_clk 8>;
0388 pinctrl-0 = <&pmx_sdio0>;
0389 pinctrl-names = "default";
0390 status = "disabled";
0391 };
0392
0393 sata0: sata-host@a0000 {
0394 compatible = "marvell,orion-sata";
0395 reg = <0xa0000 0x2400>;
0396 interrupts = <62>;
0397 clocks = <&gate_clk 3>;
0398 phys = <&sata_phy0>;
0399 phy-names = "port0";
0400 nr-ports = <1>;
0401 status = "disabled";
0402 };
0403
0404 sata_phy0: sata-phy@a2000 {
0405 compatible = "marvell,mvebu-sata-phy";
0406 reg = <0xa2000 0x0334>;
0407 clocks = <&gate_clk 3>;
0408 clock-names = "sata";
0409 #phy-cells = <0>;
0410 status = "ok";
0411 };
0412
0413 audio0: audio-controller@b0000 {
0414 compatible = "marvell,dove-audio";
0415 reg = <0xb0000 0x2210>;
0416 interrupts = <19>, <20>;
0417 clocks = <&gate_clk 12>;
0418 clock-names = "internal";
0419 status = "disabled";
0420 };
0421
0422 audio1: audio-controller@b4000 {
0423 compatible = "marvell,dove-audio";
0424 reg = <0xb4000 0x2210>;
0425 interrupts = <21>, <22>;
0426 clocks = <&gate_clk 13>;
0427 clock-names = "internal";
0428 status = "disabled";
0429 };
0430
0431 pmu: power-management@d0000 {
0432 compatible = "marvell,dove-pmu", "simple-bus";
0433 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
0434 ranges = <0x00000000 0x000d0000 0x8000
0435 0x00008000 0x000d8000 0x8000>;
0436 interrupts = <33>;
0437 interrupt-controller;
0438 #address-cells = <1>;
0439 #size-cells = <1>;
0440 #interrupt-cells = <1>;
0441 #reset-cells = <1>;
0442
0443 domains {
0444 vpu_domain: vpu-domain {
0445 #power-domain-cells = <0>;
0446 marvell,pmu_pwr_mask = <0x00000008>;
0447 marvell,pmu_iso_mask = <0x00000001>;
0448 resets = <&pmu 16>;
0449 };
0450
0451 gpu_domain: gpu-domain {
0452 #power-domain-cells = <0>;
0453 marvell,pmu_pwr_mask = <0x00000004>;
0454 marvell,pmu_iso_mask = <0x00000002>;
0455 resets = <&pmu 18>;
0456 };
0457 };
0458
0459 thermal: thermal-diode@1c {
0460 compatible = "marvell,dove-thermal";
0461 reg = <0x001c 0x0c>, <0x005c 0x08>;
0462 };
0463
0464 gate_clk: clock-gating-ctrl@38 {
0465 compatible = "marvell,dove-gating-clock";
0466 reg = <0x0038 0x4>;
0467 clocks = <&core_clk 0>;
0468 #clock-cells = <1>;
0469 };
0470
0471 divider_clk: core-clock@64 {
0472 compatible = "marvell,dove-divider-clock";
0473 reg = <0x0064 0x8>;
0474 #clock-cells = <1>;
0475 };
0476
0477 pinctrl: pin-ctrl@200 {
0478 compatible = "marvell,dove-pinctrl";
0479 reg = <0x0200 0x14>,
0480 <0x0440 0x04>;
0481 clocks = <&gate_clk 22>;
0482
0483 pmx_gpio_0: pmx-gpio-0 {
0484 marvell,pins = "mpp0";
0485 marvell,function = "gpio";
0486 };
0487
0488 pmx_gpio_1: pmx-gpio-1 {
0489 marvell,pins = "mpp1";
0490 marvell,function = "gpio";
0491 };
0492
0493 pmx_gpio_2: pmx-gpio-2 {
0494 marvell,pins = "mpp2";
0495 marvell,function = "gpio";
0496 };
0497
0498 pmx_gpio_3: pmx-gpio-3 {
0499 marvell,pins = "mpp3";
0500 marvell,function = "gpio";
0501 };
0502
0503 pmx_gpio_4: pmx-gpio-4 {
0504 marvell,pins = "mpp4";
0505 marvell,function = "gpio";
0506 };
0507
0508 pmx_gpio_5: pmx-gpio-5 {
0509 marvell,pins = "mpp5";
0510 marvell,function = "gpio";
0511 };
0512
0513 pmx_gpio_6: pmx-gpio-6 {
0514 marvell,pins = "mpp6";
0515 marvell,function = "gpio";
0516 };
0517
0518 pmx_gpio_7: pmx-gpio-7 {
0519 marvell,pins = "mpp7";
0520 marvell,function = "gpio";
0521 };
0522
0523 pmx_gpio_8: pmx-gpio-8 {
0524 marvell,pins = "mpp8";
0525 marvell,function = "gpio";
0526 };
0527
0528 pmx_gpio_9: pmx-gpio-9 {
0529 marvell,pins = "mpp9";
0530 marvell,function = "gpio";
0531 };
0532
0533 pmx_pcie1_clkreq: pmx-pcie1-clkreq {
0534 marvell,pins = "mpp9";
0535 marvell,function = "pex1";
0536 };
0537
0538 pmx_gpio_10: pmx-gpio-10 {
0539 marvell,pins = "mpp10";
0540 marvell,function = "gpio";
0541 };
0542
0543 pmx_gpio_11: pmx-gpio-11 {
0544 marvell,pins = "mpp11";
0545 marvell,function = "gpio";
0546 };
0547
0548 pmx_pcie0_clkreq: pmx-pcie0-clkreq {
0549 marvell,pins = "mpp11";
0550 marvell,function = "pex0";
0551 };
0552
0553 pmx_gpio_12: pmx-gpio-12 {
0554 marvell,pins = "mpp12";
0555 marvell,function = "gpio";
0556 };
0557
0558 pmx_gpio_13: pmx-gpio-13 {
0559 marvell,pins = "mpp13";
0560 marvell,function = "gpio";
0561 };
0562
0563 pmx_audio1_extclk: pmx-audio1-extclk {
0564 marvell,pins = "mpp13";
0565 marvell,function = "audio1";
0566 };
0567
0568 pmx_gpio_14: pmx-gpio-14 {
0569 marvell,pins = "mpp14";
0570 marvell,function = "gpio";
0571 };
0572
0573 pmx_gpio_15: pmx-gpio-15 {
0574 marvell,pins = "mpp15";
0575 marvell,function = "gpio";
0576 };
0577
0578 pmx_gpio_16: pmx-gpio-16 {
0579 marvell,pins = "mpp16";
0580 marvell,function = "gpio";
0581 };
0582
0583 pmx_gpio_17: pmx-gpio-17 {
0584 marvell,pins = "mpp17";
0585 marvell,function = "gpio";
0586 };
0587
0588 pmx_gpio_18: pmx-gpio-18 {
0589 marvell,pins = "mpp18";
0590 marvell,function = "gpio";
0591 };
0592
0593 pmx_gpio_19: pmx-gpio-19 {
0594 marvell,pins = "mpp19";
0595 marvell,function = "gpio";
0596 };
0597
0598 pmx_gpio_20: pmx-gpio-20 {
0599 marvell,pins = "mpp20";
0600 marvell,function = "gpio";
0601 };
0602
0603 pmx_gpio_21: pmx-gpio-21 {
0604 marvell,pins = "mpp21";
0605 marvell,function = "gpio";
0606 };
0607
0608 pmx_camera: pmx-camera {
0609 marvell,pins = "mpp_camera";
0610 marvell,function = "camera";
0611 };
0612
0613 pmx_camera_gpio: pmx-camera-gpio {
0614 marvell,pins = "mpp_camera";
0615 marvell,function = "gpio";
0616 };
0617
0618 pmx_sdio0: pmx-sdio0 {
0619 marvell,pins = "mpp_sdio0";
0620 marvell,function = "sdio0";
0621 };
0622
0623 pmx_sdio0_gpio: pmx-sdio0-gpio {
0624 marvell,pins = "mpp_sdio0";
0625 marvell,function = "gpio";
0626 };
0627
0628 pmx_sdio1: pmx-sdio1 {
0629 marvell,pins = "mpp_sdio1";
0630 marvell,function = "sdio1";
0631 };
0632
0633 pmx_sdio1_gpio: pmx-sdio1-gpio {
0634 marvell,pins = "mpp_sdio1";
0635 marvell,function = "gpio";
0636 };
0637
0638 pmx_audio1_gpio: pmx-audio1-gpio {
0639 marvell,pins = "mpp_audio1";
0640 marvell,function = "gpio";
0641 };
0642
0643 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
0644 marvell,pins = "mpp_audio1";
0645 marvell,function = "i2s1/spdifo";
0646 };
0647
0648 pmx_spi0: pmx-spi0 {
0649 marvell,pins = "mpp_spi0";
0650 marvell,function = "spi0";
0651 };
0652
0653 pmx_spi0_gpio: pmx-spi0-gpio {
0654 marvell,pins = "mpp_spi0";
0655 marvell,function = "gpio";
0656 };
0657
0658 pmx_spi1_4_7: pmx-spi1-4-7 {
0659 marvell,pins = "mpp4", "mpp5",
0660 "mpp6", "mpp7";
0661 marvell,function = "spi1";
0662 };
0663
0664 pmx_spi1_20_23: pmx-spi1-20-23 {
0665 marvell,pins = "mpp20", "mpp21",
0666 "mpp22", "mpp23";
0667 marvell,function = "spi1";
0668 };
0669
0670 pmx_uart1: pmx-uart1 {
0671 marvell,pins = "mpp_uart1";
0672 marvell,function = "uart1";
0673 };
0674
0675 pmx_uart1_gpio: pmx-uart1-gpio {
0676 marvell,pins = "mpp_uart1";
0677 marvell,function = "gpio";
0678 };
0679
0680 pmx_nand: pmx-nand {
0681 marvell,pins = "mpp_nand";
0682 marvell,function = "nand";
0683 };
0684
0685 pmx_nand_gpo: pmx-nand-gpo {
0686 marvell,pins = "mpp_nand";
0687 marvell,function = "gpo";
0688 };
0689
0690 pmx_i2c1: pmx-i2c1 {
0691 marvell,pins = "mpp17", "mpp19";
0692 marvell,function = "twsi";
0693 };
0694
0695 pmx_i2c2: pmx-i2c2 {
0696 marvell,pins = "mpp_audio1";
0697 marvell,function = "twsi";
0698 };
0699
0700 pmx_ssp_i2c2: pmx-ssp-i2c2 {
0701 marvell,pins = "mpp_audio1";
0702 marvell,function = "ssp/twsi";
0703 };
0704
0705 pmx_i2cmux_0: pmx-i2cmux-0 {
0706 marvell,pins = "twsi";
0707 marvell,function = "twsi-opt1";
0708 };
0709
0710 pmx_i2cmux_1: pmx-i2cmux-1 {
0711 marvell,pins = "twsi";
0712 marvell,function = "twsi-opt2";
0713 };
0714
0715 pmx_i2cmux_2: pmx-i2cmux-2 {
0716 marvell,pins = "twsi";
0717 marvell,function = "twsi-opt3";
0718 };
0719 };
0720
0721 core_clk: core-clocks@214 {
0722 compatible = "marvell,dove-core-clock";
0723 reg = <0x0214 0x4>;
0724 #clock-cells = <1>;
0725 };
0726
0727 gpio0: gpio-ctrl@400 {
0728 compatible = "marvell,orion-gpio";
0729 #gpio-cells = <2>;
0730 gpio-controller;
0731 reg = <0x0400 0x20>;
0732 ngpios = <32>;
0733 interrupt-controller;
0734 #interrupt-cells = <2>;
0735 interrupt-parent = <&intc>;
0736 interrupts = <12>, <13>, <14>, <60>;
0737 };
0738
0739 gpio1: gpio-ctrl@420 {
0740 compatible = "marvell,orion-gpio";
0741 #gpio-cells = <2>;
0742 gpio-controller;
0743 reg = <0x0420 0x20>;
0744 ngpios = <32>;
0745 interrupt-controller;
0746 #interrupt-cells = <2>;
0747 interrupt-parent = <&intc>;
0748 interrupts = <61>;
0749 };
0750
0751 rtc: real-time-clock@8500 {
0752 compatible = "marvell,orion-rtc";
0753 reg = <0x8500 0x20>;
0754 interrupts = <5>;
0755 };
0756 };
0757
0758 gconf: global-config@e802c {
0759 compatible = "marvell,dove-global-config",
0760 "syscon";
0761 reg = <0xe802c 0x14>;
0762 };
0763
0764 gpio2: gpio-ctrl@e8400 {
0765 compatible = "marvell,orion-gpio";
0766 #gpio-cells = <2>;
0767 gpio-controller;
0768 reg = <0xe8400 0x0c>;
0769 ngpios = <8>;
0770 };
0771
0772 lcd1: lcd-controller@810000 {
0773 compatible = "marvell,dove-lcd";
0774 reg = <0x810000 0x1000>;
0775 interrupts = <46>;
0776 status = "disabled";
0777 };
0778
0779 lcd0: lcd-controller@820000 {
0780 compatible = "marvell,dove-lcd";
0781 reg = <0x820000 0x1000>;
0782 interrupts = <47>;
0783 status = "disabled";
0784 };
0785
0786 crypto_sram: sram@ffffe000 {
0787 compatible = "mmio-sram";
0788 reg = <0xffffe000 0x800>;
0789 clocks = <&gate_clk 15>;
0790 #address-cells = <1>;
0791 #size-cells = <1>;
0792 };
0793
0794 gpu: gpu@840000 {
0795 clocks = <÷r_clk 1>;
0796 clock-names = "core";
0797 compatible = "vivante,gc";
0798 interrupts = <48>;
0799 power-domains = <&gpu_domain>;
0800 reg = <0x840000 0x4000>;
0801 status = "disabled";
0802 };
0803 };
0804 };
0805 };
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