0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 &scrm {
0004 main_fapll: main_fapll {
0005 #clock-cells = <1>;
0006 compatible = "ti,dm816-fapll-clock";
0007 reg = <0x400 0x40>;
0008 clocks = <&sys_clkin_ck &sys_clkin_ck>;
0009 clock-indices = <1>, <2>, <3>, <4>, <5>,
0010 <6>, <7>;
0011 clock-output-names = "main_pll_clk1",
0012 "main_pll_clk2",
0013 "main_pll_clk3",
0014 "main_pll_clk4",
0015 "main_pll_clk5",
0016 "main_pll_clk6",
0017 "main_pll_clk7";
0018 };
0019
0020 ddr_fapll: ddr_fapll {
0021 #clock-cells = <1>;
0022 compatible = "ti,dm816-fapll-clock";
0023 reg = <0x440 0x30>;
0024 clocks = <&sys_clkin_ck &sys_clkin_ck>;
0025 clock-indices = <1>, <2>, <3>, <4>;
0026 clock-output-names = "ddr_pll_clk1",
0027 "ddr_pll_clk2",
0028 "ddr_pll_clk3",
0029 "ddr_pll_clk4";
0030 };
0031
0032 video_fapll: video_fapll {
0033 #clock-cells = <1>;
0034 compatible = "ti,dm816-fapll-clock";
0035 reg = <0x470 0x30>;
0036 clocks = <&sys_clkin_ck &sys_clkin_ck>;
0037 clock-indices = <1>, <2>, <3>;
0038 clock-output-names = "video_pll_clk1",
0039 "video_pll_clk2",
0040 "video_pll_clk3";
0041 };
0042
0043 audio_fapll: audio_fapll {
0044 #clock-cells = <1>;
0045 compatible = "ti,dm816-fapll-clock";
0046 reg = <0x4a0 0x30>;
0047 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
0048 clock-indices = <1>, <2>, <3>, <4>, <5>;
0049 clock-output-names = "audio_pll_clk1",
0050 "audio_pll_clk2",
0051 "audio_pll_clk3",
0052 "audio_pll_clk4",
0053 "audio_pll_clk5";
0054 };
0055 };
0056
0057 &scrm_clocks {
0058 secure_32k_ck: secure_32k_ck {
0059 #clock-cells = <0>;
0060 compatible = "fixed-clock";
0061 clock-frequency = <32768>;
0062 };
0063
0064 sys_32k_ck: sys_32k_ck {
0065 #clock-cells = <0>;
0066 compatible = "fixed-clock";
0067 clock-frequency = <32768>;
0068 };
0069
0070 tclkin_ck: tclkin_ck {
0071 #clock-cells = <0>;
0072 compatible = "fixed-clock";
0073 clock-frequency = <32768>;
0074 };
0075
0076 sys_clkin_ck: sys_clkin_ck {
0077 #clock-cells = <0>;
0078 compatible = "fixed-clock";
0079 clock-frequency = <27000000>;
0080 };
0081 };
0082
0083 /* 0x48180000 */
0084 &prcm_clocks {
0085 clkout_pre_ck: clkout_pre_ck@100 {
0086 #clock-cells = <0>;
0087 compatible = "ti,mux-clock";
0088 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
0089 &audio_fapll 1>;
0090 reg = <0x100>;
0091 };
0092
0093 clkout_div_ck: clkout_div_ck@100 {
0094 #clock-cells = <0>;
0095 compatible = "ti,divider-clock";
0096 clocks = <&clkout_pre_ck>;
0097 ti,bit-shift = <3>;
0098 ti,max-div = <8>;
0099 reg = <0x100>;
0100 };
0101
0102 clkout_ck: clkout_ck@100 {
0103 #clock-cells = <0>;
0104 compatible = "ti,gate-clock";
0105 clocks = <&clkout_div_ck>;
0106 ti,bit-shift = <7>;
0107 reg = <0x100>;
0108 };
0109
0110 /* CM_DPLL clocks p1795 */
0111 sysclk1_ck: sysclk1_ck@300 {
0112 #clock-cells = <0>;
0113 compatible = "ti,divider-clock";
0114 clocks = <&main_fapll 1>;
0115 ti,max-div = <7>;
0116 reg = <0x0300>;
0117 };
0118
0119 sysclk2_ck: sysclk2_ck@304 {
0120 #clock-cells = <0>;
0121 compatible = "ti,divider-clock";
0122 clocks = <&main_fapll 2>;
0123 ti,max-div = <7>;
0124 reg = <0x0304>;
0125 };
0126
0127 sysclk3_ck: sysclk3_ck@308 {
0128 #clock-cells = <0>;
0129 compatible = "ti,divider-clock";
0130 clocks = <&main_fapll 3>;
0131 ti,max-div = <7>;
0132 reg = <0x0308>;
0133 };
0134
0135 sysclk4_ck: sysclk4_ck@30c {
0136 #clock-cells = <0>;
0137 compatible = "ti,divider-clock";
0138 clocks = <&main_fapll 4>;
0139 ti,max-div = <1>;
0140 reg = <0x030c>;
0141 };
0142
0143 sysclk5_ck: sysclk5_ck@310 {
0144 #clock-cells = <0>;
0145 compatible = "ti,divider-clock";
0146 clocks = <&sysclk4_ck>;
0147 ti,max-div = <1>;
0148 reg = <0x0310>;
0149 };
0150
0151 sysclk6_ck: sysclk6_ck@314 {
0152 #clock-cells = <0>;
0153 compatible = "ti,divider-clock";
0154 clocks = <&main_fapll 4>;
0155 ti,dividers = <2>, <4>;
0156 reg = <0x0314>;
0157 };
0158
0159 sysclk10_ck: sysclk10_ck@324 {
0160 #clock-cells = <0>;
0161 compatible = "ti,divider-clock";
0162 clocks = <&ddr_fapll 2>;
0163 ti,max-div = <7>;
0164 reg = <0x0324>;
0165 };
0166
0167 sysclk24_ck: sysclk24_ck@3b4 {
0168 #clock-cells = <0>;
0169 compatible = "ti,divider-clock";
0170 clocks = <&main_fapll 5>;
0171 ti,max-div = <7>;
0172 reg = <0x03b4>;
0173 };
0174
0175 mpu_ck: mpu_ck@15dc {
0176 #clock-cells = <0>;
0177 compatible = "ti,gate-clock";
0178 clocks = <&sysclk2_ck>;
0179 ti,bit-shift = <1>;
0180 reg = <0x15dc>;
0181 };
0182
0183 audio_pll_a_ck: audio_pll_a_ck@35c {
0184 #clock-cells = <0>;
0185 compatible = "ti,divider-clock";
0186 clocks = <&audio_fapll 1>;
0187 ti,max-div = <7>;
0188 reg = <0x035c>;
0189 };
0190
0191 sysclk18_ck: sysclk18_ck@378 {
0192 #clock-cells = <0>;
0193 compatible = "ti,mux-clock";
0194 clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
0195 reg = <0x0378>;
0196 };
0197
0198 timer1_fck: timer1_fck@390 {
0199 #clock-cells = <0>;
0200 compatible = "ti,mux-clock";
0201 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0202 reg = <0x0390>;
0203 };
0204
0205 timer2_fck: timer2_fck@394 {
0206 #clock-cells = <0>;
0207 compatible = "ti,mux-clock";
0208 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0209 reg = <0x0394>;
0210 };
0211
0212 timer3_fck: timer3_fck@398 {
0213 #clock-cells = <0>;
0214 compatible = "ti,mux-clock";
0215 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0216 reg = <0x0398>;
0217 };
0218
0219 timer4_fck: timer4_fck@39c {
0220 #clock-cells = <0>;
0221 compatible = "ti,mux-clock";
0222 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0223 reg = <0x039c>;
0224 };
0225
0226 timer5_fck: timer5_fck@3a0 {
0227 #clock-cells = <0>;
0228 compatible = "ti,mux-clock";
0229 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0230 reg = <0x03a0>;
0231 };
0232
0233 timer6_fck: timer6_fck@3a4 {
0234 #clock-cells = <0>;
0235 compatible = "ti,mux-clock";
0236 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0237 reg = <0x03a4>;
0238 };
0239
0240 timer7_fck: timer7_fck@3a8 {
0241 #clock-cells = <0>;
0242 compatible = "ti,mux-clock";
0243 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
0244 reg = <0x03a8>;
0245 };
0246 };
0247
0248 &prcm {
0249 default_cm: default_cm@500 {
0250 compatible = "ti,omap4-cm";
0251 reg = <0x500 0x100>;
0252 #address-cells = <1>;
0253 #size-cells = <1>;
0254 ranges = <0 0x500 0x100>;
0255
0256 default_clkctrl: clk@0 {
0257 compatible = "ti,clkctrl";
0258 reg = <0x0 0x5c>;
0259 #clock-cells = <2>;
0260 };
0261 };
0262
0263 alwon_cm: alwon_cm@1400 {
0264 compatible = "ti,omap4-cm";
0265 reg = <0x1400 0x300>;
0266 #address-cells = <1>;
0267 #size-cells = <1>;
0268 ranges = <0 0x1400 0x300>;
0269
0270 alwon_clkctrl: clk@0 {
0271 compatible = "ti,clkctrl";
0272 reg = <0x0 0x208>;
0273 #clock-cells = <2>;
0274 };
0275 };
0276 };
