0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 &pllss {
0004 /*
0005 * See TRM "2.6.10 Connected outputso DPLLS" and
0006 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
0007 * connected except for hdmi and usb.
0008 */
0009 adpll_mpu_ck: adpll@40 {
0010 #clock-cells = <1>;
0011 compatible = "ti,dm814-adpll-s-clock";
0012 reg = <0x40 0x40>;
0013 clocks = <&devosc_ck &devosc_ck &devosc_ck>;
0014 clock-names = "clkinp", "clkinpulow", "clkinphif";
0015 clock-output-names = "481c5040.adpll.dcoclkldo",
0016 "481c5040.adpll.clkout",
0017 "481c5040.adpll.clkoutx2",
0018 "481c5040.adpll.clkouthif";
0019 };
0020
0021 adpll_dsp_ck: adpll@80 {
0022 #clock-cells = <1>;
0023 compatible = "ti,dm814-adpll-lj-clock";
0024 reg = <0x80 0x30>;
0025 clocks = <&devosc_ck &devosc_ck>;
0026 clock-names = "clkinp", "clkinpulow";
0027 clock-output-names = "481c5080.adpll.dcoclkldo",
0028 "481c5080.adpll.clkout",
0029 "481c5080.adpll.clkoutldo";
0030 };
0031
0032 adpll_sgx_ck: adpll@b0 {
0033 #clock-cells = <1>;
0034 compatible = "ti,dm814-adpll-lj-clock";
0035 reg = <0xb0 0x30>;
0036 clocks = <&devosc_ck &devosc_ck>;
0037 clock-names = "clkinp", "clkinpulow";
0038 clock-output-names = "481c50b0.adpll.dcoclkldo",
0039 "481c50b0.adpll.clkout",
0040 "481c50b0.adpll.clkoutldo";
0041 };
0042
0043 adpll_hdvic_ck: adpll@e0 {
0044 #clock-cells = <1>;
0045 compatible = "ti,dm814-adpll-lj-clock";
0046 reg = <0xe0 0x30>;
0047 clocks = <&devosc_ck &devosc_ck>;
0048 clock-names = "clkinp", "clkinpulow";
0049 clock-output-names = "481c50e0.adpll.dcoclkldo",
0050 "481c50e0.adpll.clkout",
0051 "481c50e0.adpll.clkoutldo";
0052 };
0053
0054 adpll_l3_ck: adpll@110 {
0055 #clock-cells = <1>;
0056 compatible = "ti,dm814-adpll-lj-clock";
0057 reg = <0x110 0x30>;
0058 clocks = <&devosc_ck &devosc_ck>;
0059 clock-names = "clkinp", "clkinpulow";
0060 clock-output-names = "481c5110.adpll.dcoclkldo",
0061 "481c5110.adpll.clkout",
0062 "481c5110.adpll.clkoutldo";
0063 };
0064
0065 adpll_isp_ck: adpll@140 {
0066 #clock-cells = <1>;
0067 compatible = "ti,dm814-adpll-lj-clock";
0068 reg = <0x140 0x30>;
0069 clocks = <&devosc_ck &devosc_ck>;
0070 clock-names = "clkinp", "clkinpulow";
0071 clock-output-names = "481c5140.adpll.dcoclkldo",
0072 "481c5140.adpll.clkout",
0073 "481c5140.adpll.clkoutldo";
0074 };
0075
0076 adpll_dss_ck: adpll@170 {
0077 #clock-cells = <1>;
0078 compatible = "ti,dm814-adpll-lj-clock";
0079 reg = <0x170 0x30>;
0080 clocks = <&devosc_ck &devosc_ck>;
0081 clock-names = "clkinp", "clkinpulow";
0082 clock-output-names = "481c5170.adpll.dcoclkldo",
0083 "481c5170.adpll.clkout",
0084 "481c5170.adpll.clkoutldo";
0085 };
0086
0087 adpll_video0_ck: adpll@1a0 {
0088 #clock-cells = <1>;
0089 compatible = "ti,dm814-adpll-lj-clock";
0090 reg = <0x1a0 0x30>;
0091 clocks = <&devosc_ck &devosc_ck>;
0092 clock-names = "clkinp", "clkinpulow";
0093 clock-output-names = "481c51a0.adpll.dcoclkldo",
0094 "481c51a0.adpll.clkout",
0095 "481c51a0.adpll.clkoutldo";
0096 };
0097
0098 adpll_video1_ck: adpll@1d0 {
0099 #clock-cells = <1>;
0100 compatible = "ti,dm814-adpll-lj-clock";
0101 reg = <0x1d0 0x30>;
0102 clocks = <&devosc_ck &devosc_ck>;
0103 clock-names = "clkinp", "clkinpulow";
0104 clock-output-names = "481c51d0.adpll.dcoclkldo",
0105 "481c51d0.adpll.clkout",
0106 "481c51d0.adpll.clkoutldo";
0107 };
0108
0109 adpll_hdmi_ck: adpll@200 {
0110 #clock-cells = <1>;
0111 compatible = "ti,dm814-adpll-lj-clock";
0112 reg = <0x200 0x30>;
0113 clocks = <&devosc_ck &devosc_ck>;
0114 clock-names = "clkinp", "clkinpulow";
0115 clock-output-names = "481c5200.adpll.dcoclkldo",
0116 "481c5200.adpll.clkout",
0117 "481c5200.adpll.clkoutldo";
0118 };
0119
0120 adpll_audio_ck: adpll@230 {
0121 #clock-cells = <1>;
0122 compatible = "ti,dm814-adpll-lj-clock";
0123 reg = <0x230 0x30>;
0124 clocks = <&devosc_ck &devosc_ck>;
0125 clock-names = "clkinp", "clkinpulow";
0126 clock-output-names = "481c5230.adpll.dcoclkldo",
0127 "481c5230.adpll.clkout",
0128 "481c5230.adpll.clkoutldo";
0129 };
0130
0131 adpll_usb_ck: adpll@260 {
0132 #clock-cells = <1>;
0133 compatible = "ti,dm814-adpll-lj-clock";
0134 reg = <0x260 0x30>;
0135 clocks = <&devosc_ck &devosc_ck>;
0136 clock-names = "clkinp", "clkinpulow";
0137 clock-output-names = "481c5260.adpll.dcoclkldo",
0138 "481c5260.adpll.clkout",
0139 "481c5260.adpll.clkoutldo";
0140 };
0141
0142 adpll_ddr_ck: adpll@290 {
0143 #clock-cells = <1>;
0144 compatible = "ti,dm814-adpll-lj-clock";
0145 reg = <0x290 0x30>;
0146 clocks = <&devosc_ck &devosc_ck>;
0147 clock-names = "clkinp", "clkinpulow";
0148 clock-output-names = "481c5290.adpll.dcoclkldo",
0149 "481c5290.adpll.clkout",
0150 "481c5290.adpll.clkoutldo";
0151 };
0152 };
0153
0154 &pllss_clocks {
0155 timer1_fck: timer1_fck@2e0 {
0156 #clock-cells = <0>;
0157 compatible = "ti,mux-clock";
0158 clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
0159 &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
0160 ti,bit-shift = <3>;
0161 reg = <0x2e0>;
0162 };
0163
0164 timer2_fck: timer2_fck@2e0 {
0165 #clock-cells = <0>;
0166 compatible = "ti,mux-clock";
0167 clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
0168 &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
0169 ti,bit-shift = <6>;
0170 reg = <0x2e0>;
0171 };
0172
0173 /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
0174 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
0175 #clock-cells = <0>;
0176 compatible = "ti,mux-clock";
0177 clocks = <&adpll_video0_ck 1
0178 &adpll_video1_ck 1
0179 &adpll_audio_ck 1>;
0180 ti,bit-shift = <1>;
0181 reg = <0x2e8>;
0182 };
0183
0184 /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
0185 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
0186 #clock-cells = <0>;
0187 compatible = "fixed-clock";
0188 clock-frequency = <125000000>;
0189 };
0190
0191 sysclk18_ck: sysclk18_ck@2f0 {
0192 #clock-cells = <0>;
0193 compatible = "ti,mux-clock";
0194 clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
0195 ti,bit-shift = <0>;
0196 reg = <0x02f0>;
0197 };
0198 };
0199
0200 &scm_clocks {
0201 devosc_ck: devosc_ck@40 {
0202 #clock-cells = <0>;
0203 compatible = "ti,mux-clock";
0204 clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
0205 ti,bit-shift = <21>;
0206 reg = <0x0040>;
0207 };
0208
0209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
0210 auxosc_ck: auxosc_ck {
0211 #clock-cells = <0>;
0212 compatible = "fixed-clock";
0213 clock-frequency = <22572900>;
0214 };
0215
0216 /* Optional 32768Hz crystal or clock on RTCOSC pins */
0217 rtcosc_ck: rtcosc_ck {
0218 #clock-cells = <0>;
0219 compatible = "fixed-clock";
0220 clock-frequency = <32768>;
0221 };
0222
0223 /* Optional external clock on TCLKIN pin, set rate in baord dts file */
0224 tclkin_ck: tclkin_ck {
0225 #clock-cells = <0>;
0226 compatible = "fixed-clock";
0227 clock-frequency = <0>;
0228 };
0229
0230 virt_20000000_ck: virt_20000000_ck {
0231 #clock-cells = <0>;
0232 compatible = "fixed-clock";
0233 clock-frequency = <20000000>;
0234 };
0235
0236 virt_19200000_ck: virt_19200000_ck {
0237 #clock-cells = <0>;
0238 compatible = "fixed-clock";
0239 clock-frequency = <19200000>;
0240 };
0241
0242 mpu_ck: mpu_ck {
0243 #clock-cells = <0>;
0244 compatible = "fixed-clock";
0245 clock-frequency = <1000000000>;
0246 };
0247 };
0248
0249 &prcm_clocks {
0250 osc_src_ck: osc_src_ck {
0251 #clock-cells = <0>;
0252 compatible = "fixed-factor-clock";
0253 clocks = <&devosc_ck>;
0254 clock-mult = <1>;
0255 clock-div = <1>;
0256 };
0257
0258 mpu_clksrc_ck: mpu_clksrc_ck@40 {
0259 #clock-cells = <0>;
0260 compatible = "ti,mux-clock";
0261 clocks = <&devosc_ck>, <&rtcdivider_ck>;
0262 ti,bit-shift = <0>;
0263 reg = <0x0040>;
0264 };
0265
0266 /* Fixed divider clock 0.0016384 * devosc */
0267 rtcdivider_ck: rtcdivider_ck {
0268 #clock-cells = <0>;
0269 compatible = "fixed-factor-clock";
0270 clocks = <&devosc_ck>;
0271 clock-mult = <128>;
0272 clock-div = <78125>;
0273 };
0274
0275 /* L4_HS 220 MHz*/
0276 sysclk4_ck: sysclk4_ck {
0277 #clock-cells = <0>;
0278 compatible = "ti,fixed-factor-clock";
0279 clocks = <&adpll_l3_ck 1>;
0280 ti,clock-mult = <1>;
0281 ti,clock-div = <1>;
0282 };
0283
0284 /* L4_FWCFG */
0285 sysclk5_ck: sysclk5_ck {
0286 #clock-cells = <0>;
0287 compatible = "ti,fixed-factor-clock";
0288 clocks = <&adpll_l3_ck 1>;
0289 ti,clock-mult = <1>;
0290 ti,clock-div = <2>;
0291 };
0292
0293 /* L4_LS 110 MHz */
0294 sysclk6_ck: sysclk6_ck {
0295 #clock-cells = <0>;
0296 compatible = "ti,fixed-factor-clock";
0297 clocks = <&adpll_l3_ck 1>;
0298 ti,clock-mult = <1>;
0299 ti,clock-div = <2>;
0300 };
0301
0302 sysclk8_ck: sysclk8_ck {
0303 #clock-cells = <0>;
0304 compatible = "ti,fixed-factor-clock";
0305 clocks = <&adpll_usb_ck 1>;
0306 ti,clock-mult = <1>;
0307 ti,clock-div = <1>;
0308 };
0309
0310 sysclk10_ck: sysclk10_ck {
0311 compatible = "ti,divider-clock";
0312 reg = <0x324>;
0313 ti,max-div = <7>;
0314 #clock-cells = <0>;
0315 clocks = <&adpll_usb_ck 1>;
0316 };
0317
0318 aud_clkin0_ck: aud_clkin0_ck {
0319 #clock-cells = <0>;
0320 compatible = "fixed-clock";
0321 clock-frequency = <20000000>;
0322 };
0323
0324 aud_clkin1_ck: aud_clkin1_ck {
0325 #clock-cells = <0>;
0326 compatible = "fixed-clock";
0327 clock-frequency = <20000000>;
0328 };
0329
0330 aud_clkin2_ck: aud_clkin2_ck {
0331 #clock-cells = <0>;
0332 compatible = "fixed-clock";
0333 clock-frequency = <20000000>;
0334 };
0335 };
0336
0337 &prcm {
0338 default_cm: default_cm@500 {
0339 compatible = "ti,omap4-cm";
0340 reg = <0x500 0x100>;
0341 #address-cells = <1>;
0342 #size-cells = <1>;
0343 ranges = <0 0x500 0x100>;
0344
0345 default_clkctrl: clk@0 {
0346 compatible = "ti,clkctrl";
0347 reg = <0x0 0x5c>;
0348 #clock-cells = <2>;
0349 };
0350 };
0351
0352 alwon_cm: alwon_cm@1400 {
0353 compatible = "ti,omap4-cm";
0354 reg = <0x1400 0x300>;
0355 #address-cells = <1>;
0356 #size-cells = <1>;
0357 ranges = <0 0x1400 0x300>;
0358
0359 alwon_clkctrl: clk@0 {
0360 compatible = "ti,clkctrl";
0361 reg = <0x0 0x228>;
0362 #clock-cells = <2>;
0363 };
0364 };
0365
0366 alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
0367 compatible = "ti,omap4-cm";
0368 reg = <0x15d4 0x4>;
0369 #address-cells = <1>;
0370 #size-cells = <1>;
0371 ranges = <0 0x15d4 0x4>;
0372
0373 alwon_ethernet_clkctrl: clk@0 {
0374 compatible = "ti,clkctrl";
0375 reg = <0 0x4>;
0376 #clock-cells = <2>;
0377 };
0378 };
0379 };
