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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2012 DENX Software Engineering GmbH
0004 * Heiko Schocher <hs@denx.de>
0005 */
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 chosen { };
0012 aliases { };
0013
0014 memory@c0000000 {
0015 device_type = "memory";
0016 reg = <0xc0000000 0x0>;
0017 };
0018
0019 cpus {
0020 #address-cells = <1>;
0021 #size-cells = <0>;
0022
0023 cpu: cpu@0 {
0024 compatible = "arm,arm926ej-s";
0025 device_type = "cpu";
0026 reg = <0>;
0027 clocks = <&psc0 14>;
0028 operating-points-v2 = <&opp_table>;
0029 };
0030 };
0031
0032 opp_table: opp-table {
0033 compatible = "operating-points-v2";
0034
0035 opp_100: opp100-100000000 {
0036 opp-hz = /bits/ 64 <100000000>;
0037 opp-microvolt = <1000000 950000 1050000>;
0038 };
0039
0040 opp_200: opp110-200000000 {
0041 opp-hz = /bits/ 64 <200000000>;
0042 opp-microvolt = <1100000 1050000 1160000>;
0043 };
0044
0045 opp_300: opp120-300000000 {
0046 opp-hz = /bits/ 64 <300000000>;
0047 opp-microvolt = <1200000 1140000 1320000>;
0048 };
0049
0050 /*
0051 * Original silicon was 300MHz max, so higher frequencies
0052 * need to be enabled on a per-board basis if the chip is
0053 * capable.
0054 */
0055
0056 opp_375: opp120-375000000 {
0057 status = "disabled";
0058 opp-hz = /bits/ 64 <375000000>;
0059 opp-microvolt = <1200000 1140000 1320000>;
0060 };
0061
0062 opp_456: opp130-456000000 {
0063 status = "disabled";
0064 opp-hz = /bits/ 64 <456000000>;
0065 opp-microvolt = <1300000 1250000 1350000>;
0066 };
0067 };
0068
0069 arm {
0070 #address-cells = <1>;
0071 #size-cells = <1>;
0072 ranges;
0073 intc: interrupt-controller@fffee000 {
0074 compatible = "ti,cp-intc";
0075 interrupt-controller;
0076 #interrupt-cells = <1>;
0077 ti,intc-size = <101>;
0078 reg = <0xfffee000 0x2000>;
0079 };
0080 };
0081 clocks: clocks {
0082 ref_clk: ref_clk {
0083 compatible = "fixed-clock";
0084 #clock-cells = <0>;
0085 clock-output-names = "ref_clk";
0086 };
0087 sata_refclk: sata_refclk {
0088 compatible = "fixed-clock";
0089 #clock-cells = <0>;
0090 clock-output-names = "sata_refclk";
0091 status = "disabled";
0092 };
0093 usb_refclkin: usb_refclkin {
0094 compatible = "fixed-clock";
0095 #clock-cells = <0>;
0096 clock-output-names = "usb_refclkin";
0097 status = "disabled";
0098 };
0099 };
0100 dsp: dsp@11800000 {
0101 compatible = "ti,da850-dsp";
0102 reg = <0x11800000 0x40000>,
0103 <0x11e00000 0x8000>,
0104 <0x11f00000 0x8000>,
0105 <0x01c14044 0x4>,
0106 <0x01c14174 0x8>;
0107 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
0108 interrupt-parent = <&intc>;
0109 interrupts = <28>;
0110 clocks = <&psc0 15>;
0111 resets = <&psc0 15>;
0112 status = "disabled";
0113 };
0114 soc@1c00000 {
0115 compatible = "simple-bus";
0116 model = "da850";
0117 #address-cells = <1>;
0118 #size-cells = <1>;
0119 ranges = <0x0 0x01c00000 0x400000>;
0120 interrupt-parent = <&intc>;
0121
0122 psc0: clock-controller@10000 {
0123 compatible = "ti,da850-psc0";
0124 reg = <0x10000 0x1000>;
0125 #clock-cells = <1>;
0126 #reset-cells = <1>;
0127 #power-domain-cells = <1>;
0128 clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
0129 <&pll0_sysclk 4>, <&pll0_sysclk 6>,
0130 <&async1_clk>;
0131 clock-names = "pll0_sysclk1", "pll0_sysclk2",
0132 "pll0_sysclk4", "pll0_sysclk6",
0133 "async1";
0134 };
0135 pll0: clock-controller@11000 {
0136 compatible = "ti,da850-pll0";
0137 reg = <0x11000 0x1000>;
0138 clocks = <&ref_clk>, <&pll1_sysclk 3>;
0139 clock-names = "clksrc", "extclksrc";
0140
0141 pll0_pllout: pllout {
0142 #clock-cells = <0>;
0143 };
0144 pll0_sysclk: sysclk {
0145 #clock-cells = <1>;
0146 };
0147 pll0_auxclk: auxclk {
0148 #clock-cells = <0>;
0149 };
0150 pll0_obsclk: obsclk {
0151 #clock-cells = <0>;
0152 };
0153 };
0154 pmx_core: pinmux@14120 {
0155 compatible = "pinctrl-single";
0156 reg = <0x14120 0x50>;
0157 #pinctrl-cells = <2>;
0158 pinctrl-single,bit-per-mux;
0159 pinctrl-single,register-width = <32>;
0160 pinctrl-single,function-mask = <0xf>;
0161 /* pin base, nr pins & gpio function */
0162 pinctrl-single,gpio-range = <&range 0 17 0x8>,
0163 <&range 17 8 0x4>,
0164 <&range 26 8 0x4>,
0165 <&range 34 80 0x8>,
0166 <&range 129 31 0x8>;
0167 status = "disabled";
0168
0169 range: gpio-range {
0170 #pinctrl-single,gpio-range-cells = <3>;
0171 };
0172
0173 serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
0174 pinctrl-single,bits = <
0175 /* UART0_RTS UART0_CTS */
0176 0x0c 0x22000000 0xff000000
0177 >;
0178 };
0179 serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
0180 pinctrl-single,bits = <
0181 /* UART0_TXD UART0_RXD */
0182 0x0c 0x00220000 0x00ff0000
0183 >;
0184 };
0185 serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
0186 pinctrl-single,bits = <
0187 /* UART1_CTS UART1_RTS */
0188 0x00 0x00440000 0x00ff0000
0189 >;
0190 };
0191 serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
0192 pinctrl-single,bits = <
0193 /* UART1_TXD UART1_RXD */
0194 0x10 0x22000000 0xff000000
0195 >;
0196 };
0197 serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
0198 pinctrl-single,bits = <
0199 /* UART2_CTS UART2_RTS */
0200 0x00 0x44000000 0xff000000
0201 >;
0202 };
0203 serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
0204 pinctrl-single,bits = <
0205 /* UART2_TXD UART2_RXD */
0206 0x10 0x00220000 0x00ff0000
0207 >;
0208 };
0209 i2c0_pins: pinmux_i2c0_pins {
0210 pinctrl-single,bits = <
0211 /* I2C0_SDA,I2C0_SCL */
0212 0x10 0x00002200 0x0000ff00
0213 >;
0214 };
0215 i2c1_pins: pinmux_i2c1_pins {
0216 pinctrl-single,bits = <
0217 /* I2C1_SDA, I2C1_SCL */
0218 0x10 0x00440000 0x00ff0000
0219 >;
0220 };
0221 mmc0_pins: pinmux_mmc_pins {
0222 pinctrl-single,bits = <
0223 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
0224 * MMCSD0_DAT[1] MMCSD0_DAT[0]
0225 * MMCSD0_CMD MMCSD0_CLK
0226 */
0227 0x28 0x00222222 0x00ffffff
0228 >;
0229 };
0230 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
0231 pinctrl-single,bits = <
0232 /* EPWM0A */
0233 0xc 0x00000002 0x0000000f
0234 >;
0235 };
0236 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
0237 pinctrl-single,bits = <
0238 /* EPWM0B */
0239 0xc 0x00000020 0x000000f0
0240 >;
0241 };
0242 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
0243 pinctrl-single,bits = <
0244 /* EPWM1A */
0245 0x14 0x00000002 0x0000000f
0246 >;
0247 };
0248 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
0249 pinctrl-single,bits = <
0250 /* EPWM1B */
0251 0x14 0x00000020 0x000000f0
0252 >;
0253 };
0254 ecap0_pins: pinmux_ecap0_pins {
0255 pinctrl-single,bits = <
0256 /* ECAP0_APWM0 */
0257 0x8 0x20000000 0xf0000000
0258 >;
0259 };
0260 ecap1_pins: pinmux_ecap1_pins {
0261 pinctrl-single,bits = <
0262 /* ECAP1_APWM1 */
0263 0x4 0x40000000 0xf0000000
0264 >;
0265 };
0266 ecap2_pins: pinmux_ecap2_pins {
0267 pinctrl-single,bits = <
0268 /* ECAP2_APWM2 */
0269 0x4 0x00000004 0x0000000f
0270 >;
0271 };
0272 spi0_pins: pinmux_spi0_pins {
0273 pinctrl-single,bits = <
0274 /* SIMO, SOMI, CLK */
0275 0xc 0x00001101 0x0000ff0f
0276 >;
0277 };
0278 spi0_cs0_pin: pinmux_spi0_cs0 {
0279 pinctrl-single,bits = <
0280 /* CS0 */
0281 0x10 0x00000010 0x000000f0
0282 >;
0283 };
0284 spi0_cs3_pin: pinmux_spi0_cs3_pin {
0285 pinctrl-single,bits = <
0286 /* CS3 */
0287 0xc 0x01000000 0x0f000000
0288 >;
0289 };
0290 spi1_pins: pinmux_spi1_pins {
0291 pinctrl-single,bits = <
0292 /* SIMO, SOMI, CLK */
0293 0x14 0x00110100 0x00ff0f00
0294 >;
0295 };
0296 spi1_cs0_pin: pinmux_spi1_cs0 {
0297 pinctrl-single,bits = <
0298 /* CS0 */
0299 0x14 0x00000010 0x000000f0
0300 >;
0301 };
0302 mdio_pins: pinmux_mdio_pins {
0303 pinctrl-single,bits = <
0304 /* MDIO_CLK, MDIO_D */
0305 0x10 0x00000088 0x000000ff
0306 >;
0307 };
0308 mii_pins: pinmux_mii_pins {
0309 pinctrl-single,bits = <
0310 /*
0311 * MII_TXEN, MII_TXCLK, MII_COL
0312 * MII_TXD_3, MII_TXD_2, MII_TXD_1
0313 * MII_TXD_0
0314 */
0315 0x8 0x88888880 0xfffffff0
0316 /*
0317 * MII_RXER, MII_CRS, MII_RXCLK
0318 * MII_RXDV, MII_RXD_3, MII_RXD_2
0319 * MII_RXD_1, MII_RXD_0
0320 */
0321 0xc 0x88888888 0xffffffff
0322 >;
0323 };
0324 lcd_pins: pinmux_lcd_pins {
0325 pinctrl-single,bits = <
0326 /*
0327 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
0328 * LCD_D[6], LCD_D[7]
0329 */
0330 0x40 0x22222200 0xffffff00
0331 /*
0332 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
0333 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
0334 */
0335 0x44 0x22222222 0xffffffff
0336 /* LCD_D[8], LCD_D[9] */
0337 0x48 0x00000022 0x000000ff
0338
0339 /* LCD_PCLK */
0340 0x48 0x02000000 0x0f000000
0341 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
0342 0x4c 0x02000022 0x0f0000ff
0343 >;
0344 };
0345 vpif_capture_pins: vpif_capture_pins {
0346 pinctrl-single,bits = <
0347 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
0348 0x38 0x11111111 0xffffffff
0349 /* VP_DIN[10..15,0..1] */
0350 0x3c 0x11111111 0xffffffff
0351 /* VP_DIN[8..9] */
0352 0x40 0x00000011 0x000000ff
0353 >;
0354 };
0355 vpif_display_pins: vpif_display_pins {
0356 pinctrl-single,bits = <
0357 /* VP_DOUT[2..7] */
0358 0x40 0x11111100 0xffffff00
0359 /* VP_DOUT[10..15,0..1] */
0360 0x44 0x11111111 0xffffffff
0361 /* VP_DOUT[8..9] */
0362 0x48 0x00000011 0x000000ff
0363 /*
0364 * VP_CLKOUT3, VP_CLKIN3,
0365 * VP_CLKOUT2, VP_CLKIN2
0366 */
0367 0x4c 0x00111100 0x00ffff00
0368 >;
0369 };
0370 };
0371 prictrl: priority-controller@14110 {
0372 compatible = "ti,da850-mstpri";
0373 reg = <0x14110 0x0c>;
0374 status = "disabled";
0375 };
0376 cfgchip: chip-controller@1417c {
0377 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
0378 reg = <0x1417c 0x14>;
0379
0380 usb_phy: usb-phy {
0381 compatible = "ti,da830-usb-phy";
0382 #phy-cells = <1>;
0383 clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
0384 clock-names = "usb0_clk48", "usb1_clk48";
0385 status = "disabled";
0386 };
0387 usb_phy_clk: usb-phy-clocks {
0388 compatible = "ti,da830-usb-phy-clocks";
0389 #clock-cells = <1>;
0390 clocks = <&psc1 1>, <&usb_refclkin>,
0391 <&pll0_auxclk>;
0392 clock-names = "fck", "usb_refclkin", "auxclk";
0393 };
0394 ehrpwm_tbclk: ehrpwm_tbclk {
0395 compatible = "ti,da830-tbclksync";
0396 #clock-cells = <0>;
0397 clocks = <&psc1 17>;
0398 clock-names = "fck";
0399 };
0400 div4p5_clk: div4.5 {
0401 compatible = "ti,da830-div4p5ena";
0402 #clock-cells = <0>;
0403 clocks = <&pll0_pllout>;
0404 clock-names = "pll0_pllout";
0405 };
0406 async1_clk: async1 {
0407 compatible = "ti,da850-async1-clksrc";
0408 #clock-cells = <0>;
0409 clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
0410 clock-names = "pll0_sysclk3", "div4.5";
0411 };
0412 async3_clk: async3 {
0413 compatible = "ti,da850-async3-clksrc";
0414 #clock-cells = <0>;
0415 clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
0416 clock-names = "pll0_sysclk2", "pll1_sysclk2";
0417 };
0418 };
0419 edma0: edma@0 {
0420 compatible = "ti,edma3-tpcc";
0421 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
0422 reg = <0x0 0x8000>;
0423 reg-names = "edma3_cc";
0424 interrupts = <11 12>;
0425 interrupt-names = "edma3_ccint", "edma3_ccerrint";
0426 #dma-cells = <2>;
0427
0428 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
0429 power-domains = <&psc0 0>;
0430 };
0431 edma0_tptc0: tptc@8000 {
0432 compatible = "ti,edma3-tptc";
0433 reg = <0x8000 0x400>;
0434 interrupts = <13>;
0435 interrupt-names = "edm3_tcerrint";
0436 power-domains = <&psc0 1>;
0437 };
0438 edma0_tptc1: tptc@8400 {
0439 compatible = "ti,edma3-tptc";
0440 reg = <0x8400 0x400>;
0441 interrupts = <32>;
0442 interrupt-names = "edm3_tcerrint";
0443 power-domains = <&psc0 2>;
0444 };
0445 edma1: edma@230000 {
0446 compatible = "ti,edma3-tpcc";
0447 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
0448 reg = <0x230000 0x8000>;
0449 reg-names = "edma3_cc";
0450 interrupts = <93 94>;
0451 interrupt-names = "edma3_ccint", "edma3_ccerrint";
0452 #dma-cells = <2>;
0453
0454 ti,tptcs = <&edma1_tptc0 7>;
0455 power-domains = <&psc1 0>;
0456 };
0457 edma1_tptc0: tptc@238000 {
0458 compatible = "ti,edma3-tptc";
0459 reg = <0x238000 0x400>;
0460 interrupts = <95>;
0461 interrupt-names = "edm3_tcerrint";
0462 power-domains = <&psc1 21>;
0463 };
0464 serial0: serial@42000 {
0465 compatible = "ti,da830-uart", "ns16550a";
0466 reg = <0x42000 0x100>;
0467 reg-io-width = <4>;
0468 reg-shift = <2>;
0469 interrupts = <25>;
0470 clocks = <&psc0 9>;
0471 power-domains = <&psc0 9>;
0472 status = "disabled";
0473 };
0474 serial1: serial@10c000 {
0475 compatible = "ti,da830-uart", "ns16550a";
0476 reg = <0x10c000 0x100>;
0477 reg-io-width = <4>;
0478 reg-shift = <2>;
0479 interrupts = <53>;
0480 clocks = <&psc1 12>;
0481 power-domains = <&psc1 12>;
0482 status = "disabled";
0483 };
0484 serial2: serial@10d000 {
0485 compatible = "ti,da830-uart", "ns16550a";
0486 reg = <0x10d000 0x100>;
0487 reg-io-width = <4>;
0488 reg-shift = <2>;
0489 interrupts = <61>;
0490 clocks = <&psc1 13>;
0491 power-domains = <&psc1 13>;
0492 status = "disabled";
0493 };
0494 rtc0: rtc@23000 {
0495 compatible = "ti,da830-rtc";
0496 reg = <0x23000 0x1000>;
0497 interrupts = <19
0498 19>;
0499 clocks = <&pll0_auxclk>;
0500 clock-names = "int-clk";
0501 status = "disabled";
0502 };
0503 i2c0: i2c@22000 {
0504 compatible = "ti,davinci-i2c";
0505 reg = <0x22000 0x1000>;
0506 interrupts = <15>;
0507 #address-cells = <1>;
0508 #size-cells = <0>;
0509 clocks = <&pll0_auxclk>;
0510 status = "disabled";
0511 };
0512 i2c1: i2c@228000 {
0513 compatible = "ti,davinci-i2c";
0514 reg = <0x228000 0x1000>;
0515 interrupts = <51>;
0516 #address-cells = <1>;
0517 #size-cells = <0>;
0518 clocks = <&psc1 11>;
0519 power-domains = <&psc1 11>;
0520 status = "disabled";
0521 };
0522 clocksource: timer@20000 {
0523 compatible = "ti,da830-timer";
0524 reg = <0x20000 0x1000>;
0525 interrupts = <21>, <22>;
0526 interrupt-names = "tint12", "tint34";
0527 clocks = <&pll0_auxclk>;
0528 };
0529 wdt: wdt@21000 {
0530 compatible = "ti,davinci-wdt";
0531 reg = <0x21000 0x1000>;
0532 clocks = <&pll0_auxclk>;
0533 status = "disabled";
0534 };
0535 mmc0: mmc@40000 {
0536 compatible = "ti,da830-mmc";
0537 reg = <0x40000 0x1000>;
0538 cap-sd-highspeed;
0539 cap-mmc-highspeed;
0540 interrupts = <16>;
0541 dmas = <&edma0 16 0>, <&edma0 17 0>;
0542 dma-names = "rx", "tx";
0543 clocks = <&psc0 5>;
0544 status = "disabled";
0545 };
0546 vpif: video@217000 {
0547 compatible = "ti,da850-vpif";
0548 reg = <0x217000 0x1000>;
0549 interrupts = <92>;
0550 power-domains = <&psc1 9>;
0551 status = "disabled";
0552
0553 /* VPIF capture port */
0554 port@0 {
0555 #address-cells = <1>;
0556 #size-cells = <0>;
0557 };
0558
0559 /* VPIF display port */
0560 port@1 {
0561 #address-cells = <1>;
0562 #size-cells = <0>;
0563 };
0564 };
0565 mmc1: mmc@21b000 {
0566 compatible = "ti,da830-mmc";
0567 reg = <0x21b000 0x1000>;
0568 cap-sd-highspeed;
0569 cap-mmc-highspeed;
0570 interrupts = <72>;
0571 dmas = <&edma1 28 0>, <&edma1 29 0>;
0572 dma-names = "rx", "tx";
0573 clocks = <&psc1 18>;
0574 status = "disabled";
0575 };
0576 ehrpwm0: pwm@300000 {
0577 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
0578 #pwm-cells = <3>;
0579 reg = <0x300000 0x2000>;
0580 clocks = <&psc1 17>, <&ehrpwm_tbclk>;
0581 clock-names = "fck", "tbclk";
0582 power-domains = <&psc1 17>;
0583 status = "disabled";
0584 };
0585 ehrpwm1: pwm@302000 {
0586 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
0587 #pwm-cells = <3>;
0588 reg = <0x302000 0x2000>;
0589 clocks = <&psc1 17>, <&ehrpwm_tbclk>;
0590 clock-names = "fck", "tbclk";
0591 power-domains = <&psc1 17>;
0592 status = "disabled";
0593 };
0594 ecap0: pwm@306000 {
0595 compatible = "ti,da850-ecap", "ti,am3352-ecap";
0596 #pwm-cells = <3>;
0597 reg = <0x306000 0x80>;
0598 clocks = <&psc1 20>;
0599 clock-names = "fck";
0600 power-domains = <&psc1 20>;
0601 status = "disabled";
0602 };
0603 ecap1: pwm@307000 {
0604 compatible = "ti,da850-ecap", "ti,am3352-ecap";
0605 #pwm-cells = <3>;
0606 reg = <0x307000 0x80>;
0607 clocks = <&psc1 20>;
0608 clock-names = "fck";
0609 power-domains = <&psc1 20>;
0610 status = "disabled";
0611 };
0612 ecap2: pwm@308000 {
0613 compatible = "ti,da850-ecap", "ti,am3352-ecap";
0614 #pwm-cells = <3>;
0615 reg = <0x308000 0x80>;
0616 clocks = <&psc1 20>;
0617 clock-names = "fck";
0618 power-domains = <&psc1 20>;
0619 status = "disabled";
0620 };
0621 spi0: spi@41000 {
0622 #address-cells = <1>;
0623 #size-cells = <0>;
0624 compatible = "ti,da830-spi";
0625 reg = <0x41000 0x1000>;
0626 num-cs = <6>;
0627 ti,davinci-spi-intr-line = <1>;
0628 interrupts = <20>;
0629 dmas = <&edma0 14 0>, <&edma0 15 0>;
0630 dma-names = "rx", "tx";
0631 clocks = <&psc0 4>;
0632 power-domains = <&psc0 4>;
0633 status = "disabled";
0634 };
0635 spi1: spi@30e000 {
0636 #address-cells = <1>;
0637 #size-cells = <0>;
0638 compatible = "ti,da830-spi";
0639 reg = <0x30e000 0x1000>;
0640 num-cs = <4>;
0641 ti,davinci-spi-intr-line = <1>;
0642 interrupts = <56>;
0643 dmas = <&edma0 18 0>, <&edma0 19 0>;
0644 dma-names = "rx", "tx";
0645 clocks = <&psc1 10>;
0646 power-domains = <&psc1 10>;
0647 status = "disabled";
0648 };
0649 usb0: usb@200000 {
0650 compatible = "ti,da830-musb";
0651 reg = <0x200000 0x1000>;
0652 ranges;
0653 interrupts = <58>;
0654 interrupt-names = "mc";
0655 dr_mode = "otg";
0656 phys = <&usb_phy 0>;
0657 phy-names = "usb-phy";
0658 clocks = <&psc1 1>;
0659 clock-ranges;
0660 status = "disabled";
0661
0662 #address-cells = <1>;
0663 #size-cells = <1>;
0664
0665 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
0666 &cppi41dma 2 0 &cppi41dma 3 0
0667 &cppi41dma 0 1 &cppi41dma 1 1
0668 &cppi41dma 2 1 &cppi41dma 3 1>;
0669 dma-names =
0670 "rx1", "rx2", "rx3", "rx4",
0671 "tx1", "tx2", "tx3", "tx4";
0672
0673 cppi41dma: dma-controller@201000 {
0674 compatible = "ti,da830-cppi41";
0675 reg = <0x201000 0x1000
0676 0x202000 0x1000
0677 0x204000 0x4000>;
0678 reg-names = "controller",
0679 "scheduler", "queuemgr";
0680 interrupts = <58>;
0681 #dma-cells = <2>;
0682 /* For backwards compatibility: */
0683 #dma-channels = <4>;
0684 dma-channels = <4>;
0685 power-domains = <&psc1 1>;
0686 status = "okay";
0687 };
0688 };
0689 sata: sata@218000 {
0690 compatible = "ti,da850-ahci";
0691 reg = <0x218000 0x2000>, <0x22c018 0x4>;
0692 interrupts = <67>;
0693 clocks = <&psc1 8>, <&sata_refclk>;
0694 clock-names = "fck", "refclk";
0695 status = "disabled";
0696 };
0697 pll1: clock-controller@21a000 {
0698 compatible = "ti,da850-pll1";
0699 reg = <0x21a000 0x1000>;
0700 clocks = <&ref_clk>;
0701 clock-names = "clksrc";
0702
0703 pll1_sysclk: sysclk {
0704 #clock-cells = <1>;
0705 };
0706 pll1_obsclk: obsclk {
0707 #clock-cells = <0>;
0708 };
0709 };
0710 mdio: mdio@224000 {
0711 compatible = "ti,davinci_mdio";
0712 #address-cells = <1>;
0713 #size-cells = <0>;
0714 reg = <0x224000 0x1000>;
0715 clocks = <&psc1 5>;
0716 clock-names = "fck";
0717 power-domains = <&psc1 5>;
0718 status = "disabled";
0719 };
0720 eth0: ethernet@220000 {
0721 compatible = "ti,davinci-dm6467-emac";
0722 reg = <0x220000 0x4000>;
0723 ti,davinci-ctrl-reg-offset = <0x3000>;
0724 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
0725 ti,davinci-ctrl-ram-offset = <0>;
0726 ti,davinci-ctrl-ram-size = <0x2000>;
0727 local-mac-address = [ 00 00 00 00 00 00 ];
0728 interrupts = <33
0729 34
0730 35
0731 36
0732 >;
0733 clocks = <&psc1 5>;
0734 power-domains = <&psc1 5>;
0735 status = "disabled";
0736 };
0737 usb1: usb@225000 {
0738 compatible = "ti,da830-ohci";
0739 reg = <0x225000 0x1000>;
0740 interrupts = <59>;
0741 phys = <&usb_phy 1>;
0742 phy-names = "usb-phy";
0743 clocks = <&psc1 2>;
0744 status = "disabled";
0745 };
0746 gpio: gpio@226000 {
0747 compatible = "ti,dm6441-gpio";
0748 gpio-controller;
0749 #gpio-cells = <2>;
0750 reg = <0x226000 0x1000>;
0751 interrupts = <42 43 44 45 46 47 48 49 50>;
0752 ti,ngpio = <144>;
0753 ti,davinci-gpio-unbanked = <0>;
0754 clocks = <&psc1 3>;
0755 clock-names = "gpio";
0756 status = "disabled";
0757 interrupt-controller;
0758 #interrupt-cells = <2>;
0759 gpio-ranges = <&pmx_core 0 15 1>,
0760 <&pmx_core 1 14 1>,
0761 <&pmx_core 2 13 1>,
0762 <&pmx_core 3 12 1>,
0763 <&pmx_core 4 11 1>,
0764 <&pmx_core 5 10 1>,
0765 <&pmx_core 6 9 1>,
0766 <&pmx_core 7 8 1>,
0767 <&pmx_core 8 7 1>,
0768 <&pmx_core 9 6 1>,
0769 <&pmx_core 10 5 1>,
0770 <&pmx_core 11 4 1>,
0771 <&pmx_core 12 3 1>,
0772 <&pmx_core 13 2 1>,
0773 <&pmx_core 14 1 1>,
0774 <&pmx_core 15 0 1>,
0775 <&pmx_core 16 39 1>,
0776 <&pmx_core 17 38 1>,
0777 <&pmx_core 18 37 1>,
0778 <&pmx_core 19 36 1>,
0779 <&pmx_core 20 35 1>,
0780 <&pmx_core 21 34 1>,
0781 <&pmx_core 22 33 1>,
0782 <&pmx_core 23 32 1>,
0783 <&pmx_core 24 24 1>,
0784 <&pmx_core 25 22 1>,
0785 <&pmx_core 26 21 1>,
0786 <&pmx_core 27 20 1>,
0787 <&pmx_core 28 19 1>,
0788 <&pmx_core 29 18 1>,
0789 <&pmx_core 30 17 1>,
0790 <&pmx_core 31 16 1>,
0791 <&pmx_core 32 55 1>,
0792 <&pmx_core 33 54 1>,
0793 <&pmx_core 34 53 1>,
0794 <&pmx_core 35 52 1>,
0795 <&pmx_core 36 51 1>,
0796 <&pmx_core 37 50 1>,
0797 <&pmx_core 38 49 1>,
0798 <&pmx_core 39 48 1>,
0799 <&pmx_core 40 47 1>,
0800 <&pmx_core 41 46 1>,
0801 <&pmx_core 42 45 1>,
0802 <&pmx_core 43 44 1>,
0803 <&pmx_core 44 43 1>,
0804 <&pmx_core 45 42 1>,
0805 <&pmx_core 46 41 1>,
0806 <&pmx_core 47 40 1>,
0807 <&pmx_core 48 71 1>,
0808 <&pmx_core 49 70 1>,
0809 <&pmx_core 50 69 1>,
0810 <&pmx_core 51 68 1>,
0811 <&pmx_core 52 67 1>,
0812 <&pmx_core 53 66 1>,
0813 <&pmx_core 54 65 1>,
0814 <&pmx_core 55 64 1>,
0815 <&pmx_core 56 63 1>,
0816 <&pmx_core 57 62 1>,
0817 <&pmx_core 58 61 1>,
0818 <&pmx_core 59 60 1>,
0819 <&pmx_core 60 59 1>,
0820 <&pmx_core 61 58 1>,
0821 <&pmx_core 62 57 1>,
0822 <&pmx_core 63 56 1>,
0823 <&pmx_core 64 87 1>,
0824 <&pmx_core 65 86 1>,
0825 <&pmx_core 66 85 1>,
0826 <&pmx_core 67 84 1>,
0827 <&pmx_core 68 83 1>,
0828 <&pmx_core 69 82 1>,
0829 <&pmx_core 70 81 1>,
0830 <&pmx_core 71 80 1>,
0831 <&pmx_core 72 70 1>,
0832 <&pmx_core 73 78 1>,
0833 <&pmx_core 74 77 1>,
0834 <&pmx_core 75 76 1>,
0835 <&pmx_core 76 75 1>,
0836 <&pmx_core 77 74 1>,
0837 <&pmx_core 78 73 1>,
0838 <&pmx_core 79 72 1>,
0839 <&pmx_core 80 103 1>,
0840 <&pmx_core 81 102 1>,
0841 <&pmx_core 82 101 1>,
0842 <&pmx_core 83 100 1>,
0843 <&pmx_core 84 99 1>,
0844 <&pmx_core 85 98 1>,
0845 <&pmx_core 86 97 1>,
0846 <&pmx_core 87 96 1>,
0847 <&pmx_core 88 95 1>,
0848 <&pmx_core 89 94 1>,
0849 <&pmx_core 90 93 1>,
0850 <&pmx_core 91 92 1>,
0851 <&pmx_core 92 91 1>,
0852 <&pmx_core 93 90 1>,
0853 <&pmx_core 94 89 1>,
0854 <&pmx_core 95 88 1>,
0855 <&pmx_core 96 158 1>,
0856 <&pmx_core 97 157 1>,
0857 <&pmx_core 98 156 1>,
0858 <&pmx_core 99 155 1>,
0859 <&pmx_core 100 154 1>,
0860 <&pmx_core 101 129 1>,
0861 <&pmx_core 102 113 1>,
0862 <&pmx_core 103 112 1>,
0863 <&pmx_core 104 111 1>,
0864 <&pmx_core 105 110 1>,
0865 <&pmx_core 106 109 1>,
0866 <&pmx_core 107 108 1>,
0867 <&pmx_core 108 107 1>,
0868 <&pmx_core 109 106 1>,
0869 <&pmx_core 110 105 1>,
0870 <&pmx_core 111 104 1>,
0871 <&pmx_core 112 145 1>,
0872 <&pmx_core 113 144 1>,
0873 <&pmx_core 114 143 1>,
0874 <&pmx_core 115 142 1>,
0875 <&pmx_core 116 141 1>,
0876 <&pmx_core 117 140 1>,
0877 <&pmx_core 118 139 1>,
0878 <&pmx_core 119 138 1>,
0879 <&pmx_core 120 137 1>,
0880 <&pmx_core 121 136 1>,
0881 <&pmx_core 122 135 1>,
0882 <&pmx_core 123 134 1>,
0883 <&pmx_core 124 133 1>,
0884 <&pmx_core 125 132 1>,
0885 <&pmx_core 126 131 1>,
0886 <&pmx_core 127 130 1>,
0887 <&pmx_core 128 159 1>,
0888 <&pmx_core 129 31 1>,
0889 <&pmx_core 130 30 1>,
0890 <&pmx_core 131 20 1>,
0891 <&pmx_core 132 28 1>,
0892 <&pmx_core 133 27 1>,
0893 <&pmx_core 134 26 1>,
0894 <&pmx_core 135 23 1>,
0895 <&pmx_core 136 153 1>,
0896 <&pmx_core 137 152 1>,
0897 <&pmx_core 138 151 1>,
0898 <&pmx_core 139 150 1>,
0899 <&pmx_core 140 149 1>,
0900 <&pmx_core 141 148 1>,
0901 <&pmx_core 142 147 1>,
0902 <&pmx_core 143 146 1>;
0903 };
0904 psc1: clock-controller@227000 {
0905 compatible = "ti,da850-psc1";
0906 reg = <0x227000 0x1000>;
0907 #clock-cells = <1>;
0908 #power-domain-cells = <1>;
0909 clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
0910 <&async3_clk>;
0911 clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
0912 assigned-clocks = <&async3_clk>;
0913 assigned-clock-parents = <&pll1_sysclk 2>;
0914 };
0915 pinconf: pin-controller@22c00c {
0916 compatible = "ti,da850-pupd";
0917 reg = <0x22c00c 0x8>;
0918 status = "disabled";
0919 };
0920
0921 mcasp0: mcasp@100000 {
0922 compatible = "ti,da830-mcasp-audio";
0923 reg = <0x100000 0x2000>,
0924 <0x102000 0x400000>;
0925 reg-names = "mpu", "dat";
0926 interrupts = <54>;
0927 interrupt-names = "common";
0928 power-domains = <&psc1 7>;
0929 status = "disabled";
0930 dmas = <&edma0 1 1>,
0931 <&edma0 0 1>;
0932 dma-names = "tx", "rx";
0933 };
0934
0935 lcdc: display@213000 {
0936 compatible = "ti,da850-tilcdc";
0937 reg = <0x213000 0x1000>;
0938 interrupts = <52>;
0939 max-pixelclock = <37500>;
0940 clocks = <&psc1 16>;
0941 clock-names = "fck";
0942 power-domains = <&psc1 16>;
0943 status = "disabled";
0944 };
0945 };
0946 aemif: aemif@68000000 {
0947 compatible = "ti,da850-aemif";
0948 #address-cells = <2>;
0949 #size-cells = <1>;
0950
0951 reg = <0x68000000 0x00008000>;
0952 ranges = <0 0 0x60000000 0x08000000
0953 1 0 0x68000000 0x00008000>;
0954 clocks = <&psc0 3>;
0955 clock-names = "aemif";
0956 clock-ranges;
0957 status = "disabled";
0958 };
0959 memctrl: memory-controller@b0000000 {
0960 compatible = "ti,da850-ddr-controller";
0961 reg = <0xb0000000 0xe8>;
0962 status = "disabled";
0963 };
0964 };
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