0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2016 BayLibre, Inc.
0004 */
0005 /dts-v1/;
0006 #include "da850.dtsi"
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/input/input.h>
0009
0010 / {
0011 model = "DA850/AM1808/OMAP-L138 LCDK";
0012 compatible = "ti,da850-lcdk", "ti,da850";
0013
0014 aliases {
0015 serial2 = &serial2;
0016 ethernet0 = ð0;
0017 };
0018
0019 chosen {
0020 stdout-path = "serial2:115200n8";
0021 };
0022
0023 memory@c0000000 {
0024 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
0025 reg = <0xc0000000 0x08000000>;
0026 };
0027
0028 reserved-memory {
0029 #address-cells = <1>;
0030 #size-cells = <1>;
0031 ranges;
0032
0033 dsp_memory_region: dsp-memory@c3000000 {
0034 compatible = "shared-dma-pool";
0035 reg = <0xc3000000 0x1000000>;
0036 reusable;
0037 status = "okay";
0038 };
0039 };
0040
0041 vcc_5vd: fixedregulator-vcc_5vd {
0042 compatible = "regulator-fixed";
0043 regulator-name = "vcc_5vd";
0044 regulator-min-microvolt = <5000000>;
0045 regulator-max-microvolt = <5000000>;
0046 regulator-boot-on;
0047 };
0048
0049 vcc_3v3d: fixedregulator-vcc_3v3d {
0050 /* TPS650250 - VDCDC1 */
0051 compatible = "regulator-fixed";
0052 regulator-name = "vcc_3v3d";
0053 regulator-min-microvolt = <3300000>;
0054 regulator-max-microvolt = <3300000>;
0055 vin-supply = <&vcc_5vd>;
0056 regulator-always-on;
0057 regulator-boot-on;
0058 };
0059
0060 vcc_1v8d: fixedregulator-vcc_1v8d {
0061 /* TPS650250 - VDCDC2 */
0062 compatible = "regulator-fixed";
0063 regulator-name = "vcc_1v8d";
0064 regulator-min-microvolt = <1800000>;
0065 regulator-max-microvolt = <1800000>;
0066 vin-supply = <&vcc_5vd>;
0067 regulator-always-on;
0068 regulator-boot-on;
0069 };
0070
0071 sound {
0072 compatible = "simple-audio-card";
0073 simple-audio-card,name = "DA850-OMAPL138 LCDK";
0074 simple-audio-card,widgets =
0075 "Line", "Line In",
0076 "Line", "Line Out",
0077 "Microphone", "Mic Jack";
0078 simple-audio-card,routing =
0079 "LINE1L", "Line In",
0080 "LINE1R", "Line In",
0081 "Line Out", "LLOUT",
0082 "Line Out", "RLOUT",
0083 "MIC3L", "Mic Jack",
0084 "MIC3R", "Mic Jack",
0085 "Mic Jack", "Mic Bias";
0086 simple-audio-card,format = "dsp_b";
0087 simple-audio-card,bitclock-master = <&link0_codec>;
0088 simple-audio-card,frame-master = <&link0_codec>;
0089 simple-audio-card,bitclock-inversion;
0090
0091 simple-audio-card,cpu {
0092 sound-dai = <&mcasp0>;
0093 system-clock-frequency = <24576000>;
0094 };
0095
0096 link0_codec: simple-audio-card,codec {
0097 sound-dai = <&tlv320aic3106>;
0098 system-clock-frequency = <24576000>;
0099 };
0100 };
0101
0102 gpio-keys {
0103 compatible = "gpio-keys";
0104 autorepeat;
0105
0106 user1 {
0107 label = "GPIO Key USER1";
0108 linux,code = <BTN_0>;
0109 gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
0110 };
0111
0112 user2 {
0113 label = "GPIO Key USER2";
0114 linux,code = <BTN_1>;
0115 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
0116 };
0117 };
0118
0119 vga-bridge {
0120 compatible = "ti,ths8135";
0121 #address-cells = <1>;
0122 #size-cells = <0>;
0123
0124 ports {
0125 #address-cells = <1>;
0126 #size-cells = <0>;
0127
0128 port@0 {
0129 reg = <0>;
0130
0131 vga_bridge_in: endpoint {
0132 remote-endpoint = <&lcdc_out_vga>;
0133 };
0134 };
0135
0136 port@1 {
0137 reg = <1>;
0138
0139 vga_bridge_out: endpoint {
0140 remote-endpoint = <&vga_con_in>;
0141 };
0142 };
0143 };
0144 };
0145
0146 vga {
0147 compatible = "vga-connector";
0148
0149 ddc-i2c-bus = <&i2c0>;
0150
0151 port {
0152 vga_con_in: endpoint {
0153 remote-endpoint = <&vga_bridge_out>;
0154 };
0155 };
0156 };
0157
0158 cvdd: regulator0 {
0159 compatible = "regulator-fixed";
0160 regulator-name = "cvdd";
0161 regulator-min-microvolt = <1300000>;
0162 regulator-max-microvolt = <1300000>;
0163 regulator-always-on;
0164 regulator-boot-on;
0165 };
0166 };
0167
0168 &ref_clk {
0169 clock-frequency = <24000000>;
0170 };
0171
0172 &cpu {
0173 cpu-supply = <&cvdd>;
0174 };
0175
0176 /*
0177 * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
0178 * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
0179 * can't enable more than one OPP by default, since the controller sometimes
0180 * becomes unresponsive after a transition. Fix the frequency at 456 MHz.
0181 */
0182
0183 &opp_100 {
0184 status = "disabled";
0185 };
0186
0187 &opp_200 {
0188 status = "disabled";
0189 };
0190
0191 &opp_300 {
0192 status = "disabled";
0193 };
0194
0195 &opp_456 {
0196 status = "okay";
0197 };
0198
0199 &pmx_core {
0200 status = "okay";
0201
0202 mcasp0_pins: pinmux_mcasp0_pins {
0203 pinctrl-single,bits = <
0204 /* AHCLKX AFSX ACLKX */
0205 0x00 0x00101010 0x00f0f0f0
0206 /* ARX13 ARX14 */
0207 0x04 0x00000110 0x00000ff0
0208 >;
0209 };
0210
0211 nand_pins: nand_pins {
0212 pinctrl-single,bits = <
0213 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
0214 0x1c 0x10110010 0xf0ff00f0
0215 /*
0216 * EMA_D[0], EMA_D[1], EMA_D[2],
0217 * EMA_D[3], EMA_D[4], EMA_D[5],
0218 * EMA_D[6], EMA_D[7]
0219 */
0220 0x24 0x11111111 0xffffffff
0221 /*
0222 * EMA_D[8], EMA_D[9], EMA_D[10],
0223 * EMA_D[11], EMA_D[12], EMA_D[13],
0224 * EMA_D[14], EMA_D[15]
0225 */
0226 0x20 0x11111111 0xffffffff
0227 /* EMA_A[1], EMA_A[2] */
0228 0x30 0x01100000 0x0ff00000
0229 >;
0230 };
0231 };
0232
0233 &serial2 {
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&serial2_rxtx_pins>;
0236 status = "okay";
0237 };
0238
0239 &wdt {
0240 status = "okay";
0241 };
0242
0243 &rtc0 {
0244 status = "okay";
0245 };
0246
0247 &gpio {
0248 status = "okay";
0249 };
0250
0251 &sata_refclk {
0252 status = "okay";
0253 clock-frequency = <100000000>;
0254 };
0255
0256 &sata {
0257 status = "okay";
0258 };
0259
0260 &mdio {
0261 pinctrl-names = "default";
0262 pinctrl-0 = <&mdio_pins>;
0263 bus_freq = <2200000>;
0264 status = "okay";
0265 };
0266
0267 ð0 {
0268 pinctrl-names = "default";
0269 pinctrl-0 = <&mii_pins>;
0270 status = "okay";
0271 };
0272
0273 &mmc0 {
0274 max-frequency = <50000000>;
0275 bus-width = <4>;
0276 pinctrl-names = "default";
0277 pinctrl-0 = <&mmc0_pins>;
0278 cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
0279 status = "okay";
0280 };
0281
0282 &i2c0 {
0283 pinctrl-names = "default";
0284 pinctrl-0 = <&i2c0_pins>;
0285 clock-frequency = <100000>;
0286 status = "okay";
0287
0288 tlv320aic3106: tlv320aic3106@18 {
0289 #sound-dai-cells = <0>;
0290 compatible = "ti,tlv320aic3106";
0291 reg = <0x18>;
0292 adc-settle-ms = <40>;
0293 ai3x-micbias-vg = <1>; /* 2.0V */
0294 status = "okay";
0295
0296 /* Regulators */
0297 IOVDD-supply = <&vcc_3v3d>;
0298 AVDD-supply = <&vcc_3v3d>;
0299 DRVDD-supply = <&vcc_3v3d>;
0300 DVDD-supply = <&vcc_1v8d>;
0301 };
0302 };
0303
0304 &mcasp0 {
0305 #sound-dai-cells = <0>;
0306 pinctrl-names = "default";
0307 pinctrl-0 = <&mcasp0_pins>;
0308 status = "okay";
0309
0310 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
0311 tdm-slots = <2>;
0312 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0313 0 0 0 0
0314 0 0 0 0
0315 0 0 0 0
0316 0 1 2 0
0317 >;
0318 tx-num-evt = <32>;
0319 rx-num-evt = <32>;
0320 };
0321
0322 &usb_phy {
0323 status = "okay";
0324 };
0325
0326 &usb0 {
0327 status = "okay";
0328 };
0329
0330 &usb1 {
0331 status = "okay";
0332 };
0333
0334 &aemif {
0335 pinctrl-names = "default";
0336 pinctrl-0 = <&nand_pins>;
0337 status = "okay";
0338 cs3 {
0339 #address-cells = <2>;
0340 #size-cells = <1>;
0341 clock-ranges;
0342 ranges;
0343
0344 ti,cs-chipselect = <3>;
0345
0346 nand@2000000,0 {
0347 compatible = "ti,davinci-nand";
0348 #address-cells = <1>;
0349 #size-cells = <1>;
0350 reg = <0 0x02000000 0x02000000
0351 1 0x00000000 0x00008000>;
0352
0353 ti,davinci-chipselect = <1>;
0354 ti,davinci-mask-ale = <0>;
0355 ti,davinci-mask-cle = <0>;
0356 ti,davinci-mask-chipsel = <0>;
0357
0358 ti,davinci-nand-buswidth = <16>;
0359 ti,davinci-ecc-mode = "hw";
0360 ti,davinci-ecc-bits = <4>;
0361 ti,davinci-nand-use-bbt;
0362
0363 /*
0364 * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
0365 * "To boot from NAND Flash, the AIS should be written
0366 * to NAND block 1 (NAND block 0 is not used by default)".
0367 * The same doc mentions that for ROM "Silicon Revision 2.1",
0368 * "Updated NAND boot mode to offer boot from block 0 or block 1".
0369 * However the limitaion is left here by default for compatibility
0370 * with older silicon and because it needs new boot pin settings
0371 * not possible in stock LCDK.
0372 */
0373 partitions {
0374 compatible = "fixed-partitions";
0375 #address-cells = <1>;
0376 #size-cells = <1>;
0377
0378 partition@0 {
0379 label = "u-boot env";
0380 reg = <0 0x020000>;
0381 };
0382 partition@20000 {
0383 /* The LCDK defaults to booting from this partition */
0384 label = "u-boot";
0385 reg = <0x020000 0x080000>;
0386 };
0387 partition@a0000 {
0388 label = "free space";
0389 reg = <0x0a0000 0>;
0390 };
0391 };
0392 };
0393 };
0394 };
0395
0396 &prictrl {
0397 status = "okay";
0398 };
0399
0400 &memctrl {
0401 status = "okay";
0402 };
0403
0404 &lcdc {
0405 status = "okay";
0406 pinctrl-names = "default";
0407 pinctrl-0 = <&lcd_pins>;
0408
0409 port {
0410 lcdc_out_vga: endpoint {
0411 remote-endpoint = <&vga_bridge_in>;
0412 };
0413 };
0414 };
0415
0416 &vpif {
0417 pinctrl-names = "default";
0418 pinctrl-0 = <&vpif_capture_pins>;
0419 status = "okay";
0420 };
0421
0422 &dsp {
0423 memory-region = <&dsp_memory_region>;
0424 status = "okay";
0425 };
