OSCL-LXR |
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0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
0004 */
0005
0006 #include <dt-bindings/clock/berlin2q.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008
0009 / {
0010 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
0011 compatible = "marvell,berlin2q", "marvell,berlin";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 aliases {
0016 serial0 = &uart0;
0017 serial1 = &uart1;
0018 };
0019
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023 enable-method = "marvell,berlin-smp";
0024
0025 cpu0: cpu@0 {
0026 compatible = "arm,cortex-a9";
0027 device_type = "cpu";
0028 next-level-cache = <&l2>;
0029 reg = <0>;
0030
0031 clocks = <&chip_clk CLKID_CPU>;
0032 clock-latency = <100000>;
0033 /* Can be modified by the bootloader */
0034 operating-points = <
0035 /* kHz uV */
0036 1200000 1200000
0037 1000000 1200000
0038 800000 1200000
0039 600000 1200000
0040 >;
0041 };
0042
0043 cpu1: cpu@1 {
0044 compatible = "arm,cortex-a9";
0045 device_type = "cpu";
0046 next-level-cache = <&l2>;
0047 reg = <1>;
0048
0049 clocks = <&chip_clk CLKID_CPU>;
0050 clock-latency = <100000>;
0051 /* Can be modified by the bootloader */
0052 operating-points = <
0053 /* kHz uV */
0054 1200000 1200000
0055 1000000 1200000
0056 800000 1200000
0057 600000 1200000
0058 >;
0059 };
0060
0061 cpu2: cpu@2 {
0062 compatible = "arm,cortex-a9";
0063 device_type = "cpu";
0064 next-level-cache = <&l2>;
0065 reg = <2>;
0066
0067 clocks = <&chip_clk CLKID_CPU>;
0068 clock-latency = <100000>;
0069 /* Can be modified by the bootloader */
0070 operating-points = <
0071 /* kHz uV */
0072 1200000 1200000
0073 1000000 1200000
0074 800000 1200000
0075 600000 1200000
0076 >;
0077 };
0078
0079 cpu3: cpu@3 {
0080 compatible = "arm,cortex-a9";
0081 device_type = "cpu";
0082 next-level-cache = <&l2>;
0083 reg = <3>;
0084
0085 clocks = <&chip_clk CLKID_CPU>;
0086 clock-latency = <100000>;
0087 /* Can be modified by the bootloader */
0088 operating-points = <
0089 /* kHz uV */
0090 1200000 1200000
0091 1000000 1200000
0092 800000 1200000
0093 600000 1200000
0094 >;
0095 };
0096 };
0097
0098 pmu {
0099 compatible = "arm,cortex-a9-pmu";
0100 interrupt-parent = <&gic>;
0101 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0102 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0105 interrupt-affinity = <&cpu0>,
0106 <&cpu1>,
0107 <&cpu2>,
0108 <&cpu3>;
0109 };
0110
0111 refclk: oscillator {
0112 compatible = "fixed-clock";
0113 #clock-cells = <0>;
0114 clock-frequency = <25000000>;
0115 };
0116
0117 soc@f7000000 {
0118 compatible = "simple-bus";
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121
0122 ranges = <0 0xf7000000 0x1000000>;
0123 interrupt-parent = <&gic>;
0124
0125 sdhci0: mmc@ab0000 {
0126 compatible = "mrvl,pxav3-mmc";
0127 reg = <0xab0000 0x200>;
0128 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
0129 clock-names = "io", "core";
0130 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0131 status = "disabled";
0132 };
0133
0134 sdhci1: mmc@ab0800 {
0135 compatible = "mrvl,pxav3-mmc";
0136 reg = <0xab0800 0x200>;
0137 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
0138 clock-names = "io", "core";
0139 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0140 status = "disabled";
0141 };
0142
0143 sdhci2: mmc@ab1000 {
0144 compatible = "mrvl,pxav3-mmc";
0145 reg = <0xab1000 0x200>;
0146 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0147 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
0148 clock-names = "io", "core";
0149 status = "disabled";
0150 };
0151
0152 l2: cache-controller@ac0000 {
0153 compatible = "arm,pl310-cache";
0154 reg = <0xac0000 0x1000>;
0155 cache-unified;
0156 cache-level = <2>;
0157 arm,data-latency = <2 2 2>;
0158 arm,tag-latency = <2 2 2>;
0159 };
0160
0161 scu: snoop-control-unit@ad0000 {
0162 compatible = "arm,cortex-a9-scu";
0163 reg = <0xad0000 0x58>;
0164 };
0165
0166 local-timer@ad0600 {
0167 compatible = "arm,cortex-a9-twd-timer";
0168 reg = <0xad0600 0x20>;
0169 clocks = <&chip_clk CLKID_TWD>;
0170 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0171 };
0172
0173 gic: interrupt-controller@ad1000 {
0174 compatible = "arm,cortex-a9-gic";
0175 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
0176 interrupt-controller;
0177 #interrupt-cells = <3>;
0178 };
0179
0180 usb_phy2: phy@a2f400 {
0181 compatible = "marvell,berlin2cd-usb-phy";
0182 reg = <0xa2f400 0x128>;
0183 #phy-cells = <0>;
0184 resets = <&chip_rst 0x104 14>;
0185 status = "disabled";
0186 };
0187
0188 usb2: usb@a30000 {
0189 compatible = "chipidea,usb2";
0190 reg = <0xa30000 0x10000>;
0191 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0192 clocks = <&chip_clk CLKID_USB2>;
0193 phys = <&usb_phy2>;
0194 phy-names = "usb-phy";
0195 status = "disabled";
0196 };
0197
0198 usb_phy0: phy@b74000 {
0199 compatible = "marvell,berlin2cd-usb-phy";
0200 reg = <0xb74000 0x128>;
0201 #phy-cells = <0>;
0202 resets = <&chip_rst 0x104 12>;
0203 status = "disabled";
0204 };
0205
0206 usb_phy1: phy@b78000 {
0207 compatible = "marvell,berlin2cd-usb-phy";
0208 reg = <0xb78000 0x128>;
0209 #phy-cells = <0>;
0210 resets = <&chip_rst 0x104 13>;
0211 status = "disabled";
0212 };
0213
0214 eth0: ethernet@b90000 {
0215 compatible = "marvell,pxa168-eth";
0216 reg = <0xb90000 0x10000>;
0217 clocks = <&chip_clk CLKID_GETH0>;
0218 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0219 /* set by bootloader */
0220 local-mac-address = [00 00 00 00 00 00];
0221 #address-cells = <1>;
0222 #size-cells = <0>;
0223 phy-connection-type = "mii";
0224 phy-handle = <ðphy0>;
0225 status = "disabled";
0226
0227 ethphy0: ethernet-phy@0 {
0228 reg = <0>;
0229 };
0230 };
0231
0232 cpu-ctrl@dd0000 {
0233 compatible = "marvell,berlin-cpu-ctrl";
0234 reg = <0xdd0000 0x10000>;
0235 };
0236
0237 apb@e80000 {
0238 compatible = "simple-bus";
0239 #address-cells = <1>;
0240 #size-cells = <1>;
0241
0242 ranges = <0 0xe80000 0x10000>;
0243 interrupt-parent = <&aic>;
0244
0245 gpio0: gpio@400 {
0246 compatible = "snps,dw-apb-gpio";
0247 reg = <0x0400 0x400>;
0248 #address-cells = <1>;
0249 #size-cells = <0>;
0250
0251 porta: gpio-port@0 {
0252 compatible = "snps,dw-apb-gpio-port";
0253 gpio-controller;
0254 #gpio-cells = <2>;
0255 ngpios = <32>;
0256 reg = <0>;
0257 interrupt-controller;
0258 #interrupt-cells = <2>;
0259 interrupts = <0>;
0260 };
0261 };
0262
0263 gpio1: gpio@800 {
0264 compatible = "snps,dw-apb-gpio";
0265 reg = <0x0800 0x400>;
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268
0269 portb: gpio-port@1 {
0270 compatible = "snps,dw-apb-gpio-port";
0271 gpio-controller;
0272 #gpio-cells = <2>;
0273 ngpios = <32>;
0274 reg = <0>;
0275 interrupt-controller;
0276 #interrupt-cells = <2>;
0277 interrupts = <1>;
0278 };
0279 };
0280
0281 gpio2: gpio@c00 {
0282 compatible = "snps,dw-apb-gpio";
0283 reg = <0x0c00 0x400>;
0284 #address-cells = <1>;
0285 #size-cells = <0>;
0286
0287 portc: gpio-port@2 {
0288 compatible = "snps,dw-apb-gpio-port";
0289 gpio-controller;
0290 #gpio-cells = <2>;
0291 ngpios = <32>;
0292 reg = <0>;
0293 interrupt-controller;
0294 #interrupt-cells = <2>;
0295 interrupts = <2>;
0296 };
0297 };
0298
0299 gpio3: gpio@1000 {
0300 compatible = "snps,dw-apb-gpio";
0301 reg = <0x1000 0x400>;
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304
0305 portd: gpio-port@3 {
0306 compatible = "snps,dw-apb-gpio-port";
0307 gpio-controller;
0308 #gpio-cells = <2>;
0309 ngpios = <32>;
0310 reg = <0>;
0311 interrupt-controller;
0312 #interrupt-cells = <2>;
0313 interrupts = <3>;
0314 };
0315 };
0316
0317 i2c0: i2c@1400 {
0318 compatible = "snps,designware-i2c";
0319 #address-cells = <1>;
0320 #size-cells = <0>;
0321 reg = <0x1400 0x100>;
0322 interrupts = <4>;
0323 clocks = <&chip_clk CLKID_CFG>;
0324 pinctrl-0 = <&twsi0_pmux>;
0325 pinctrl-names = "default";
0326 status = "disabled";
0327 };
0328
0329 i2c1: i2c@1800 {
0330 compatible = "snps,designware-i2c";
0331 #address-cells = <1>;
0332 #size-cells = <0>;
0333 reg = <0x1800 0x100>;
0334 interrupts = <5>;
0335 clocks = <&chip_clk CLKID_CFG>;
0336 pinctrl-0 = <&twsi1_pmux>;
0337 pinctrl-names = "default";
0338 status = "disabled";
0339 };
0340
0341 timer0: timer@2c00 {
0342 compatible = "snps,dw-apb-timer";
0343 reg = <0x2c00 0x14>;
0344 clocks = <&chip_clk CLKID_CFG>;
0345 clock-names = "timer";
0346 interrupts = <8>;
0347 };
0348
0349 timer1: timer@2c14 {
0350 compatible = "snps,dw-apb-timer";
0351 reg = <0x2c14 0x14>;
0352 clocks = <&chip_clk CLKID_CFG>;
0353 clock-names = "timer";
0354 };
0355
0356 timer2: timer@2c28 {
0357 compatible = "snps,dw-apb-timer";
0358 reg = <0x2c28 0x14>;
0359 clocks = <&chip_clk CLKID_CFG>;
0360 clock-names = "timer";
0361 status = "disabled";
0362 };
0363
0364 timer3: timer@2c3c {
0365 compatible = "snps,dw-apb-timer";
0366 reg = <0x2c3c 0x14>;
0367 clocks = <&chip_clk CLKID_CFG>;
0368 clock-names = "timer";
0369 status = "disabled";
0370 };
0371
0372 timer4: timer@2c50 {
0373 compatible = "snps,dw-apb-timer";
0374 reg = <0x2c50 0x14>;
0375 clocks = <&chip_clk CLKID_CFG>;
0376 clock-names = "timer";
0377 status = "disabled";
0378 };
0379
0380 timer5: timer@2c64 {
0381 compatible = "snps,dw-apb-timer";
0382 reg = <0x2c64 0x14>;
0383 clocks = <&chip_clk CLKID_CFG>;
0384 clock-names = "timer";
0385 status = "disabled";
0386 };
0387
0388 timer6: timer@2c78 {
0389 compatible = "snps,dw-apb-timer";
0390 reg = <0x2c78 0x14>;
0391 clocks = <&chip_clk CLKID_CFG>;
0392 clock-names = "timer";
0393 status = "disabled";
0394 };
0395
0396 timer7: timer@2c8c {
0397 compatible = "snps,dw-apb-timer";
0398 reg = <0x2c8c 0x14>;
0399 clocks = <&chip_clk CLKID_CFG>;
0400 clock-names = "timer";
0401 status = "disabled";
0402 };
0403
0404 aic: interrupt-controller@3800 {
0405 compatible = "snps,dw-apb-ictl";
0406 reg = <0x3800 0x30>;
0407 interrupt-controller;
0408 #interrupt-cells = <1>;
0409 interrupt-parent = <&gic>;
0410 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0411 };
0412 };
0413
0414 chip: chip-control@ea0000 {
0415 compatible = "simple-mfd", "syscon";
0416 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
0417
0418 chip_clk: clock {
0419 compatible = "marvell,berlin2q-clk";
0420 #clock-cells = <1>;
0421 clocks = <&refclk>;
0422 clock-names = "refclk";
0423 };
0424
0425 soc_pinctrl: pin-controller {
0426 compatible = "marvell,berlin2q-soc-pinctrl";
0427
0428 sd1_pmux: sd1-pmux {
0429 groups = "G31";
0430 function = "sd1";
0431 };
0432
0433 twsi0_pmux: twsi0-pmux {
0434 groups = "G6";
0435 function = "twsi0";
0436 };
0437
0438 twsi1_pmux: twsi1-pmux {
0439 groups = "G7";
0440 function = "twsi1";
0441 };
0442 };
0443
0444 chip_rst: reset {
0445 compatible = "marvell,berlin2-reset";
0446 #reset-cells = <2>;
0447 };
0448 };
0449
0450 ahci: sata@e90000 {
0451 compatible = "marvell,berlin2q-ahci", "generic-ahci";
0452 reg = <0xe90000 0x1000>;
0453 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0454 clocks = <&chip_clk CLKID_SATA>;
0455 #address-cells = <1>;
0456 #size-cells = <0>;
0457
0458 sata0: sata-port@0 {
0459 reg = <0>;
0460 phys = <&sata_phy 0>;
0461 status = "disabled";
0462 };
0463
0464 sata1: sata-port@1 {
0465 reg = <1>;
0466 phys = <&sata_phy 1>;
0467 status = "disabled";
0468 };
0469 };
0470
0471 sata_phy: phy@e900a0 {
0472 compatible = "marvell,berlin2q-sata-phy";
0473 reg = <0xe900a0 0x200>;
0474 clocks = <&chip_clk CLKID_SATA>;
0475 #address-cells = <1>;
0476 #size-cells = <0>;
0477 #phy-cells = <1>;
0478 status = "disabled";
0479
0480 sata-phy@0 {
0481 reg = <0>;
0482 };
0483
0484 sata-phy@1 {
0485 reg = <1>;
0486 };
0487 };
0488
0489 usb0: usb@ed0000 {
0490 compatible = "chipidea,usb2";
0491 reg = <0xed0000 0x10000>;
0492 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0493 clocks = <&chip_clk CLKID_USB0>;
0494 phys = <&usb_phy0>;
0495 phy-names = "usb-phy";
0496 status = "disabled";
0497 };
0498
0499 usb1: usb@ee0000 {
0500 compatible = "chipidea,usb2";
0501 reg = <0xee0000 0x10000>;
0502 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&chip_clk CLKID_USB1>;
0504 phys = <&usb_phy1>;
0505 phy-names = "usb-phy";
0506 status = "disabled";
0507 };
0508
0509 pwm: pwm@f20000 {
0510 compatible = "marvell,berlin-pwm";
0511 reg = <0xf20000 0x40>;
0512 clocks = <&chip_clk CLKID_CFG>;
0513 #pwm-cells = <3>;
0514 };
0515
0516 apb@fc0000 {
0517 compatible = "simple-bus";
0518 #address-cells = <1>;
0519 #size-cells = <1>;
0520
0521 ranges = <0 0xfc0000 0x10000>;
0522 interrupt-parent = <&sic>;
0523
0524 wdt0: watchdog@1000 {
0525 compatible = "snps,dw-wdt";
0526 reg = <0x1000 0x100>;
0527 clocks = <&refclk>;
0528 interrupts = <0>;
0529 };
0530
0531 wdt1: watchdog@2000 {
0532 compatible = "snps,dw-wdt";
0533 reg = <0x2000 0x100>;
0534 clocks = <&refclk>;
0535 interrupts = <1>;
0536 };
0537
0538 wdt2: watchdog@3000 {
0539 compatible = "snps,dw-wdt";
0540 reg = <0x3000 0x100>;
0541 clocks = <&refclk>;
0542 interrupts = <2>;
0543 };
0544
0545 sm_gpio1: gpio@5000 {
0546 compatible = "snps,dw-apb-gpio";
0547 reg = <0x5000 0x400>;
0548 #address-cells = <1>;
0549 #size-cells = <0>;
0550
0551 portf: gpio-port@5 {
0552 compatible = "snps,dw-apb-gpio-port";
0553 gpio-controller;
0554 #gpio-cells = <2>;
0555 ngpios = <32>;
0556 reg = <0>;
0557 };
0558 };
0559
0560 i2c2: i2c@7000 {
0561 compatible = "snps,designware-i2c";
0562 #address-cells = <1>;
0563 #size-cells = <0>;
0564 reg = <0x7000 0x100>;
0565 interrupts = <6>;
0566 clocks = <&refclk>;
0567 pinctrl-0 = <&twsi2_pmux>;
0568 pinctrl-names = "default";
0569 status = "disabled";
0570 };
0571
0572 i2c3: i2c@8000 {
0573 compatible = "snps,designware-i2c";
0574 #address-cells = <1>;
0575 #size-cells = <0>;
0576 reg = <0x8000 0x100>;
0577 interrupts = <7>;
0578 clocks = <&refclk>;
0579 pinctrl-0 = <&twsi3_pmux>;
0580 pinctrl-names = "default";
0581 status = "disabled";
0582 };
0583
0584 uart0: uart@9000 {
0585 compatible = "snps,dw-apb-uart";
0586 reg = <0x9000 0x100>;
0587 interrupts = <8>;
0588 clocks = <&refclk>;
0589 reg-shift = <2>;
0590 pinctrl-0 = <&uart0_pmux>;
0591 pinctrl-names = "default";
0592 status = "disabled";
0593 };
0594
0595 uart1: uart@a000 {
0596 compatible = "snps,dw-apb-uart";
0597 reg = <0xa000 0x100>;
0598 interrupts = <9>;
0599 clocks = <&refclk>;
0600 reg-shift = <2>;
0601 pinctrl-0 = <&uart1_pmux>;
0602 pinctrl-names = "default";
0603 status = "disabled";
0604 };
0605
0606 sm_gpio0: gpio@c000 {
0607 compatible = "snps,dw-apb-gpio";
0608 reg = <0xc000 0x400>;
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611
0612 porte: gpio-port@4 {
0613 compatible = "snps,dw-apb-gpio-port";
0614 gpio-controller;
0615 #gpio-cells = <2>;
0616 ngpios = <32>;
0617 reg = <0>;
0618 };
0619 };
0620
0621 sysctrl: pin-controller@d000 {
0622 compatible = "simple-mfd", "syscon";
0623 reg = <0xd000 0x100>;
0624
0625 sys_pinctrl: pin-controller {
0626 compatible = "marvell,berlin2q-system-pinctrl";
0627
0628 uart0_pmux: uart0-pmux {
0629 groups = "GSM12";
0630 function = "uart0";
0631 };
0632
0633 uart1_pmux: uart1-pmux {
0634 groups = "GSM14";
0635 function = "uart1";
0636 };
0637
0638 twsi2_pmux: twsi2-pmux {
0639 groups = "GSM13";
0640 function = "twsi2";
0641 };
0642
0643 twsi3_pmux: twsi3-pmux {
0644 groups = "GSM14";
0645 function = "twsi3";
0646 };
0647 };
0648
0649 adc: adc {
0650 compatible = "marvell,berlin2-adc";
0651 interrupts = <12>, <14>;
0652 interrupt-names = "adc", "tsen";
0653 };
0654 };
0655
0656 sic: interrupt-controller@e000 {
0657 compatible = "snps,dw-apb-ictl";
0658 reg = <0xe000 0x30>;
0659 interrupt-controller;
0660 #interrupt-cells = <1>;
0661 interrupt-parent = <&gic>;
0662 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0663 };
0664 };
0665 };
0666 };
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