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0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
0004 *
0005 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0006 *
0007 * based on GPL'ed 2.6 kernel sources
0008 * (c) Marvell International Ltd.
0009 */
0010
0011 #include <dt-bindings/clock/berlin2.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013
0014 / {
0015 model = "Marvell Armada 1500 (BG2) SoC";
0016 compatible = "marvell,berlin2", "marvell,berlin";
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019
0020 aliases {
0021 serial0 = &uart0;
0022 serial1 = &uart1;
0023 serial2 = &uart2;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029 enable-method = "marvell,berlin-smp";
0030
0031 cpu@0 {
0032 compatible = "marvell,pj4b";
0033 device_type = "cpu";
0034 next-level-cache = <&l2>;
0035 reg = <0>;
0036
0037 clocks = <&chip_clk CLKID_CPU>;
0038 clock-latency = <100000>;
0039 operating-points = <
0040 /* kHz uV */
0041 1200000 1200000
0042 1000000 1200000
0043 800000 1200000
0044 600000 1200000
0045 >;
0046 };
0047
0048 cpu@1 {
0049 compatible = "marvell,pj4b";
0050 device_type = "cpu";
0051 next-level-cache = <&l2>;
0052 reg = <1>;
0053
0054 clocks = <&chip_clk CLKID_CPU>;
0055 clock-latency = <100000>;
0056 operating-points = <
0057 /* kHz uV */
0058 1200000 1200000
0059 1000000 1200000
0060 800000 1200000
0061 600000 1200000
0062 >;
0063 };
0064 };
0065
0066 refclk: oscillator {
0067 compatible = "fixed-clock";
0068 #clock-cells = <0>;
0069 clock-frequency = <25000000>;
0070 };
0071
0072 soc@f7000000 {
0073 compatible = "simple-bus";
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076 interrupt-parent = <&gic>;
0077
0078 ranges = <0 0xf7000000 0x1000000>;
0079
0080 sdhci0: mmc@ab0000 {
0081 compatible = "mrvl,pxav3-mmc";
0082 reg = <0xab0000 0x200>;
0083 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
0084 clock-names = "io", "core";
0085 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0086 status = "disabled";
0087 };
0088
0089 sdhci1: mmc@ab0800 {
0090 compatible = "mrvl,pxav3-mmc";
0091 reg = <0xab0800 0x200>;
0092 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
0093 clock-names = "io", "core";
0094 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0095 status = "disabled";
0096 };
0097
0098 sdhci2: mmc@ab1000 {
0099 compatible = "mrvl,pxav3-mmc";
0100 reg = <0xab1000 0x200>;
0101 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0102 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
0103 clock-names = "io", "core";
0104 pinctrl-0 = <&emmc_pmux>;
0105 pinctrl-names = "default";
0106 status = "disabled";
0107 };
0108
0109 l2: cache-controller@ac0000 {
0110 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
0111 reg = <0xac0000 0x1000>;
0112 cache-unified;
0113 cache-level = <2>;
0114 };
0115
0116 scu: snoop-control-unit@ad0000 {
0117 compatible = "arm,cortex-a9-scu";
0118 reg = <0xad0000 0x58>;
0119 };
0120
0121 gic: interrupt-controller@ad1000 {
0122 compatible = "arm,cortex-a9-gic";
0123 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
0124 interrupt-controller;
0125 #interrupt-cells = <3>;
0126 };
0127
0128 local-timer@ad0600 {
0129 compatible = "arm,cortex-a9-twd-timer";
0130 reg = <0xad0600 0x20>;
0131 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
0132 clocks = <&chip_clk CLKID_TWD>;
0133 };
0134
0135 eth1: ethernet@b90000 {
0136 compatible = "marvell,pxa168-eth";
0137 reg = <0xb90000 0x10000>;
0138 clocks = <&chip_clk CLKID_GETH1>;
0139 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0140 /* set by bootloader */
0141 local-mac-address = [00 00 00 00 00 00];
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144 phy-connection-type = "mii";
0145 phy-handle = <ðphy1>;
0146 status = "disabled";
0147
0148 ethphy1: ethernet-phy@0 {
0149 reg = <0>;
0150 };
0151 };
0152
0153 cpu-ctrl@dd0000 {
0154 compatible = "marvell,berlin-cpu-ctrl";
0155 reg = <0xdd0000 0x10000>;
0156 };
0157
0158 eth0: ethernet@e50000 {
0159 compatible = "marvell,pxa168-eth";
0160 reg = <0xe50000 0x10000>;
0161 clocks = <&chip_clk CLKID_GETH0>;
0162 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0163 /* set by bootloader */
0164 local-mac-address = [00 00 00 00 00 00];
0165 #address-cells = <1>;
0166 #size-cells = <0>;
0167 phy-connection-type = "mii";
0168 phy-handle = <ðphy0>;
0169 status = "disabled";
0170
0171 ethphy0: ethernet-phy@0 {
0172 reg = <0>;
0173 };
0174 };
0175
0176 apb@e80000 {
0177 compatible = "simple-bus";
0178 #address-cells = <1>;
0179 #size-cells = <1>;
0180
0181 ranges = <0 0xe80000 0x10000>;
0182 interrupt-parent = <&aic>;
0183
0184 gpio0: gpio@400 {
0185 compatible = "snps,dw-apb-gpio";
0186 reg = <0x0400 0x400>;
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189
0190 porta: gpio-port@0 {
0191 compatible = "snps,dw-apb-gpio-port";
0192 gpio-controller;
0193 #gpio-cells = <2>;
0194 ngpios = <8>;
0195 reg = <0>;
0196 interrupt-controller;
0197 #interrupt-cells = <2>;
0198 interrupts = <0>;
0199 };
0200 };
0201
0202 gpio1: gpio@800 {
0203 compatible = "snps,dw-apb-gpio";
0204 reg = <0x0800 0x400>;
0205 #address-cells = <1>;
0206 #size-cells = <0>;
0207
0208 portb: gpio-port@1 {
0209 compatible = "snps,dw-apb-gpio-port";
0210 gpio-controller;
0211 #gpio-cells = <2>;
0212 ngpios = <8>;
0213 reg = <0>;
0214 interrupt-controller;
0215 #interrupt-cells = <2>;
0216 interrupts = <1>;
0217 };
0218 };
0219
0220 gpio2: gpio@c00 {
0221 compatible = "snps,dw-apb-gpio";
0222 reg = <0x0c00 0x400>;
0223 #address-cells = <1>;
0224 #size-cells = <0>;
0225
0226 portc: gpio-port@2 {
0227 compatible = "snps,dw-apb-gpio-port";
0228 gpio-controller;
0229 #gpio-cells = <2>;
0230 ngpios = <8>;
0231 reg = <0>;
0232 interrupt-controller;
0233 #interrupt-cells = <2>;
0234 interrupts = <2>;
0235 };
0236 };
0237
0238 gpio3: gpio@1000 {
0239 compatible = "snps,dw-apb-gpio";
0240 reg = <0x1000 0x400>;
0241 #address-cells = <1>;
0242 #size-cells = <0>;
0243
0244 portd: gpio-port@3 {
0245 compatible = "snps,dw-apb-gpio-port";
0246 gpio-controller;
0247 #gpio-cells = <2>;
0248 ngpios = <8>;
0249 reg = <0>;
0250 interrupt-controller;
0251 #interrupt-cells = <2>;
0252 interrupts = <3>;
0253 };
0254 };
0255
0256 timer0: timer@2c00 {
0257 compatible = "snps,dw-apb-timer";
0258 reg = <0x2c00 0x14>;
0259 interrupts = <8>;
0260 clocks = <&chip_clk CLKID_CFG>;
0261 clock-names = "timer";
0262 status = "okay";
0263 };
0264
0265 timer1: timer@2c14 {
0266 compatible = "snps,dw-apb-timer";
0267 reg = <0x2c14 0x14>;
0268 interrupts = <9>;
0269 clocks = <&chip_clk CLKID_CFG>;
0270 clock-names = "timer";
0271 status = "okay";
0272 };
0273
0274 timer2: timer@2c28 {
0275 compatible = "snps,dw-apb-timer";
0276 reg = <0x2c28 0x14>;
0277 interrupts = <10>;
0278 clocks = <&chip_clk CLKID_CFG>;
0279 clock-names = "timer";
0280 status = "disabled";
0281 };
0282
0283 timer3: timer@2c3c {
0284 compatible = "snps,dw-apb-timer";
0285 reg = <0x2c3c 0x14>;
0286 interrupts = <11>;
0287 clocks = <&chip_clk CLKID_CFG>;
0288 clock-names = "timer";
0289 status = "disabled";
0290 };
0291
0292 timer4: timer@2c50 {
0293 compatible = "snps,dw-apb-timer";
0294 reg = <0x2c50 0x14>;
0295 interrupts = <12>;
0296 clocks = <&chip_clk CLKID_CFG>;
0297 clock-names = "timer";
0298 status = "disabled";
0299 };
0300
0301 timer5: timer@2c64 {
0302 compatible = "snps,dw-apb-timer";
0303 reg = <0x2c64 0x14>;
0304 interrupts = <13>;
0305 clocks = <&chip_clk CLKID_CFG>;
0306 clock-names = "timer";
0307 status = "disabled";
0308 };
0309
0310 timer6: timer@2c78 {
0311 compatible = "snps,dw-apb-timer";
0312 reg = <0x2c78 0x14>;
0313 interrupts = <14>;
0314 clocks = <&chip_clk CLKID_CFG>;
0315 clock-names = "timer";
0316 status = "disabled";
0317 };
0318
0319 timer7: timer@2c8c {
0320 compatible = "snps,dw-apb-timer";
0321 reg = <0x2c8c 0x14>;
0322 interrupts = <15>;
0323 clocks = <&chip_clk CLKID_CFG>;
0324 clock-names = "timer";
0325 status = "disabled";
0326 };
0327
0328 aic: interrupt-controller@3000 {
0329 compatible = "snps,dw-apb-ictl";
0330 reg = <0x3000 0xc00>;
0331 interrupt-controller;
0332 #interrupt-cells = <1>;
0333 interrupt-parent = <&gic>;
0334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0335 };
0336 };
0337
0338 ahci: sata@e90000 {
0339 compatible = "marvell,berlin2-ahci", "generic-ahci";
0340 reg = <0xe90000 0x1000>;
0341 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&chip_clk CLKID_SATA>;
0343 #address-cells = <1>;
0344 #size-cells = <0>;
0345
0346 sata0: sata-port@0 {
0347 reg = <0>;
0348 phys = <&sata_phy 0>;
0349 status = "disabled";
0350 };
0351
0352 sata1: sata-port@1 {
0353 reg = <1>;
0354 phys = <&sata_phy 1>;
0355 status = "disabled";
0356 };
0357 };
0358
0359 sata_phy: phy@e900a0 {
0360 compatible = "marvell,berlin2-sata-phy";
0361 reg = <0xe900a0 0x200>;
0362 clocks = <&chip_clk CLKID_SATA>;
0363 #address-cells = <1>;
0364 #size-cells = <0>;
0365 #phy-cells = <1>;
0366 status = "disabled";
0367
0368 sata-phy@0 {
0369 reg = <0>;
0370 };
0371
0372 sata-phy@1 {
0373 reg = <1>;
0374 };
0375 };
0376
0377 chip: chip-control@ea0000 {
0378 compatible = "simple-mfd", "syscon";
0379 reg = <0xea0000 0x400>;
0380
0381 chip_clk: clock {
0382 compatible = "marvell,berlin2-clk";
0383 #clock-cells = <1>;
0384 clocks = <&refclk>;
0385 clock-names = "refclk";
0386 };
0387
0388 soc_pinctrl: pin-controller {
0389 compatible = "marvell,berlin2-soc-pinctrl";
0390
0391 emmc_pmux: emmc-pmux {
0392 groups = "G26";
0393 function = "emmc";
0394 };
0395 };
0396
0397 chip_rst: reset {
0398 compatible = "marvell,berlin2-reset";
0399 #reset-cells = <2>;
0400 };
0401 };
0402
0403 pwm: pwm@f20000 {
0404 compatible = "marvell,berlin-pwm";
0405 reg = <0xf20000 0x40>;
0406 clocks = <&chip_clk CLKID_CFG>;
0407 #pwm-cells = <3>;
0408 };
0409
0410 apb@fc0000 {
0411 compatible = "simple-bus";
0412 #address-cells = <1>;
0413 #size-cells = <1>;
0414
0415 ranges = <0 0xfc0000 0x10000>;
0416 interrupt-parent = <&sic>;
0417
0418 wdt0: watchdog@1000 {
0419 compatible = "snps,dw-wdt";
0420 reg = <0x1000 0x100>;
0421 clocks = <&refclk>;
0422 interrupts = <0>;
0423 };
0424
0425 wdt1: watchdog@2000 {
0426 compatible = "snps,dw-wdt";
0427 reg = <0x2000 0x100>;
0428 clocks = <&refclk>;
0429 interrupts = <1>;
0430 };
0431
0432 wdt2: watchdog@3000 {
0433 compatible = "snps,dw-wdt";
0434 reg = <0x3000 0x100>;
0435 clocks = <&refclk>;
0436 interrupts = <2>;
0437 };
0438
0439 sm_gpio1: gpio@5000 {
0440 compatible = "snps,dw-apb-gpio";
0441 reg = <0x5000 0x400>;
0442 #address-cells = <1>;
0443 #size-cells = <0>;
0444
0445 portf: gpio-port@5 {
0446 compatible = "snps,dw-apb-gpio-port";
0447 gpio-controller;
0448 #gpio-cells = <2>;
0449 ngpios = <8>;
0450 reg = <0>;
0451 };
0452 };
0453
0454 sm_gpio0: gpio@c000 {
0455 compatible = "snps,dw-apb-gpio";
0456 reg = <0xc000 0x400>;
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459
0460 porte: gpio-port@4 {
0461 compatible = "snps,dw-apb-gpio-port";
0462 gpio-controller;
0463 #gpio-cells = <2>;
0464 ngpios = <8>;
0465 reg = <0>;
0466 interrupt-controller;
0467 #interrupt-cells = <2>;
0468 interrupts = <11>;
0469 };
0470 };
0471
0472 uart0: serial@9000 {
0473 compatible = "snps,dw-apb-uart";
0474 reg = <0x9000 0x100>;
0475 reg-shift = <2>;
0476 reg-io-width = <1>;
0477 interrupts = <8>;
0478 clocks = <&refclk>;
0479 pinctrl-0 = <&uart0_pmux>;
0480 pinctrl-names = "default";
0481 status = "disabled";
0482 };
0483
0484 uart1: serial@a000 {
0485 compatible = "snps,dw-apb-uart";
0486 reg = <0xa000 0x100>;
0487 reg-shift = <2>;
0488 reg-io-width = <1>;
0489 interrupts = <9>;
0490 clocks = <&refclk>;
0491 pinctrl-0 = <&uart1_pmux>;
0492 pinctrl-names = "default";
0493 status = "disabled";
0494 };
0495
0496 uart2: serial@b000 {
0497 compatible = "snps,dw-apb-uart";
0498 reg = <0xb000 0x100>;
0499 reg-shift = <2>;
0500 reg-io-width = <1>;
0501 interrupts = <10>;
0502 clocks = <&refclk>;
0503 pinctrl-0 = <&uart2_pmux>;
0504 pinctrl-names = "default";
0505 status = "disabled";
0506 };
0507
0508 sysctrl: system-controller@d000 {
0509 compatible = "simple-mfd", "syscon";
0510 reg = <0xd000 0x100>;
0511
0512 sys_pinctrl: pin-controller {
0513 compatible = "marvell,berlin2-system-pinctrl";
0514 uart0_pmux: uart0-pmux {
0515 groups = "GSM4";
0516 function = "uart0";
0517 };
0518
0519 uart1_pmux: uart1-pmux {
0520 groups = "GSM5";
0521 function = "uart1";
0522 };
0523 uart2_pmux: uart2-pmux {
0524 groups = "GSM3";
0525 function = "uart2";
0526 };
0527 };
0528 };
0529
0530 sic: interrupt-controller@e000 {
0531 compatible = "snps,dw-apb-ictl";
0532 reg = <0xe000 0x400>;
0533 interrupt-controller;
0534 #interrupt-cells = <1>;
0535 interrupt-parent = <&gic>;
0536 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0537 };
0538 };
0539 };
0540 };
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