0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 compatible = "brcm,bcm6878", "brcm,bcmbca";
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 CA7_0: cpu@0 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a7";
0023 reg = <0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 CA7_1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 L2_0: l2-cache0 {
0037 compatible = "cache";
0038 };
0039 };
0040
0041 timer {
0042 compatible = "arm,armv7-timer";
0043 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0044 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0045 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0046 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0047 arm,cpu-registers-not-fw-configured;
0048 };
0049
0050 pmu: pmu {
0051 compatible = "arm,cortex-a7-pmu";
0052 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0053 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0054 interrupt-affinity = <&CA7_0>, <&CA7_1>;
0055 };
0056
0057 clocks: clocks {
0058 periph_clk: periph-clk {
0059 compatible = "fixed-clock";
0060 #clock-cells = <0>;
0061 clock-frequency = <200000000>;
0062 };
0063 uart_clk: uart-clk {
0064 compatible = "fixed-factor-clock";
0065 #clock-cells = <0>;
0066 clocks = <&periph_clk>;
0067 clock-div = <4>;
0068 clock-mult = <1>;
0069 };
0070 };
0071
0072 psci {
0073 compatible = "arm,psci-0.2";
0074 method = "smc";
0075 };
0076
0077 axi@81000000 {
0078 compatible = "simple-bus";
0079 #address-cells = <1>;
0080 #size-cells = <1>;
0081 ranges = <0 0x81000000 0x8000>;
0082
0083 gic: interrupt-controller@1000 {
0084 compatible = "arm,cortex-a7-gic";
0085 #interrupt-cells = <3>;
0086 interrupt-controller;
0087 reg = <0x1000 0x1000>,
0088 <0x2000 0x2000>,
0089 <0x4000 0x2000>,
0090 <0x6000 0x2000>;
0091 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
0092 IRQ_TYPE_LEVEL_HIGH)>;
0093 };
0094 };
0095
0096 bus@ff800000 {
0097 compatible = "simple-bus";
0098 #address-cells = <1>;
0099 #size-cells = <1>;
0100 ranges = <0 0xff800000 0x800000>;
0101
0102 uart0: serial@12000 {
0103 compatible = "arm,pl011", "arm,primecell";
0104 reg = <0x12000 0x1000>;
0105 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0106 clocks = <&uart_clk>, <&uart_clk>;
0107 clock-names = "uartclk", "apb_pclk";
0108 status = "disabled";
0109 };
0110 };
0111 };
