0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 compatible = "brcm,bcm6855", "brcm,bcmbca";
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 CA7_0: cpu@0 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a7";
0023 reg = <0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 CA7_1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 CA7_2: cpu@2 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a7";
0039 reg = <0x2>;
0040 next-level-cache = <&L2_0>;
0041 enable-method = "psci";
0042 };
0043
0044 L2_0: l2-cache0 {
0045 compatible = "cache";
0046 };
0047 };
0048
0049 timer {
0050 compatible = "arm,armv7-timer";
0051 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
0052 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
0053 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
0054 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
0055 arm,cpu-registers-not-fw-configured;
0056 };
0057
0058 pmu: pmu {
0059 compatible = "arm,cortex-a7-pmu";
0060 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0061 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0062 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0063 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
0064 };
0065
0066 clocks: clocks {
0067 periph_clk: periph-clk {
0068 compatible = "fixed-clock";
0069 #clock-cells = <0>;
0070 clock-frequency = <200000000>;
0071 };
0072
0073 uart_clk: uart-clk {
0074 compatible = "fixed-factor-clock";
0075 #clock-cells = <0>;
0076 clocks = <&periph_clk>;
0077 clock-div = <4>;
0078 clock-mult = <1>;
0079 };
0080 };
0081
0082 psci {
0083 compatible = "arm,psci-0.2";
0084 method = "smc";
0085 };
0086
0087 axi@81000000 {
0088 compatible = "simple-bus";
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 ranges = <0 0x81000000 0x8000>;
0092
0093 gic: interrupt-controller@1000 {
0094 compatible = "arm,cortex-a7-gic";
0095 #interrupt-cells = <3>;
0096 interrupt-controller;
0097 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
0098 reg = <0x1000 0x1000>,
0099 <0x2000 0x2000>,
0100 <0x4000 0x2000>,
0101 <0x6000 0x2000>;
0102 };
0103 };
0104
0105 bus@ff800000 {
0106 compatible = "simple-bus";
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 ranges = <0 0xff800000 0x800000>;
0110
0111 uart0: serial@12000 {
0112 compatible = "arm,pl011", "arm,primecell";
0113 reg = <0x12000 0x1000>;
0114 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0115 clocks = <&uart_clk>, <&uart_clk>;
0116 clock-names = "uartclk", "apb_pclk";
0117 status = "disabled";
0118 };
0119 };
0120 };
