0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 compatible = "brcm,bcm6756", "brcm,bcmbca";
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 CA7_0: cpu@0 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a7";
0023 reg = <0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 CA7_1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 CA7_2: cpu@2 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a7";
0039 reg = <0x2>;
0040 next-level-cache = <&L2_0>;
0041 enable-method = "psci";
0042 };
0043
0044 CA7_3: cpu@3 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a7";
0047 reg = <0x3>;
0048 next-level-cache = <&L2_0>;
0049 enable-method = "psci";
0050 };
0051
0052 L2_0: l2-cache0 {
0053 compatible = "cache";
0054 };
0055 };
0056
0057 timer {
0058 compatible = "arm,armv7-timer";
0059 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0060 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0061 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0062 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0063 arm,cpu-registers-not-fw-configured;
0064 };
0065
0066 pmu: pmu {
0067 compatible = "arm,cortex-a7-pmu";
0068 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0070 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0072 interrupt-affinity = <&CA7_0>, <&CA7_1>,
0073 <&CA7_2>, <&CA7_3>;
0074 };
0075
0076 clocks: clocks {
0077 periph_clk: periph-clk {
0078 compatible = "fixed-clock";
0079 #clock-cells = <0>;
0080 clock-frequency = <200000000>;
0081 };
0082
0083 uart_clk: uart-clk {
0084 compatible = "fixed-factor-clock";
0085 #clock-cells = <0>;
0086 clocks = <&periph_clk>;
0087 clock-div = <4>;
0088 clock-mult = <1>;
0089 };
0090 };
0091
0092 psci {
0093 compatible = "arm,psci-0.2";
0094 method = "smc";
0095 };
0096
0097 axi@81000000 {
0098 compatible = "simple-bus";
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 ranges = <0 0x81000000 0x8000>;
0102
0103 gic: interrupt-controller@1000 {
0104 compatible = "arm,cortex-a7-gic";
0105 #interrupt-cells = <3>;
0106 interrupt-controller;
0107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0108 reg = <0x1000 0x1000>,
0109 <0x2000 0x2000>,
0110 <0x4000 0x2000>,
0111 <0x6000 0x2000>;
0112 };
0113 };
0114
0115 bus@ff800000 {
0116 compatible = "simple-bus";
0117 #address-cells = <1>;
0118 #size-cells = <1>;
0119 ranges = <0 0xff800000 0x800000>;
0120
0121 uart0: serial@12000 {
0122 compatible = "arm,pl011", "arm,primecell";
0123 reg = <0x12000 0x1000>;
0124 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0125 clocks = <&uart_clk>, <&uart_clk>;
0126 clock-names = "uartclk", "apb_pclk";
0127 status = "disabled";
0128 };
0129 };
0130 };
