0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Broadcom BCM63138 DSL SoCs Device Tree
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 compatible = "brcm,bcm63138", "brcm,bcmbca";
0013 model = "Broadcom BCM963138 Reference Board";
0014 interrupt-parent = <&gic>;
0015
0016 aliases {
0017 uart0 = &serial0;
0018 uart1 = &serial1;
0019 };
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu@0 {
0026 device_type = "cpu";
0027 compatible = "arm,cortex-a9";
0028 next-level-cache = <&L2>;
0029 reg = <0>;
0030 enable-method = "brcm,bcm63138";
0031 };
0032
0033 cpu@1 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a9";
0036 next-level-cache = <&L2>;
0037 reg = <1>;
0038 enable-method = "brcm,bcm63138";
0039 resets = <&pmb0 4 1>;
0040 };
0041 };
0042
0043 clocks {
0044 /* UBUS peripheral clock */
0045 periph_clk: periph_clk {
0046 #clock-cells = <0>;
0047 compatible = "fixed-clock";
0048 clock-frequency = <50000000>;
0049 clock-output-names = "periph";
0050 };
0051
0052 /* peripheral clock for system timer */
0053 axi_clk: axi_clk {
0054 #clock-cells = <0>;
0055 compatible = "fixed-factor-clock";
0056 clocks = <&armpll>;
0057 clock-div = <2>;
0058 clock-mult = <1>;
0059 };
0060
0061 /* APB bus clock */
0062 apb_clk: apb_clk {
0063 #clock-cells = <0>;
0064 compatible = "fixed-factor-clock";
0065 clocks = <&armpll>;
0066 clock-div = <4>;
0067 clock-mult = <1>;
0068 };
0069 };
0070
0071 /* ARM bus */
0072 axi@80000000 {
0073 compatible = "simple-bus";
0074 ranges = <0 0x80000000 0x784000>;
0075 #address-cells = <1>;
0076 #size-cells = <1>;
0077
0078 L2: cache-controller@1d000 {
0079 compatible = "arm,pl310-cache";
0080 reg = <0x1d000 0x1000>;
0081 cache-unified;
0082 cache-level = <2>;
0083 cache-size = <524288>;
0084 cache-sets = <1024>;
0085 cache-line-size = <32>;
0086 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
0087 };
0088
0089 scu: scu@1e000 {
0090 compatible = "arm,cortex-a9-scu";
0091 reg = <0x1e000 0x100>;
0092 };
0093
0094 gic: interrupt-controller@1f000 {
0095 compatible = "arm,cortex-a9-gic";
0096 reg = <0x1f000 0x1000
0097 0x1e100 0x100>;
0098 #interrupt-cells = <3>;
0099 #address-cells = <0>;
0100 interrupt-controller;
0101 };
0102
0103 global_timer: timer@1e200 {
0104 compatible = "arm,cortex-a9-global-timer";
0105 reg = <0x1e200 0x20>;
0106 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
0107 clocks = <&axi_clk>;
0108 };
0109
0110 local_timer: local-timer@1e600 {
0111 compatible = "arm,cortex-a9-twd-timer";
0112 reg = <0x1e600 0x20>;
0113 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
0114 IRQ_TYPE_EDGE_RISING)>;
0115 clocks = <&axi_clk>;
0116 };
0117
0118 twd_watchdog: watchdog@1e620 {
0119 compatible = "arm,cortex-a9-twd-wdt";
0120 reg = <0x1e620 0x20>;
0121 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
0122 IRQ_TYPE_LEVEL_HIGH)>;
0123 };
0124
0125 armpll: armpll@20000 {
0126 #clock-cells = <0>;
0127 compatible = "brcm,bcm63138-armpll";
0128 clocks = <&periph_clk>;
0129 reg = <0x20000 0xf00>;
0130 };
0131
0132 pmb0: reset-controller@4800c0 {
0133 compatible = "brcm,bcm63138-pmb";
0134 reg = <0x4800c0 0x10>;
0135 #reset-cells = <2>;
0136 };
0137
0138 pmb1: reset-controller@4800e0 {
0139 compatible = "brcm,bcm63138-pmb";
0140 reg = <0x4800e0 0x10>;
0141 #reset-cells = <2>;
0142 };
0143
0144 ahci: sata@a000 {
0145 compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
0146 reg-names = "ahci", "top-ctrl";
0147 reg = <0xa000 0x9ac>, <0x8040 0x24>;
0148 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0149 #address-cells = <1>;
0150 #size-cells = <0>;
0151 resets = <&pmb0 3 1>;
0152 reset-names = "ahci";
0153 status = "disabled";
0154
0155 sata0: sata-port@0 {
0156 reg = <0>;
0157 phys = <&sata_phy0>;
0158 };
0159 };
0160
0161 sata_phy: sata-phy@8100 {
0162 compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
0163 reg = <0x8100 0x1e00>;
0164 reg-names = "phy";
0165 #address-cells = <1>;
0166 #size-cells = <0>;
0167 status = "disabled";
0168
0169 sata_phy0: sata-phy@0 {
0170 reg = <0>;
0171 #phy-cells = <0>;
0172 };
0173 };
0174 };
0175
0176 /* Legacy UBUS base */
0177 ubus@fffe8000 {
0178 compatible = "simple-bus";
0179 #address-cells = <1>;
0180 #size-cells = <1>;
0181 ranges = <0 0xfffe8000 0x8100>;
0182
0183 timer: timer@80 {
0184 compatible = "brcm,bcm6328-timer", "syscon";
0185 reg = <0x80 0x3c>;
0186 };
0187
0188 serial0: serial@600 {
0189 compatible = "brcm,bcm6345-uart";
0190 reg = <0x600 0x1b>;
0191 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0192 clocks = <&periph_clk>;
0193 clock-names = "periph";
0194 status = "disabled";
0195 };
0196
0197 serial1: serial@620 {
0198 compatible = "brcm,bcm6345-uart";
0199 reg = <0x620 0x1b>;
0200 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0201 clocks = <&periph_clk>;
0202 clock-names = "periph";
0203 status = "disabled";
0204 };
0205
0206 nand_controller: nand-controller@2000 {
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
0210 reg = <0x2000 0x600>, <0xf0 0x10>;
0211 reg-names = "nand", "nand-int-base";
0212 status = "disabled";
0213 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0214 interrupt-names = "nand";
0215 };
0216
0217 bootlut: bootlut@8000 {
0218 compatible = "brcm,bcm63138-bootlut";
0219 reg = <0x8000 0x50>;
0220 };
0221
0222 reboot {
0223 compatible = "syscon-reboot";
0224 regmap = <&timer>;
0225 offset = <0x34>;
0226 mask = <1>;
0227 };
0228 };
0229 };
