0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/input.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 interrupt-parent = <&gic>;
0015
0016 aliases {
0017 serial0 = &uart0;
0018 };
0019
0020 chosen {
0021 stdout-path = "serial0:115200n8";
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu@0 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0x0>;
0032 };
0033 };
0034
0035 mpcore@18310000 {
0036 compatible = "simple-bus";
0037 ranges = <0x00000000 0x18310000 0x00008000>;
0038 #address-cells = <1>;
0039 #size-cells = <1>;
0040
0041 gic: interrupt-controller@1000 {
0042 compatible = "arm,cortex-a7-gic";
0043 #interrupt-cells = <3>;
0044 #address-cells = <0>;
0045 interrupt-controller;
0046 reg = <0x1000 0x1000>,
0047 <0x2000 0x0100>;
0048 };
0049 };
0050
0051 timer {
0052 compatible = "arm,armv7-timer";
0053 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0054 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0055 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0056 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0057 };
0058
0059 clocks {
0060 #address-cells = <1>;
0061 #size-cells = <1>;
0062 ranges;
0063
0064 alp: oscillator {
0065 #clock-cells = <0>;
0066 compatible = "fixed-clock";
0067 clock-frequency = <40000000>;
0068 };
0069 };
0070
0071 axi@18000000 {
0072 compatible = "brcm,bus-axi";
0073 reg = <0x18000000 0x1000>;
0074 ranges = <0x00000000 0x18000000 0x00100000>;
0075 #address-cells = <1>;
0076 #size-cells = <1>;
0077
0078 #interrupt-cells = <1>;
0079 interrupt-map-mask = <0x000fffff 0xffff>;
0080 interrupt-map =
0081 /* ChipCommon */
0082 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0083
0084 /* IEEE 802.11 0 */
0085 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0086
0087 /* PCIe Controller 0 */
0088 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0089 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0090 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0091 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0092 <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0093 <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0094
0095 /* USB 2.0 Controller */
0096 <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0097
0098 /* Ethernet Controller 0 */
0099 <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0100
0101 /* IEEE 802.11 1 */
0102 <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0103
0104 /* Ethernet Controller 1 */
0105 <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0106
0107 chipcommon: chipcommon@0 {
0108 compatible = "simple-bus";
0109 reg = <0x00000000 0x1000>;
0110 ranges;
0111
0112 #address-cells = <1>;
0113 #size-cells = <1>;
0114
0115 gpio-controller;
0116 #gpio-cells = <2>;
0117
0118 uart0: serial@300 {
0119 compatible = "ns16550a";
0120 reg = <0x0300 0x100>;
0121 interrupt-parent = <&gic>;
0122 interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
0123 clocks = <&alp>;
0124 status = "okay";
0125 };
0126 };
0127
0128 pcie0: pcie@2000 {
0129 reg = <0x00002000 0x1000>;
0130 };
0131
0132 usb2: usb2@4000 {
0133 reg = <0x4000 0x1000>;
0134 ranges;
0135 #address-cells = <1>;
0136 #size-cells = <1>;
0137
0138 ehci: usb@4000 {
0139 compatible = "generic-ehci";
0140 reg = <0x4000 0x1000>;
0141 interrupt-parent = <&gic>;
0142 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0143
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146
0147 ehci_port1: port@1 {
0148 reg = <1>;
0149 #trigger-source-cells = <0>;
0150 };
0151
0152 ehci_port2: port@2 {
0153 reg = <2>;
0154 #trigger-source-cells = <0>;
0155 };
0156 };
0157
0158 ohci: usb@d000 {
0159 #usb-cells = <0>;
0160
0161 compatible = "generic-ohci";
0162 reg = <0xd000 0x1000>;
0163 interrupt-parent = <&gic>;
0164 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0165
0166 #address-cells = <1>;
0167 #size-cells = <0>;
0168
0169 ohci_port1: port@1 {
0170 reg = <1>;
0171 #trigger-source-cells = <0>;
0172 };
0173
0174 ohci_port2: port@2 {
0175 reg = <2>;
0176 #trigger-source-cells = <0>;
0177 };
0178 };
0179 };
0180
0181 gmac0: ethernet@5000 {
0182 reg = <0x5000 0x1000>;
0183
0184 mdio {
0185 #address-cells = <1>;
0186 #size-cells = <0>;
0187
0188 switch: switch@1e {
0189 compatible = "brcm,bcm53125";
0190 reg = <0x1e>;
0191
0192 status = "disabled";
0193
0194 /* ports are defined in board DTS */
0195 ports {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198 };
0199 };
0200 };
0201 };
0202
0203 gmac1: ethernet@b000 {
0204 reg = <0xb000 0x1000>;
0205 };
0206
0207 pmu@12000 {
0208 compatible = "simple-mfd", "syscon";
0209 reg = <0x00012000 0x00001000>;
0210
0211 ilp: ilp {
0212 compatible = "brcm,bcm53573-ilp";
0213 clocks = <&alp>;
0214 #clock-cells = <0>;
0215 clock-output-names = "ilp";
0216 };
0217 };
0218 };
0219 };
