0001 #include <dt-bindings/pinctrl/bcm2835.h>
0002 #include <dt-bindings/clock/bcm2835.h>
0003 #include <dt-bindings/clock/bcm2835-aux.h>
0004 #include <dt-bindings/gpio/gpio.h>
0005 #include <dt-bindings/interrupt-controller/irq.h>
0006 #include <dt-bindings/soc/bcm2835-pm.h>
0007
0008 /* firmware-provided startup stubs live here, where the secondary CPUs are
0009 * spinning.
0010 */
0011 /memreserve/ 0x00000000 0x00001000;
0012
0013 /* This include file covers the common peripherals and configuration between
0014 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
0015 * bcm2835.dtsi and bcm2836.dtsi.
0016 */
0017
0018 / {
0019 compatible = "brcm,bcm2835";
0020 model = "BCM2835";
0021 #address-cells = <1>;
0022 #size-cells = <1>;
0023
0024 aliases {
0025 serial0 = &uart0;
0026 serial1 = &uart1;
0027 };
0028
0029 chosen {
0030 stdout-path = "serial0:115200n8";
0031 };
0032
0033 rmem: reserved-memory {
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 ranges;
0037
0038 cma: linux,cma {
0039 compatible = "shared-dma-pool";
0040 size = <0x4000000>; /* 64MB */
0041 reusable;
0042 linux,cma-default;
0043 };
0044 };
0045
0046 thermal-zones {
0047 cpu_thermal: cpu-thermal {
0048 polling-delay-passive = <0>;
0049 polling-delay = <1000>;
0050
0051 trips {
0052 cpu-crit {
0053 temperature = <90000>;
0054 hysteresis = <0>;
0055 type = "critical";
0056 };
0057 };
0058
0059 cooling-maps {
0060 };
0061 };
0062 };
0063
0064 soc {
0065 compatible = "simple-bus";
0066 #address-cells = <1>;
0067 #size-cells = <1>;
0068
0069 system_timer: timer@7e003000 {
0070 compatible = "brcm,bcm2835-system-timer";
0071 reg = <0x7e003000 0x1000>;
0072 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
0073 /* This could be a reference to BCM2835_CLOCK_TIMER,
0074 * but we don't have the driver using the common clock
0075 * support yet.
0076 */
0077 clock-frequency = <1000000>;
0078 };
0079
0080 txp: txp@7e004000 {
0081 compatible = "brcm,bcm2835-txp";
0082 reg = <0x7e004000 0x20>;
0083 interrupts = <1 11>;
0084 };
0085
0086 clocks: cprman@7e101000 {
0087 compatible = "brcm,bcm2835-cprman";
0088 #clock-cells = <1>;
0089 reg = <0x7e101000 0x2000>;
0090
0091 /* CPRMAN derives almost everything from the
0092 * platform's oscillator. However, the DSI
0093 * pixel clocks come from the DSI analog PHY.
0094 */
0095 clocks = <&clk_osc>,
0096 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
0097 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
0098 };
0099
0100 mailbox: mailbox@7e00b880 {
0101 compatible = "brcm,bcm2835-mbox";
0102 reg = <0x7e00b880 0x40>;
0103 interrupts = <0 1>;
0104 #mbox-cells = <0>;
0105 };
0106
0107 gpio: gpio@7e200000 {
0108 compatible = "brcm,bcm2835-gpio";
0109 reg = <0x7e200000 0xb4>;
0110 /*
0111 * The GPIO IP block is designed for 3 banks of GPIOs.
0112 * Each bank has a GPIO interrupt for itself.
0113 * There is an overall "any bank" interrupt.
0114 * In order, these are GIC interrupts 17, 18, 19, 20.
0115 * Since the BCM2835 only has 2 banks, the 2nd bank
0116 * interrupt output appears to be mirrored onto the
0117 * 3rd bank's interrupt signal.
0118 * So, a bank0 interrupt shows up on 17, 20, and
0119 * a bank1 interrupt shows up on 18, 19, 20!
0120 */
0121 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
0122
0123 gpio-controller;
0124 #gpio-cells = <2>;
0125
0126 interrupt-controller;
0127 #interrupt-cells = <2>;
0128
0129 gpio-ranges = <&gpio 0 0 54>;
0130
0131 /* Defines common pin muxing groups
0132 *
0133 * While each pin can have its mux selected
0134 * for various functions individually, some
0135 * groups only make sense to switch to a
0136 * particular function together.
0137 */
0138 dpi_gpio0: dpi_gpio0 {
0139 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
0140 12 13 14 15 16 17 18 19
0141 20 21 22 23 24 25 26 27>;
0142 brcm,function = <BCM2835_FSEL_ALT2>;
0143 };
0144 emmc_gpio22: emmc_gpio22 {
0145 brcm,pins = <22 23 24 25 26 27>;
0146 brcm,function = <BCM2835_FSEL_ALT3>;
0147 };
0148 emmc_gpio34: emmc_gpio34 {
0149 brcm,pins = <34 35 36 37 38 39>;
0150 brcm,function = <BCM2835_FSEL_ALT3>;
0151 brcm,pull = <BCM2835_PUD_OFF
0152 BCM2835_PUD_UP
0153 BCM2835_PUD_UP
0154 BCM2835_PUD_UP
0155 BCM2835_PUD_UP
0156 BCM2835_PUD_UP>;
0157 };
0158 emmc_gpio48: emmc_gpio48 {
0159 brcm,pins = <48 49 50 51 52 53>;
0160 brcm,function = <BCM2835_FSEL_ALT3>;
0161 };
0162
0163 gpclk0_gpio4: gpclk0_gpio4 {
0164 brcm,pins = <4>;
0165 brcm,function = <BCM2835_FSEL_ALT0>;
0166 };
0167 gpclk1_gpio5: gpclk1_gpio5 {
0168 brcm,pins = <5>;
0169 brcm,function = <BCM2835_FSEL_ALT0>;
0170 };
0171 gpclk1_gpio42: gpclk1_gpio42 {
0172 brcm,pins = <42>;
0173 brcm,function = <BCM2835_FSEL_ALT0>;
0174 };
0175 gpclk1_gpio44: gpclk1_gpio44 {
0176 brcm,pins = <44>;
0177 brcm,function = <BCM2835_FSEL_ALT0>;
0178 };
0179 gpclk2_gpio6: gpclk2_gpio6 {
0180 brcm,pins = <6>;
0181 brcm,function = <BCM2835_FSEL_ALT0>;
0182 };
0183 gpclk2_gpio43: gpclk2_gpio43 {
0184 brcm,pins = <43>;
0185 brcm,function = <BCM2835_FSEL_ALT0>;
0186 brcm,pull = <BCM2835_PUD_OFF>;
0187 };
0188
0189 i2c0_gpio0: i2c0_gpio0 {
0190 brcm,pins = <0 1>;
0191 brcm,function = <BCM2835_FSEL_ALT0>;
0192 };
0193 i2c0_gpio28: i2c0_gpio28 {
0194 brcm,pins = <28 29>;
0195 brcm,function = <BCM2835_FSEL_ALT0>;
0196 };
0197 i2c0_gpio44: i2c0_gpio44 {
0198 brcm,pins = <44 45>;
0199 brcm,function = <BCM2835_FSEL_ALT1>;
0200 };
0201 i2c1_gpio2: i2c1_gpio2 {
0202 brcm,pins = <2 3>;
0203 brcm,function = <BCM2835_FSEL_ALT0>;
0204 };
0205 i2c1_gpio44: i2c1_gpio44 {
0206 brcm,pins = <44 45>;
0207 brcm,function = <BCM2835_FSEL_ALT2>;
0208 };
0209
0210 jtag_gpio22: jtag_gpio22 {
0211 brcm,pins = <22 23 24 25 26 27>;
0212 brcm,function = <BCM2835_FSEL_ALT4>;
0213 };
0214
0215 pcm_gpio18: pcm_gpio18 {
0216 brcm,pins = <18 19 20 21>;
0217 brcm,function = <BCM2835_FSEL_ALT0>;
0218 };
0219 pcm_gpio28: pcm_gpio28 {
0220 brcm,pins = <28 29 30 31>;
0221 brcm,function = <BCM2835_FSEL_ALT2>;
0222 };
0223
0224 sdhost_gpio48: sdhost_gpio48 {
0225 brcm,pins = <48 49 50 51 52 53>;
0226 brcm,function = <BCM2835_FSEL_ALT0>;
0227 };
0228
0229 spi0_gpio7: spi0_gpio7 {
0230 brcm,pins = <7 8 9 10 11>;
0231 brcm,function = <BCM2835_FSEL_ALT0>;
0232 };
0233 spi0_gpio35: spi0_gpio35 {
0234 brcm,pins = <35 36 37 38 39>;
0235 brcm,function = <BCM2835_FSEL_ALT0>;
0236 };
0237 spi1_gpio16: spi1_gpio16 {
0238 brcm,pins = <16 17 18 19 20 21>;
0239 brcm,function = <BCM2835_FSEL_ALT4>;
0240 };
0241 spi2_gpio40: spi2_gpio40 {
0242 brcm,pins = <40 41 42 43 44 45>;
0243 brcm,function = <BCM2835_FSEL_ALT4>;
0244 };
0245
0246 uart0_gpio14: uart0_gpio14 {
0247 brcm,pins = <14 15>;
0248 brcm,function = <BCM2835_FSEL_ALT0>;
0249 };
0250 /* Separate from the uart0_gpio14 group
0251 * because it conflicts with spi1_gpio16, and
0252 * people often run uart0 on the two pins
0253 * without flow control.
0254 */
0255 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
0256 brcm,pins = <16 17>;
0257 brcm,function = <BCM2835_FSEL_ALT3>;
0258 };
0259 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
0260 brcm,pins = <30 31>;
0261 brcm,function = <BCM2835_FSEL_ALT3>;
0262 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
0263 };
0264 uart0_gpio32: uart0_gpio32 {
0265 brcm,pins = <32 33>;
0266 brcm,function = <BCM2835_FSEL_ALT3>;
0267 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
0268 };
0269 uart0_gpio36: uart0_gpio36 {
0270 brcm,pins = <36 37>;
0271 brcm,function = <BCM2835_FSEL_ALT2>;
0272 };
0273 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
0274 brcm,pins = <38 39>;
0275 brcm,function = <BCM2835_FSEL_ALT2>;
0276 };
0277
0278 uart1_gpio14: uart1_gpio14 {
0279 brcm,pins = <14 15>;
0280 brcm,function = <BCM2835_FSEL_ALT5>;
0281 };
0282 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
0283 brcm,pins = <16 17>;
0284 brcm,function = <BCM2835_FSEL_ALT5>;
0285 };
0286 uart1_gpio32: uart1_gpio32 {
0287 brcm,pins = <32 33>;
0288 brcm,function = <BCM2835_FSEL_ALT5>;
0289 };
0290 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
0291 brcm,pins = <30 31>;
0292 brcm,function = <BCM2835_FSEL_ALT5>;
0293 };
0294 uart1_gpio40: uart1_gpio40 {
0295 brcm,pins = <40 41>;
0296 brcm,function = <BCM2835_FSEL_ALT5>;
0297 };
0298 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
0299 brcm,pins = <42 43>;
0300 brcm,function = <BCM2835_FSEL_ALT5>;
0301 };
0302 };
0303
0304 uart0: serial@7e201000 {
0305 compatible = "arm,pl011", "arm,primecell";
0306 reg = <0x7e201000 0x200>;
0307 interrupts = <2 25>;
0308 clocks = <&clocks BCM2835_CLOCK_UART>,
0309 <&clocks BCM2835_CLOCK_VPU>;
0310 clock-names = "uartclk", "apb_pclk";
0311 arm,primecell-periphid = <0x00241011>;
0312 };
0313
0314 sdhost: mmc@7e202000 {
0315 compatible = "brcm,bcm2835-sdhost";
0316 reg = <0x7e202000 0x100>;
0317 interrupts = <2 24>;
0318 clocks = <&clocks BCM2835_CLOCK_VPU>;
0319 status = "disabled";
0320 };
0321
0322 i2s: i2s@7e203000 {
0323 compatible = "brcm,bcm2835-i2s";
0324 reg = <0x7e203000 0x24>;
0325 clocks = <&clocks BCM2835_CLOCK_PCM>;
0326 status = "disabled";
0327 };
0328
0329 spi: spi@7e204000 {
0330 compatible = "brcm,bcm2835-spi";
0331 reg = <0x7e204000 0x200>;
0332 interrupts = <2 22>;
0333 clocks = <&clocks BCM2835_CLOCK_VPU>;
0334 #address-cells = <1>;
0335 #size-cells = <0>;
0336 status = "disabled";
0337 };
0338
0339 i2c0: i2c@7e205000 {
0340 compatible = "brcm,bcm2835-i2c";
0341 reg = <0x7e205000 0x200>;
0342 interrupts = <2 21>;
0343 clocks = <&clocks BCM2835_CLOCK_VPU>;
0344 #address-cells = <1>;
0345 #size-cells = <0>;
0346 status = "disabled";
0347 };
0348
0349 dpi: dpi@7e208000 {
0350 compatible = "brcm,bcm2835-dpi";
0351 reg = <0x7e208000 0x8c>;
0352 clocks = <&clocks BCM2835_CLOCK_VPU>,
0353 <&clocks BCM2835_CLOCK_DPI>;
0354 clock-names = "core", "pixel";
0355 status = "disabled";
0356 };
0357
0358 dsi0: dsi@7e209000 {
0359 compatible = "brcm,bcm2835-dsi0";
0360 reg = <0x7e209000 0x78>;
0361 interrupts = <2 4>;
0362 #address-cells = <1>;
0363 #size-cells = <0>;
0364 #clock-cells = <1>;
0365
0366 clocks = <&clocks BCM2835_PLLA_DSI0>,
0367 <&clocks BCM2835_CLOCK_DSI0E>,
0368 <&clocks BCM2835_CLOCK_DSI0P>;
0369 clock-names = "phy", "escape", "pixel";
0370
0371 clock-output-names = "dsi0_byte",
0372 "dsi0_ddr2",
0373 "dsi0_ddr";
0374
0375 status = "disabled";
0376 };
0377
0378 aux: aux@7e215000 {
0379 compatible = "brcm,bcm2835-aux";
0380 #clock-cells = <1>;
0381 reg = <0x7e215000 0x8>;
0382 clocks = <&clocks BCM2835_CLOCK_VPU>;
0383 };
0384
0385 uart1: serial@7e215040 {
0386 compatible = "brcm,bcm2835-aux-uart";
0387 reg = <0x7e215040 0x40>;
0388 interrupts = <1 29>;
0389 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
0390 status = "disabled";
0391 };
0392
0393 spi1: spi@7e215080 {
0394 compatible = "brcm,bcm2835-aux-spi";
0395 reg = <0x7e215080 0x40>;
0396 interrupts = <1 29>;
0397 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
0398 #address-cells = <1>;
0399 #size-cells = <0>;
0400 status = "disabled";
0401 };
0402
0403 spi2: spi@7e2150c0 {
0404 compatible = "brcm,bcm2835-aux-spi";
0405 reg = <0x7e2150c0 0x40>;
0406 interrupts = <1 29>;
0407 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410 status = "disabled";
0411 };
0412
0413 pwm: pwm@7e20c000 {
0414 compatible = "brcm,bcm2835-pwm";
0415 reg = <0x7e20c000 0x28>;
0416 clocks = <&clocks BCM2835_CLOCK_PWM>;
0417 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
0418 assigned-clock-rates = <10000000>;
0419 #pwm-cells = <2>;
0420 status = "disabled";
0421 };
0422
0423 sdhci: mmc@7e300000 {
0424 compatible = "brcm,bcm2835-sdhci";
0425 reg = <0x7e300000 0x100>;
0426 interrupts = <2 30>;
0427 clocks = <&clocks BCM2835_CLOCK_EMMC>;
0428 status = "disabled";
0429 };
0430
0431 hvs@7e400000 {
0432 compatible = "brcm,bcm2835-hvs";
0433 reg = <0x7e400000 0x6000>;
0434 interrupts = <2 1>;
0435 };
0436
0437 dsi1: dsi@7e700000 {
0438 compatible = "brcm,bcm2835-dsi1";
0439 reg = <0x7e700000 0x8c>;
0440 interrupts = <2 12>;
0441 #address-cells = <1>;
0442 #size-cells = <0>;
0443 #clock-cells = <1>;
0444
0445 clocks = <&clocks BCM2835_PLLD_DSI1>,
0446 <&clocks BCM2835_CLOCK_DSI1E>,
0447 <&clocks BCM2835_CLOCK_DSI1P>;
0448 clock-names = "phy", "escape", "pixel";
0449
0450 clock-output-names = "dsi1_byte",
0451 "dsi1_ddr2",
0452 "dsi1_ddr";
0453
0454 status = "disabled";
0455 };
0456
0457 i2c1: i2c@7e804000 {
0458 compatible = "brcm,bcm2835-i2c";
0459 reg = <0x7e804000 0x1000>;
0460 interrupts = <2 21>;
0461 clocks = <&clocks BCM2835_CLOCK_VPU>;
0462 #address-cells = <1>;
0463 #size-cells = <0>;
0464 status = "disabled";
0465 };
0466
0467 usb: usb@7e980000 {
0468 compatible = "brcm,bcm2835-usb";
0469 reg = <0x7e980000 0x10000>;
0470 interrupts = <1 9>;
0471 #address-cells = <1>;
0472 #size-cells = <0>;
0473 clocks = <&clk_usb>;
0474 clock-names = "otg";
0475 phys = <&usbphy>;
0476 phy-names = "usb2-phy";
0477 };
0478 };
0479
0480 clocks {
0481 /* The oscillator is the root of the clock tree. */
0482 clk_osc: clk-osc {
0483 compatible = "fixed-clock";
0484 #clock-cells = <0>;
0485 clock-output-names = "osc";
0486 clock-frequency = <19200000>;
0487 };
0488
0489 clk_usb: clk-usb {
0490 compatible = "fixed-clock";
0491 #clock-cells = <0>;
0492 clock-output-names = "otg";
0493 clock-frequency = <480000000>;
0494 };
0495 };
0496
0497 usbphy: phy {
0498 compatible = "usb-nop-xceiv";
0499 #phy-cells = <0>;
0500 };
0501 };
