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0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "bcm283x.dtsi"
0003 #include "bcm2835-common.dtsi"
0004 #include "bcm2835-rpi-common.dtsi"
0005 
0006 / {
0007         compatible = "brcm,bcm2836";
0008 
0009         soc {
0010                 ranges = <0x7e000000 0x3f000000 0x1000000>,
0011                          <0x40000000 0x40000000 0x00001000>;
0012                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
0013 
0014                 local_intc: local_intc@40000000 {
0015                         compatible = "brcm,bcm2836-l1-intc";
0016                         reg = <0x40000000 0x100>;
0017                         interrupt-controller;
0018                         #interrupt-cells = <2>;
0019                         interrupt-parent = <&local_intc>;
0020                 };
0021         };
0022 
0023         arm-pmu {
0024                 compatible = "arm,cortex-a7-pmu";
0025                 interrupt-parent = <&local_intc>;
0026                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
0027         };
0028 
0029         timer {
0030                 compatible = "arm,armv7-timer";
0031                 interrupt-parent = <&local_intc>;
0032                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
0033                              <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
0034                              <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
0035                              <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
0036                 always-on;
0037         };
0038 
0039         cpus: cpus {
0040                 #address-cells = <1>;
0041                 #size-cells = <0>;
0042                 enable-method = "brcm,bcm2836-smp";
0043 
0044                 /* Source for d/i-cache-line-size and d/i-cache-sets
0045                  * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
0046                  * /About-the-L1-memory-system?lang=en
0047                  *
0048                  * Source for d/i-cache-size
0049                  * https://forums.raspberrypi.com/viewtopic.php?t=98428
0050                  */
0051 
0052                 v7_cpu0: cpu@0 {
0053                         device_type = "cpu";
0054                         compatible = "arm,cortex-a7";
0055                         reg = <0xf00>;
0056                         clock-frequency = <800000000>;
0057                         d-cache-size = <0x8000>;
0058                         d-cache-line-size = <64>;
0059                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0060                         i-cache-size = <0x8000>;
0061                         i-cache-line-size = <32>;
0062                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
0063                         next-level-cache = <&l2>;
0064                 };
0065 
0066                 v7_cpu1: cpu@1 {
0067                         device_type = "cpu";
0068                         compatible = "arm,cortex-a7";
0069                         reg = <0xf01>;
0070                         clock-frequency = <800000000>;
0071                         d-cache-size = <0x8000>;
0072                         d-cache-line-size = <64>;
0073                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0074                         i-cache-size = <0x8000>;
0075                         i-cache-line-size = <32>;
0076                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
0077                         next-level-cache = <&l2>;
0078                 };
0079 
0080                 v7_cpu2: cpu@2 {
0081                         device_type = "cpu";
0082                         compatible = "arm,cortex-a7";
0083                         reg = <0xf02>;
0084                         clock-frequency = <800000000>;
0085                         d-cache-size = <0x8000>;
0086                         d-cache-line-size = <64>;
0087                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0088                         i-cache-size = <0x8000>;
0089                         i-cache-line-size = <32>;
0090                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
0091                         next-level-cache = <&l2>;
0092                 };
0093 
0094                 v7_cpu3: cpu@3 {
0095                         device_type = "cpu";
0096                         compatible = "arm,cortex-a7";
0097                         reg = <0xf03>;
0098                         clock-frequency = <800000000>;
0099                         d-cache-size = <0x8000>;
0100                         d-cache-line-size = <64>;
0101                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
0102                         i-cache-size = <0x8000>;
0103                         i-cache-line-size = <32>;
0104                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
0105                         next-level-cache = <&l2>;
0106                 };
0107 
0108                 /* Source for cache-line-size + cache-sets
0109                  * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
0110                  * /About-the-L2-Memory-system?lang=en
0111                  * Source for cache-size
0112                  * https://forums.raspberrypi.com/viewtopic.php?t=98428
0113                  */
0114                 l2: l2-cache0 {
0115                         compatible = "cache";
0116                         cache-size = <0x80000>;
0117                         cache-line-size = <64>;
0118                         cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
0119                         cache-level = <2>;
0120                 };
0121         };
0122 };
0123 
0124 /* Make the BCM2835-style global interrupt controller be a child of the
0125  * CPU-local interrupt controller.
0126  */
0127 &intc {
0128         compatible = "brcm,bcm2836-armctrl-ic";
0129         reg = <0x7e00b200 0x200>;
0130         interrupt-parent = <&local_intc>;
0131         interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
0132 };
0133 
0134 &cpu_thermal {
0135         coefficients = <(-538)  407000>;
0136 };
0137 
0138 /* enable thermal sensor with the correct compatible property set */
0139 &thermal {
0140         compatible = "brcm,bcm2836-thermal";
0141         status = "okay";
0142 };