0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /* This include file covers the common peripherals and configuration between
0004 * bcm2835, bcm2836 and bcm2837 implementations.
0005 */
0006
0007 / {
0008 interrupt-parent = <&intc>;
0009
0010 soc {
0011 dma: dma@7e007000 {
0012 compatible = "brcm,bcm2835-dma";
0013 reg = <0x7e007000 0xf00>;
0014 interrupts = <1 16>,
0015 <1 17>,
0016 <1 18>,
0017 <1 19>,
0018 <1 20>,
0019 <1 21>,
0020 <1 22>,
0021 <1 23>,
0022 <1 24>,
0023 <1 25>,
0024 <1 26>,
0025 /* dma channel 11-14 share one irq */
0026 <1 27>,
0027 <1 27>,
0028 <1 27>,
0029 <1 27>,
0030 /* unused shared irq for all channels */
0031 <1 28>;
0032 interrupt-names = "dma0",
0033 "dma1",
0034 "dma2",
0035 "dma3",
0036 "dma4",
0037 "dma5",
0038 "dma6",
0039 "dma7",
0040 "dma8",
0041 "dma9",
0042 "dma10",
0043 "dma11",
0044 "dma12",
0045 "dma13",
0046 "dma14",
0047 "dma-shared-all";
0048 #dma-cells = <1>;
0049 brcm,dma-channel-mask = <0x7f35>;
0050 };
0051
0052 intc: interrupt-controller@7e00b200 {
0053 compatible = "brcm,bcm2835-armctrl-ic";
0054 reg = <0x7e00b200 0x200>;
0055 interrupt-controller;
0056 #interrupt-cells = <2>;
0057 };
0058
0059 pm: watchdog@7e100000 {
0060 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
0061 #power-domain-cells = <1>;
0062 #reset-cells = <1>;
0063 reg = <0x7e100000 0x114>,
0064 <0x7e00a000 0x24>;
0065 reg-names = "pm", "asb";
0066 clocks = <&clocks BCM2835_CLOCK_V3D>,
0067 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
0068 <&clocks BCM2835_CLOCK_H264>,
0069 <&clocks BCM2835_CLOCK_ISP>;
0070 clock-names = "v3d", "peri_image", "h264", "isp";
0071 system-power-controller;
0072 };
0073
0074 rng@7e104000 {
0075 compatible = "brcm,bcm2835-rng";
0076 reg = <0x7e104000 0x10>;
0077 interrupts = <2 29>;
0078 };
0079
0080 pixelvalve@7e206000 {
0081 compatible = "brcm,bcm2835-pixelvalve0";
0082 reg = <0x7e206000 0x100>;
0083 interrupts = <2 13>; /* pwa0 */
0084 };
0085
0086 pixelvalve@7e207000 {
0087 compatible = "brcm,bcm2835-pixelvalve1";
0088 reg = <0x7e207000 0x100>;
0089 interrupts = <2 14>; /* pwa1 */
0090 };
0091
0092 thermal: thermal@7e212000 {
0093 compatible = "brcm,bcm2835-thermal";
0094 reg = <0x7e212000 0x8>;
0095 clocks = <&clocks BCM2835_CLOCK_TSENS>;
0096 #thermal-sensor-cells = <0>;
0097 status = "disabled";
0098 };
0099
0100 i2c2: i2c@7e805000 {
0101 compatible = "brcm,bcm2835-i2c";
0102 reg = <0x7e805000 0x1000>;
0103 interrupts = <2 21>;
0104 clocks = <&clocks BCM2835_CLOCK_VPU>;
0105 #address-cells = <1>;
0106 #size-cells = <0>;
0107 status = "okay";
0108 };
0109
0110 vec: vec@7e806000 {
0111 compatible = "brcm,bcm2835-vec";
0112 reg = <0x7e806000 0x1000>;
0113 clocks = <&clocks BCM2835_CLOCK_VEC>;
0114 interrupts = <2 27>;
0115 status = "disabled";
0116 };
0117
0118 pixelvalve@7e807000 {
0119 compatible = "brcm,bcm2835-pixelvalve2";
0120 reg = <0x7e807000 0x100>;
0121 interrupts = <2 10>; /* pixelvalve */
0122 };
0123
0124 hdmi: hdmi@7e902000 {
0125 compatible = "brcm,bcm2835-hdmi";
0126 reg = <0x7e902000 0x600>,
0127 <0x7e808000 0x100>;
0128 interrupts = <2 8>, <2 9>;
0129 ddc = <&i2c2>;
0130 clocks = <&clocks BCM2835_PLLH_PIX>,
0131 <&clocks BCM2835_CLOCK_HSM>;
0132 clock-names = "pixel", "hdmi";
0133 dmas = <&dma 17>;
0134 dma-names = "audio-rx";
0135 status = "disabled";
0136 };
0137
0138 v3d: v3d@7ec00000 {
0139 compatible = "brcm,bcm2835-v3d";
0140 reg = <0x7ec00000 0x1000>;
0141 interrupts = <1 10>;
0142 };
0143
0144 vc4: gpu {
0145 compatible = "brcm,bcm2835-vc4";
0146 };
0147 };
0148 };
0149
0150 &cpu_thermal {
0151 thermal-sensors = <&thermal>;
0152 };
0153
0154 &gpio {
0155 i2c_slave_gpio18: i2c_slave_gpio18 {
0156 brcm,pins = <18 19 20 21>;
0157 brcm,function = <BCM2835_FSEL_ALT3>;
0158 };
0159
0160 jtag_gpio4: jtag_gpio4 {
0161 brcm,pins = <4 5 6 12 13>;
0162 brcm,function = <BCM2835_FSEL_ALT5>;
0163 };
0164
0165 pwm0_gpio12: pwm0_gpio12 {
0166 brcm,pins = <12>;
0167 brcm,function = <BCM2835_FSEL_ALT0>;
0168 };
0169 pwm0_gpio18: pwm0_gpio18 {
0170 brcm,pins = <18>;
0171 brcm,function = <BCM2835_FSEL_ALT5>;
0172 };
0173 pwm0_gpio40: pwm0_gpio40 {
0174 brcm,pins = <40>;
0175 brcm,function = <BCM2835_FSEL_ALT0>;
0176 };
0177 pwm1_gpio13: pwm1_gpio13 {
0178 brcm,pins = <13>;
0179 brcm,function = <BCM2835_FSEL_ALT0>;
0180 };
0181 pwm1_gpio19: pwm1_gpio19 {
0182 brcm,pins = <19>;
0183 brcm,function = <BCM2835_FSEL_ALT5>;
0184 };
0185 pwm1_gpio41: pwm1_gpio41 {
0186 brcm,pins = <41>;
0187 brcm,function = <BCM2835_FSEL_ALT0>;
0188 };
0189 pwm1_gpio45: pwm1_gpio45 {
0190 brcm,pins = <45>;
0191 brcm,function = <BCM2835_FSEL_ALT0>;
0192 };
0193 };
0194
0195 &i2s {
0196 dmas = <&dma 2>, <&dma 3>;
0197 dma-names = "tx", "rx";
0198 };
0199
0200 &sdhost {
0201 dmas = <&dma 13>;
0202 dma-names = "rx-tx";
0203 };
0204
0205 &spi {
0206 dmas = <&dma 6>, <&dma 7>;
0207 dma-names = "tx", "rx";
0208 };
