0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "bcm283x.dtsi"
0003
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/soc/bcm2835-pm.h>
0006
0007 / {
0008 compatible = "brcm,bcm2711";
0009
0010 #address-cells = <2>;
0011 #size-cells = <1>;
0012
0013 interrupt-parent = <&gicv2>;
0014
0015 vc4: gpu {
0016 compatible = "brcm,bcm2711-vc5";
0017 status = "disabled";
0018 };
0019
0020 clk_27MHz: clk-27M {
0021 #clock-cells = <0>;
0022 compatible = "fixed-clock";
0023 clock-frequency = <27000000>;
0024 clock-output-names = "27MHz-clock";
0025 };
0026
0027 clk_108MHz: clk-108M {
0028 #clock-cells = <0>;
0029 compatible = "fixed-clock";
0030 clock-frequency = <108000000>;
0031 clock-output-names = "108MHz-clock";
0032 };
0033
0034 soc {
0035 /*
0036 * Defined ranges:
0037 * Common BCM283x peripherals
0038 * BCM2711-specific peripherals
0039 * ARM-local peripherals
0040 */
0041 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
0042 <0x7c000000 0x0 0xfc000000 0x02000000>,
0043 <0x40000000 0x0 0xff800000 0x00800000>;
0044 /* Emulate a contiguous 30-bit address range for DMA */
0045 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
0046
0047 /*
0048 * This node is the provider for the enable-method for
0049 * bringing up secondary cores.
0050 */
0051 local_intc: local_intc@40000000 {
0052 compatible = "brcm,bcm2836-l1-intc";
0053 reg = <0x40000000 0x100>;
0054 };
0055
0056 gicv2: interrupt-controller@40041000 {
0057 interrupt-controller;
0058 #interrupt-cells = <3>;
0059 compatible = "arm,gic-400";
0060 reg = <0x40041000 0x1000>,
0061 <0x40042000 0x2000>,
0062 <0x40044000 0x2000>,
0063 <0x40046000 0x2000>;
0064 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
0065 IRQ_TYPE_LEVEL_HIGH)>;
0066 };
0067
0068 avs_monitor: avs-monitor@7d5d2000 {
0069 compatible = "brcm,bcm2711-avs-monitor",
0070 "syscon", "simple-mfd";
0071 reg = <0x7d5d2000 0xf00>;
0072
0073 thermal: thermal {
0074 compatible = "brcm,bcm2711-thermal";
0075 #thermal-sensor-cells = <0>;
0076 };
0077 };
0078
0079 dma: dma@7e007000 {
0080 compatible = "brcm,bcm2835-dma";
0081 reg = <0x7e007000 0xb00>;
0082 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0085 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0086 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0087 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0088 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0089 /* DMA lite 7 - 10 */
0090 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0091 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0092 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0093 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0094 interrupt-names = "dma0",
0095 "dma1",
0096 "dma2",
0097 "dma3",
0098 "dma4",
0099 "dma5",
0100 "dma6",
0101 "dma7",
0102 "dma8",
0103 "dma9",
0104 "dma10";
0105 #dma-cells = <1>;
0106 brcm,dma-channel-mask = <0x07f5>;
0107 };
0108
0109 pm: watchdog@7e100000 {
0110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
0111 #power-domain-cells = <1>;
0112 #reset-cells = <1>;
0113 reg = <0x7e100000 0x114>,
0114 <0x7e00a000 0x24>,
0115 <0x7ec11000 0x20>;
0116 reg-names = "pm", "asb", "rpivid_asb";
0117 clocks = <&clocks BCM2835_CLOCK_V3D>,
0118 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
0119 <&clocks BCM2835_CLOCK_H264>,
0120 <&clocks BCM2835_CLOCK_ISP>;
0121 clock-names = "v3d", "peri_image", "h264", "isp";
0122 system-power-controller;
0123 };
0124
0125 rng@7e104000 {
0126 compatible = "brcm,bcm2711-rng200";
0127 reg = <0x7e104000 0x28>;
0128 };
0129
0130 uart2: serial@7e201400 {
0131 compatible = "arm,pl011", "arm,primecell";
0132 reg = <0x7e201400 0x200>;
0133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0134 clocks = <&clocks BCM2835_CLOCK_UART>,
0135 <&clocks BCM2835_CLOCK_VPU>;
0136 clock-names = "uartclk", "apb_pclk";
0137 arm,primecell-periphid = <0x00241011>;
0138 status = "disabled";
0139 };
0140
0141 uart3: serial@7e201600 {
0142 compatible = "arm,pl011", "arm,primecell";
0143 reg = <0x7e201600 0x200>;
0144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0145 clocks = <&clocks BCM2835_CLOCK_UART>,
0146 <&clocks BCM2835_CLOCK_VPU>;
0147 clock-names = "uartclk", "apb_pclk";
0148 arm,primecell-periphid = <0x00241011>;
0149 status = "disabled";
0150 };
0151
0152 uart4: serial@7e201800 {
0153 compatible = "arm,pl011", "arm,primecell";
0154 reg = <0x7e201800 0x200>;
0155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0156 clocks = <&clocks BCM2835_CLOCK_UART>,
0157 <&clocks BCM2835_CLOCK_VPU>;
0158 clock-names = "uartclk", "apb_pclk";
0159 arm,primecell-periphid = <0x00241011>;
0160 status = "disabled";
0161 };
0162
0163 uart5: serial@7e201a00 {
0164 compatible = "arm,pl011", "arm,primecell";
0165 reg = <0x7e201a00 0x200>;
0166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0167 clocks = <&clocks BCM2835_CLOCK_UART>,
0168 <&clocks BCM2835_CLOCK_VPU>;
0169 clock-names = "uartclk", "apb_pclk";
0170 arm,primecell-periphid = <0x00241011>;
0171 status = "disabled";
0172 };
0173
0174 spi3: spi@7e204600 {
0175 compatible = "brcm,bcm2835-spi";
0176 reg = <0x7e204600 0x0200>;
0177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0178 clocks = <&clocks BCM2835_CLOCK_VPU>;
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181 status = "disabled";
0182 };
0183
0184 spi4: spi@7e204800 {
0185 compatible = "brcm,bcm2835-spi";
0186 reg = <0x7e204800 0x0200>;
0187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0188 clocks = <&clocks BCM2835_CLOCK_VPU>;
0189 #address-cells = <1>;
0190 #size-cells = <0>;
0191 status = "disabled";
0192 };
0193
0194 spi5: spi@7e204a00 {
0195 compatible = "brcm,bcm2835-spi";
0196 reg = <0x7e204a00 0x0200>;
0197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0198 clocks = <&clocks BCM2835_CLOCK_VPU>;
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201 status = "disabled";
0202 };
0203
0204 spi6: spi@7e204c00 {
0205 compatible = "brcm,bcm2835-spi";
0206 reg = <0x7e204c00 0x0200>;
0207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0208 clocks = <&clocks BCM2835_CLOCK_VPU>;
0209 #address-cells = <1>;
0210 #size-cells = <0>;
0211 status = "disabled";
0212 };
0213
0214 i2c3: i2c@7e205600 {
0215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
0216 reg = <0x7e205600 0x200>;
0217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0218 clocks = <&clocks BCM2835_CLOCK_VPU>;
0219 #address-cells = <1>;
0220 #size-cells = <0>;
0221 status = "disabled";
0222 };
0223
0224 i2c4: i2c@7e205800 {
0225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
0226 reg = <0x7e205800 0x200>;
0227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0228 clocks = <&clocks BCM2835_CLOCK_VPU>;
0229 #address-cells = <1>;
0230 #size-cells = <0>;
0231 status = "disabled";
0232 };
0233
0234 i2c5: i2c@7e205a00 {
0235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
0236 reg = <0x7e205a00 0x200>;
0237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0238 clocks = <&clocks BCM2835_CLOCK_VPU>;
0239 #address-cells = <1>;
0240 #size-cells = <0>;
0241 status = "disabled";
0242 };
0243
0244 i2c6: i2c@7e205c00 {
0245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
0246 reg = <0x7e205c00 0x200>;
0247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0248 clocks = <&clocks BCM2835_CLOCK_VPU>;
0249 #address-cells = <1>;
0250 #size-cells = <0>;
0251 status = "disabled";
0252 };
0253
0254 pixelvalve0: pixelvalve@7e206000 {
0255 compatible = "brcm,bcm2711-pixelvalve0";
0256 reg = <0x7e206000 0x100>;
0257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0258 status = "disabled";
0259 };
0260
0261 pixelvalve1: pixelvalve@7e207000 {
0262 compatible = "brcm,bcm2711-pixelvalve1";
0263 reg = <0x7e207000 0x100>;
0264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0265 status = "disabled";
0266 };
0267
0268 pixelvalve2: pixelvalve@7e20a000 {
0269 compatible = "brcm,bcm2711-pixelvalve2";
0270 reg = <0x7e20a000 0x100>;
0271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0272 status = "disabled";
0273 };
0274
0275 pwm1: pwm@7e20c800 {
0276 compatible = "brcm,bcm2835-pwm";
0277 reg = <0x7e20c800 0x28>;
0278 clocks = <&clocks BCM2835_CLOCK_PWM>;
0279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
0280 assigned-clock-rates = <10000000>;
0281 #pwm-cells = <2>;
0282 status = "disabled";
0283 };
0284
0285 pixelvalve4: pixelvalve@7e216000 {
0286 compatible = "brcm,bcm2711-pixelvalve4";
0287 reg = <0x7e216000 0x100>;
0288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0289 status = "disabled";
0290 };
0291
0292 hvs: hvs@7e400000 {
0293 compatible = "brcm,bcm2711-hvs";
0294 reg = <0x7e400000 0x8000>;
0295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0296 };
0297
0298 pixelvalve3: pixelvalve@7ec12000 {
0299 compatible = "brcm,bcm2711-pixelvalve3";
0300 reg = <0x7ec12000 0x100>;
0301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0302 status = "disabled";
0303 };
0304
0305 vec: vec@7ec13000 {
0306 compatible = "brcm,bcm2711-vec";
0307 reg = <0x7ec13000 0x1000>;
0308 clocks = <&clocks BCM2835_CLOCK_VEC>;
0309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0310 status = "disabled";
0311 };
0312
0313 dvp: clock@7ef00000 {
0314 compatible = "brcm,brcm2711-dvp";
0315 reg = <0x7ef00000 0x10>;
0316 clocks = <&clk_108MHz>;
0317 #clock-cells = <1>;
0318 #reset-cells = <1>;
0319 };
0320
0321 aon_intr: interrupt-controller@7ef00100 {
0322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
0323 reg = <0x7ef00100 0x30>;
0324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0325 interrupt-controller;
0326 #interrupt-cells = <1>;
0327 };
0328
0329 hdmi0: hdmi@7ef00700 {
0330 compatible = "brcm,bcm2711-hdmi0";
0331 reg = <0x7ef00700 0x300>,
0332 <0x7ef00300 0x200>,
0333 <0x7ef00f00 0x80>,
0334 <0x7ef00f80 0x80>,
0335 <0x7ef01b00 0x200>,
0336 <0x7ef01f00 0x400>,
0337 <0x7ef00200 0x80>,
0338 <0x7ef04300 0x100>,
0339 <0x7ef20000 0x100>;
0340 reg-names = "hdmi",
0341 "dvp",
0342 "phy",
0343 "rm",
0344 "packet",
0345 "metadata",
0346 "csc",
0347 "cec",
0348 "hd";
0349 clock-names = "hdmi", "bvb", "audio", "cec";
0350 resets = <&dvp 0>;
0351 interrupt-parent = <&aon_intr>;
0352 interrupts = <0>, <1>, <2>,
0353 <3>, <4>, <5>;
0354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
0355 "wakeup", "hpd-connected", "hpd-removed";
0356 ddc = <&ddc0>;
0357 dmas = <&dma 10>;
0358 dma-names = "audio-rx";
0359 status = "disabled";
0360 };
0361
0362 ddc0: i2c@7ef04500 {
0363 compatible = "brcm,bcm2711-hdmi-i2c";
0364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
0365 reg-names = "bsc", "auto-i2c";
0366 clock-frequency = <97500>;
0367 status = "disabled";
0368 };
0369
0370 hdmi1: hdmi@7ef05700 {
0371 compatible = "brcm,bcm2711-hdmi1";
0372 reg = <0x7ef05700 0x300>,
0373 <0x7ef05300 0x200>,
0374 <0x7ef05f00 0x80>,
0375 <0x7ef05f80 0x80>,
0376 <0x7ef06b00 0x200>,
0377 <0x7ef06f00 0x400>,
0378 <0x7ef00280 0x80>,
0379 <0x7ef09300 0x100>,
0380 <0x7ef20000 0x100>;
0381 reg-names = "hdmi",
0382 "dvp",
0383 "phy",
0384 "rm",
0385 "packet",
0386 "metadata",
0387 "csc",
0388 "cec",
0389 "hd";
0390 ddc = <&ddc1>;
0391 clock-names = "hdmi", "bvb", "audio", "cec";
0392 resets = <&dvp 1>;
0393 interrupt-parent = <&aon_intr>;
0394 interrupts = <8>, <7>, <6>,
0395 <9>, <10>, <11>;
0396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
0397 "wakeup", "hpd-connected", "hpd-removed";
0398 dmas = <&dma 17>;
0399 dma-names = "audio-rx";
0400 status = "disabled";
0401 };
0402
0403 ddc1: i2c@7ef09500 {
0404 compatible = "brcm,bcm2711-hdmi-i2c";
0405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
0406 reg-names = "bsc", "auto-i2c";
0407 clock-frequency = <97500>;
0408 status = "disabled";
0409 };
0410 };
0411
0412 /*
0413 * emmc2 has different DMA constraints based on SoC revisions. It was
0414 * moved into its own bus, so as for RPi4's firmware to update them.
0415 * The firmware will find whether the emmc2bus alias is defined, and if
0416 * so, it'll edit the dma-ranges property below accordingly.
0417 */
0418 emmc2bus: emmc2bus {
0419 compatible = "simple-bus";
0420 #address-cells = <2>;
0421 #size-cells = <1>;
0422
0423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
0424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
0425
0426 emmc2: mmc@7e340000 {
0427 compatible = "brcm,bcm2711-emmc2";
0428 reg = <0x0 0x7e340000 0x100>;
0429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0430 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
0431 status = "disabled";
0432 };
0433 };
0434
0435 arm-pmu {
0436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
0437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0442 };
0443
0444 timer {
0445 compatible = "arm,armv8-timer";
0446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
0447 IRQ_TYPE_LEVEL_LOW)>,
0448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
0449 IRQ_TYPE_LEVEL_LOW)>,
0450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
0451 IRQ_TYPE_LEVEL_LOW)>,
0452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
0453 IRQ_TYPE_LEVEL_LOW)>;
0454 /* This only applies to the ARMv7 stub */
0455 arm,cpu-registers-not-fw-configured;
0456 };
0457
0458 cpus: cpus {
0459 #address-cells = <1>;
0460 #size-cells = <0>;
0461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
0462
0463 /* Source for d/i-cache-line-size and d/i-cache-sets
0464 * https://developer.arm.com/documentation/100095/0003
0465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
0466 * Source for d/i-cache-size
0467 * https://www.raspberrypi.com/documentation/computers
0468 * /processors.html#bcm2711
0469 */
0470 cpu0: cpu@0 {
0471 device_type = "cpu";
0472 compatible = "arm,cortex-a72";
0473 reg = <0>;
0474 enable-method = "spin-table";
0475 cpu-release-addr = <0x0 0x000000d8>;
0476 d-cache-size = <0x8000>;
0477 d-cache-line-size = <64>;
0478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0479 i-cache-size = <0xc000>;
0480 i-cache-line-size = <64>;
0481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
0482 next-level-cache = <&l2>;
0483 };
0484
0485 cpu1: cpu@1 {
0486 device_type = "cpu";
0487 compatible = "arm,cortex-a72";
0488 reg = <1>;
0489 enable-method = "spin-table";
0490 cpu-release-addr = <0x0 0x000000e0>;
0491 d-cache-size = <0x8000>;
0492 d-cache-line-size = <64>;
0493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0494 i-cache-size = <0xc000>;
0495 i-cache-line-size = <64>;
0496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
0497 next-level-cache = <&l2>;
0498 };
0499
0500 cpu2: cpu@2 {
0501 device_type = "cpu";
0502 compatible = "arm,cortex-a72";
0503 reg = <2>;
0504 enable-method = "spin-table";
0505 cpu-release-addr = <0x0 0x000000e8>;
0506 d-cache-size = <0x8000>;
0507 d-cache-line-size = <64>;
0508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0509 i-cache-size = <0xc000>;
0510 i-cache-line-size = <64>;
0511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
0512 next-level-cache = <&l2>;
0513 };
0514
0515 cpu3: cpu@3 {
0516 device_type = "cpu";
0517 compatible = "arm,cortex-a72";
0518 reg = <3>;
0519 enable-method = "spin-table";
0520 cpu-release-addr = <0x0 0x000000f0>;
0521 d-cache-size = <0x8000>;
0522 d-cache-line-size = <64>;
0523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
0524 i-cache-size = <0xc000>;
0525 i-cache-line-size = <64>;
0526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
0527 next-level-cache = <&l2>;
0528 };
0529
0530 /* Source for d/i-cache-line-size and d/i-cache-sets
0531 * https://developer.arm.com/documentation/100095/0003
0532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
0533 * Source for d/i-cache-size
0534 * https://www.raspberrypi.com/documentation/computers
0535 * /processors.html#bcm2711
0536 */
0537 l2: l2-cache0 {
0538 compatible = "cache";
0539 cache-size = <0x100000>;
0540 cache-line-size = <64>;
0541 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
0542 cache-level = <2>;
0543 };
0544 };
0545
0546 scb {
0547 compatible = "simple-bus";
0548 #address-cells = <2>;
0549 #size-cells = <1>;
0550
0551 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
0552 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
0553
0554 pcie0: pcie@7d500000 {
0555 compatible = "brcm,bcm2711-pcie";
0556 reg = <0x0 0x7d500000 0x9310>;
0557 device_type = "pci";
0558 #address-cells = <3>;
0559 #interrupt-cells = <1>;
0560 #size-cells = <2>;
0561 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0562 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0563 interrupt-names = "pcie", "msi";
0564 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0565 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
0566 IRQ_TYPE_LEVEL_HIGH>,
0567 <0 0 0 2 &gicv2 GIC_SPI 144
0568 IRQ_TYPE_LEVEL_HIGH>,
0569 <0 0 0 3 &gicv2 GIC_SPI 145
0570 IRQ_TYPE_LEVEL_HIGH>,
0571 <0 0 0 4 &gicv2 GIC_SPI 146
0572 IRQ_TYPE_LEVEL_HIGH>;
0573 msi-controller;
0574 msi-parent = <&pcie0>;
0575
0576 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
0577 0x0 0x04000000>;
0578 /*
0579 * The wrapper around the PCIe block has a bug
0580 * preventing it from accessing beyond the first 3GB of
0581 * memory.
0582 */
0583 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
0584 0x0 0xc0000000>;
0585 brcm,enable-ssc;
0586 };
0587
0588 genet: ethernet@7d580000 {
0589 compatible = "brcm,bcm2711-genet-v5";
0590 reg = <0x0 0x7d580000 0x10000>;
0591 #address-cells = <0x1>;
0592 #size-cells = <0x1>;
0593 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0595 status = "disabled";
0596
0597 genet_mdio: mdio@e14 {
0598 compatible = "brcm,genet-mdio-v5";
0599 reg = <0xe14 0x8>;
0600 reg-names = "mdio";
0601 #address-cells = <0x1>;
0602 #size-cells = <0x0>;
0603 };
0604 };
0605
0606 v3d: gpu@7ec00000 {
0607 compatible = "brcm,2711-v3d";
0608 reg = <0x0 0x7ec00000 0x4000>,
0609 <0x0 0x7ec04000 0x4000>;
0610 reg-names = "hub", "core0";
0611
0612 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
0613 resets = <&pm BCM2835_RESET_V3D>;
0614 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0615 };
0616 };
0617 };
0618
0619 &clk_osc {
0620 clock-frequency = <54000000>;
0621 };
0622
0623 &clocks {
0624 compatible = "brcm,bcm2711-cprman";
0625 };
0626
0627 &cpu_thermal {
0628 coefficients = <(-487) 410040>;
0629 thermal-sensors = <&thermal>;
0630 };
0631
0632 &dsi0 {
0633 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0634 };
0635
0636 &dsi1 {
0637 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0638 compatible = "brcm,bcm2711-dsi1";
0639 };
0640
0641 &gpio {
0642 compatible = "brcm,bcm2711-gpio";
0643 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0644 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0645 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0646 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0647
0648 gpio-ranges = <&gpio 0 0 58>;
0649
0650 gpclk0_gpio49: gpclk0_gpio49 {
0651 pin-gpclk {
0652 pins = "gpio49";
0653 function = "alt1";
0654 bias-disable;
0655 };
0656 };
0657 gpclk1_gpio50: gpclk1_gpio50 {
0658 pin-gpclk {
0659 pins = "gpio50";
0660 function = "alt1";
0661 bias-disable;
0662 };
0663 };
0664 gpclk2_gpio51: gpclk2_gpio51 {
0665 pin-gpclk {
0666 pins = "gpio51";
0667 function = "alt1";
0668 bias-disable;
0669 };
0670 };
0671
0672 i2c0_gpio46: i2c0_gpio46 {
0673 pin-sda {
0674 function = "alt0";
0675 pins = "gpio46";
0676 bias-pull-up;
0677 };
0678 pin-scl {
0679 function = "alt0";
0680 pins = "gpio47";
0681 bias-disable;
0682 };
0683 };
0684 i2c1_gpio46: i2c1_gpio46 {
0685 pin-sda {
0686 function = "alt1";
0687 pins = "gpio46";
0688 bias-pull-up;
0689 };
0690 pin-scl {
0691 function = "alt1";
0692 pins = "gpio47";
0693 bias-disable;
0694 };
0695 };
0696 i2c3_gpio2: i2c3_gpio2 {
0697 pin-sda {
0698 function = "alt5";
0699 pins = "gpio2";
0700 bias-pull-up;
0701 };
0702 pin-scl {
0703 function = "alt5";
0704 pins = "gpio3";
0705 bias-disable;
0706 };
0707 };
0708 i2c3_gpio4: i2c3_gpio4 {
0709 pin-sda {
0710 function = "alt5";
0711 pins = "gpio4";
0712 bias-pull-up;
0713 };
0714 pin-scl {
0715 function = "alt5";
0716 pins = "gpio5";
0717 bias-disable;
0718 };
0719 };
0720 i2c4_gpio6: i2c4_gpio6 {
0721 pin-sda {
0722 function = "alt5";
0723 pins = "gpio6";
0724 bias-pull-up;
0725 };
0726 pin-scl {
0727 function = "alt5";
0728 pins = "gpio7";
0729 bias-disable;
0730 };
0731 };
0732 i2c4_gpio8: i2c4_gpio8 {
0733 pin-sda {
0734 function = "alt5";
0735 pins = "gpio8";
0736 bias-pull-up;
0737 };
0738 pin-scl {
0739 function = "alt5";
0740 pins = "gpio9";
0741 bias-disable;
0742 };
0743 };
0744 i2c5_gpio10: i2c5_gpio10 {
0745 pin-sda {
0746 function = "alt5";
0747 pins = "gpio10";
0748 bias-pull-up;
0749 };
0750 pin-scl {
0751 function = "alt5";
0752 pins = "gpio11";
0753 bias-disable;
0754 };
0755 };
0756 i2c5_gpio12: i2c5_gpio12 {
0757 pin-sda {
0758 function = "alt5";
0759 pins = "gpio12";
0760 bias-pull-up;
0761 };
0762 pin-scl {
0763 function = "alt5";
0764 pins = "gpio13";
0765 bias-disable;
0766 };
0767 };
0768 i2c6_gpio0: i2c6_gpio0 {
0769 pin-sda {
0770 function = "alt5";
0771 pins = "gpio0";
0772 bias-pull-up;
0773 };
0774 pin-scl {
0775 function = "alt5";
0776 pins = "gpio1";
0777 bias-disable;
0778 };
0779 };
0780 i2c6_gpio22: i2c6_gpio22 {
0781 pin-sda {
0782 function = "alt5";
0783 pins = "gpio22";
0784 bias-pull-up;
0785 };
0786 pin-scl {
0787 function = "alt5";
0788 pins = "gpio23";
0789 bias-disable;
0790 };
0791 };
0792 i2c_slave_gpio8: i2c_slave_gpio8 {
0793 pins-i2c-slave {
0794 pins = "gpio8",
0795 "gpio9",
0796 "gpio10",
0797 "gpio11";
0798 function = "alt3";
0799 };
0800 };
0801
0802 jtag_gpio48: jtag_gpio48 {
0803 pins-jtag {
0804 pins = "gpio48",
0805 "gpio49",
0806 "gpio50",
0807 "gpio51",
0808 "gpio52",
0809 "gpio53";
0810 function = "alt4";
0811 };
0812 };
0813
0814 mii_gpio28: mii_gpio28 {
0815 pins-mii {
0816 pins = "gpio28",
0817 "gpio29",
0818 "gpio30",
0819 "gpio31";
0820 function = "alt4";
0821 };
0822 };
0823 mii_gpio36: mii_gpio36 {
0824 pins-mii {
0825 pins = "gpio36",
0826 "gpio37",
0827 "gpio38",
0828 "gpio39";
0829 function = "alt5";
0830 };
0831 };
0832
0833 pcm_gpio50: pcm_gpio50 {
0834 pins-pcm {
0835 pins = "gpio50",
0836 "gpio51",
0837 "gpio52",
0838 "gpio53";
0839 function = "alt2";
0840 };
0841 };
0842
0843 pwm0_0_gpio12: pwm0_0_gpio12 {
0844 pin-pwm {
0845 pins = "gpio12";
0846 function = "alt0";
0847 bias-disable;
0848 };
0849 };
0850 pwm0_0_gpio18: pwm0_0_gpio18 {
0851 pin-pwm {
0852 pins = "gpio18";
0853 function = "alt5";
0854 bias-disable;
0855 };
0856 };
0857 pwm1_0_gpio40: pwm1_0_gpio40 {
0858 pin-pwm {
0859 pins = "gpio40";
0860 function = "alt0";
0861 bias-disable;
0862 };
0863 };
0864 pwm0_1_gpio13: pwm0_1_gpio13 {
0865 pin-pwm {
0866 pins = "gpio13";
0867 function = "alt0";
0868 bias-disable;
0869 };
0870 };
0871 pwm0_1_gpio19: pwm0_1_gpio19 {
0872 pin-pwm {
0873 pins = "gpio19";
0874 function = "alt5";
0875 bias-disable;
0876 };
0877 };
0878 pwm1_1_gpio41: pwm1_1_gpio41 {
0879 pin-pwm {
0880 pins = "gpio41";
0881 function = "alt0";
0882 bias-disable;
0883 };
0884 };
0885 pwm0_1_gpio45: pwm0_1_gpio45 {
0886 pin-pwm {
0887 pins = "gpio45";
0888 function = "alt0";
0889 bias-disable;
0890 };
0891 };
0892 pwm0_0_gpio52: pwm0_0_gpio52 {
0893 pin-pwm {
0894 pins = "gpio52";
0895 function = "alt1";
0896 bias-disable;
0897 };
0898 };
0899 pwm0_1_gpio53: pwm0_1_gpio53 {
0900 pin-pwm {
0901 pins = "gpio53";
0902 function = "alt1";
0903 bias-disable;
0904 };
0905 };
0906
0907 rgmii_gpio35: rgmii_gpio35 {
0908 pin-start-stop {
0909 pins = "gpio35";
0910 function = "alt4";
0911 };
0912 pin-rx-ok {
0913 pins = "gpio36";
0914 function = "alt4";
0915 };
0916 };
0917 rgmii_irq_gpio34: rgmii_irq_gpio34 {
0918 pin-irq {
0919 pins = "gpio34";
0920 function = "alt5";
0921 };
0922 };
0923 rgmii_irq_gpio39: rgmii_irq_gpio39 {
0924 pin-irq {
0925 pins = "gpio39";
0926 function = "alt4";
0927 };
0928 };
0929 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
0930 pins-mdio {
0931 pins = "gpio28",
0932 "gpio29";
0933 function = "alt5";
0934 };
0935 };
0936 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
0937 pins-mdio {
0938 pins = "gpio37",
0939 "gpio38";
0940 function = "alt4";
0941 };
0942 };
0943
0944 spi0_gpio46: spi0_gpio46 {
0945 pins-spi {
0946 pins = "gpio46",
0947 "gpio47",
0948 "gpio48",
0949 "gpio49";
0950 function = "alt2";
0951 };
0952 };
0953 spi2_gpio46: spi2_gpio46 {
0954 pins-spi {
0955 pins = "gpio46",
0956 "gpio47",
0957 "gpio48",
0958 "gpio49",
0959 "gpio50";
0960 function = "alt5";
0961 };
0962 };
0963 spi3_gpio0: spi3_gpio0 {
0964 pins-spi {
0965 pins = "gpio0",
0966 "gpio1",
0967 "gpio2",
0968 "gpio3";
0969 function = "alt3";
0970 };
0971 };
0972 spi4_gpio4: spi4_gpio4 {
0973 pins-spi {
0974 pins = "gpio4",
0975 "gpio5",
0976 "gpio6",
0977 "gpio7";
0978 function = "alt3";
0979 };
0980 };
0981 spi5_gpio12: spi5_gpio12 {
0982 pins-spi {
0983 pins = "gpio12",
0984 "gpio13",
0985 "gpio14",
0986 "gpio15";
0987 function = "alt3";
0988 };
0989 };
0990 spi6_gpio18: spi6_gpio18 {
0991 pins-spi {
0992 pins = "gpio18",
0993 "gpio19",
0994 "gpio20",
0995 "gpio21";
0996 function = "alt3";
0997 };
0998 };
0999
1000 uart2_gpio0: uart2_gpio0 {
1001 pin-tx {
1002 pins = "gpio0";
1003 function = "alt4";
1004 bias-disable;
1005 };
1006 pin-rx {
1007 pins = "gpio1";
1008 function = "alt4";
1009 bias-pull-up;
1010 };
1011 };
1012 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
1013 pin-cts {
1014 pins = "gpio2";
1015 function = "alt4";
1016 bias-pull-up;
1017 };
1018 pin-rts {
1019 pins = "gpio3";
1020 function = "alt4";
1021 bias-disable;
1022 };
1023 };
1024 uart3_gpio4: uart3_gpio4 {
1025 pin-tx {
1026 pins = "gpio4";
1027 function = "alt4";
1028 bias-disable;
1029 };
1030 pin-rx {
1031 pins = "gpio5";
1032 function = "alt4";
1033 bias-pull-up;
1034 };
1035 };
1036 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
1037 pin-cts {
1038 pins = "gpio6";
1039 function = "alt4";
1040 bias-pull-up;
1041 };
1042 pin-rts {
1043 pins = "gpio7";
1044 function = "alt4";
1045 bias-disable;
1046 };
1047 };
1048 uart4_gpio8: uart4_gpio8 {
1049 pin-tx {
1050 pins = "gpio8";
1051 function = "alt4";
1052 bias-disable;
1053 };
1054 pin-rx {
1055 pins = "gpio9";
1056 function = "alt4";
1057 bias-pull-up;
1058 };
1059 };
1060 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1061 pin-cts {
1062 pins = "gpio10";
1063 function = "alt4";
1064 bias-pull-up;
1065 };
1066 pin-rts {
1067 pins = "gpio11";
1068 function = "alt4";
1069 bias-disable;
1070 };
1071 };
1072 uart5_gpio12: uart5_gpio12 {
1073 pin-tx {
1074 pins = "gpio12";
1075 function = "alt4";
1076 bias-disable;
1077 };
1078 pin-rx {
1079 pins = "gpio13";
1080 function = "alt4";
1081 bias-pull-up;
1082 };
1083 };
1084 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1085 pin-cts {
1086 pins = "gpio14";
1087 function = "alt4";
1088 bias-pull-up;
1089 };
1090 pin-rts {
1091 pins = "gpio15";
1092 function = "alt4";
1093 bias-disable;
1094 };
1095 };
1096 };
1097
1098 &rmem {
1099 #address-cells = <2>;
1100 };
1101
1102 &cma {
1103 /*
1104 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1105 * that's not good enough for the BCM2711 as some devices can
1106 * only address the lower 1G of memory (ZONE_DMA).
1107 */
1108 alloc-ranges = <0x0 0x00000000 0x40000000>;
1109 };
1110
1111 &i2c0 {
1112 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1113 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1114 };
1115
1116 &i2c1 {
1117 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1118 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1119 };
1120
1121 &mailbox {
1122 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1123 };
1124
1125 &sdhci {
1126 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1127 };
1128
1129 &sdhost {
1130 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1131 };
1132
1133 &spi {
1134 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1135 };
1136
1137 &spi1 {
1138 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1139 };
1140
1141 &spi2 {
1142 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1143 };
1144
1145 &system_timer {
1146 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1150 };
1151
1152 &txp {
1153 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1154 };
1155
1156 &uart0 {
1157 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1158 };
1159
1160 &uart1 {
1161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1162 };
1163
1164 &usb {
1165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1166 };
1167
1168 &vec {
1169 compatible = "brcm,bcm2711-vec";
1170 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1171 };
