0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright(c) 2017 Broadcom. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom Corporation nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 #include <dt-bindings/interrupt-controller/arm-gic.h>
0034 #include <dt-bindings/interrupt-controller/irq.h>
0035
0036 / {
0037 compatible = "brcm,hr2";
0038 model = "Broadcom Hurricane 2 SoC";
0039 interrupt-parent = <&gic>;
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042
0043 cpus {
0044 #address-cells = <1>;
0045 #size-cells = <0>;
0046
0047 cpu0: cpu@0 {
0048 device_type = "cpu";
0049 compatible = "arm,cortex-a9";
0050 next-level-cache = <&L2>;
0051 reg = <0x0>;
0052 };
0053 };
0054
0055 pmu {
0056 compatible = "arm,cortex-a9-pmu";
0057 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
0058 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0059 interrupt-affinity = <&cpu0>;
0060 };
0061
0062 mpcore@19000000 {
0063 compatible = "simple-bus";
0064 ranges = <0x00000000 0x19000000 0x00023000>;
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067
0068 a9pll: arm_clk@0 {
0069 #clock-cells = <0>;
0070 compatible = "brcm,hr2-armpll";
0071 clocks = <&osc>;
0072 reg = <0x0 0x1000>;
0073 };
0074
0075 timer@20200 {
0076 compatible = "arm,cortex-a9-global-timer";
0077 reg = <0x20200 0x100>;
0078 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
0079 clocks = <&periph_clk>;
0080 };
0081
0082 twd-timer@20600 {
0083 compatible = "arm,cortex-a9-twd-timer";
0084 reg = <0x20600 0x20>;
0085 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
0086 IRQ_TYPE_EDGE_RISING)>;
0087 clocks = <&periph_clk>;
0088 };
0089
0090 twd-watchdog@20620 {
0091 compatible = "arm,cortex-a9-twd-wdt";
0092 reg = <0x20620 0x20>;
0093 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
0094 IRQ_TYPE_EDGE_RISING)>;
0095 clocks = <&periph_clk>;
0096 };
0097
0098 gic: interrupt-controller@21000 {
0099 compatible = "arm,cortex-a9-gic";
0100 #interrupt-cells = <3>;
0101 #address-cells = <0>;
0102 interrupt-controller;
0103 reg = <0x21000 0x1000>,
0104 <0x20100 0x100>;
0105 };
0106
0107 L2: cache-controller@22000 {
0108 compatible = "arm,pl310-cache";
0109 reg = <0x22000 0x1000>;
0110 cache-unified;
0111 cache-level = <2>;
0112 };
0113 };
0114
0115 clocks {
0116 #address-cells = <1>;
0117 #size-cells = <1>;
0118 ranges;
0119
0120 osc: oscillator {
0121 #clock-cells = <0>;
0122 compatible = "fixed-clock";
0123 clock-frequency = <25000000>;
0124 };
0125
0126 periph_clk: periph_clk {
0127 #clock-cells = <0>;
0128 compatible = "fixed-factor-clock";
0129 clocks = <&a9pll>;
0130 clock-div = <2>;
0131 clock-mult = <1>;
0132 };
0133 };
0134
0135 axi@18000000 {
0136 compatible = "simple-bus";
0137 ranges = <0x00000000 0x18000000 0x0011c40c>;
0138 #address-cells = <1>;
0139 #size-cells = <1>;
0140
0141 uart0: serial@300 {
0142 compatible = "ns16550a";
0143 reg = <0x0300 0x100>;
0144 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0145 clocks = <&osc>;
0146 status = "disabled";
0147 };
0148
0149 uart1: serial@400 {
0150 compatible = "ns16550a";
0151 reg = <0x0400 0x100>;
0152 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0153 clocks = <&osc>;
0154 status = "disabled";
0155 };
0156
0157 dma@20000 {
0158 compatible = "arm,pl330", "arm,primecell";
0159 reg = <0x20000 0x1000>;
0160 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0162 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0163 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
0164 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0166 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0167 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0168 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0169 #dma-cells = <1>;
0170 status = "disabled";
0171 };
0172
0173 amac0: ethernet@22000 {
0174 compatible = "brcm,nsp-amac";
0175 reg = <0x22000 0x1000>,
0176 <0x110000 0x1000>;
0177 reg-names = "amac_base", "idm_base";
0178 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
0179 status = "disabled";
0180 };
0181
0182 nand_controller: nand-controller@26000 {
0183 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
0184 reg = <0x26000 0x600>,
0185 <0x11b408 0x600>,
0186 <0x026f00 0x20>;
0187 reg-names = "nand", "iproc-idm", "iproc-ext";
0188 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0189
0190 #address-cells = <1>;
0191 #size-cells = <0>;
0192
0193 brcm,nand-has-wp;
0194 };
0195
0196 gpiob: gpio@30000 {
0197 compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
0198 reg = <0x30000 0x50>;
0199 #gpio-cells = <2>;
0200 gpio-controller;
0201 ngpios = <4>;
0202 interrupt-controller;
0203 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0204 };
0205
0206 pwm: pwm@31000 {
0207 compatible = "brcm,iproc-pwm";
0208 reg = <0x31000 0x28>;
0209 clocks = <&osc>;
0210 #pwm-cells = <3>;
0211 status = "disabled";
0212 };
0213
0214 rng: rng@33000 {
0215 compatible = "brcm,bcm-nsp-rng";
0216 reg = <0x33000 0x14>;
0217 };
0218
0219 qspi: spi@27200 {
0220 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
0221 reg = <0x027200 0x184>,
0222 <0x027000 0x124>,
0223 <0x11c408 0x004>,
0224 <0x0273a0 0x01c>;
0225 reg-names = "mspi", "bspi", "intr_regs",
0226 "intr_status_reg";
0227 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0228 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
0229 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
0230 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
0231 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0232 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0233 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0234 interrupt-names = "spi_lr_fullness_reached",
0235 "spi_lr_session_aborted",
0236 "spi_lr_impatient",
0237 "spi_lr_session_done",
0238 "spi_lr_overhead",
0239 "mspi_done",
0240 "mspi_halted";
0241 num-cs = <2>;
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244
0245 /* partitions defined in board DTS */
0246 };
0247
0248 ccbtimer0: timer@34000 {
0249 compatible = "arm,sp804";
0250 reg = <0x34000 0x1000>;
0251 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0252 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0253 };
0254
0255 ccbtimer1: timer@35000 {
0256 compatible = "arm,sp804";
0257 reg = <0x35000 0x1000>;
0258 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0259 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0260 };
0261
0262 i2c0: i2c@38000 {
0263 compatible = "brcm,iproc-i2c";
0264 reg = <0x38000 0x50>;
0265 #address-cells = <1>;
0266 #size-cells = <0>;
0267 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0268 clock-frequency = <100000>;
0269 };
0270
0271 watchdog: watchdog@39000 {
0272 compatible = "arm,sp805", "arm,primecell";
0273 reg = <0x39000 0x1000>;
0274 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
0275 };
0276
0277 i2c1: i2c@3b000 {
0278 compatible = "brcm,iproc-i2c";
0279 reg = <0x3b000 0x50>;
0280 #address-cells = <1>;
0281 #size-cells = <0>;
0282 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0283 clock-frequency = <100000>;
0284 };
0285 };
0286
0287 pflash: nor@20000000 {
0288 compatible = "cfi-flash", "jedec-flash";
0289 reg = <0x20000000 0x04000000>;
0290 status = "disabled";
0291 #address-cells = <1>;
0292 #size-cells = <1>;
0293
0294 /* partitions defined in board DTS */
0295 };
0296
0297 pcie0: pcie@18012000 {
0298 compatible = "brcm,iproc-pcie";
0299 reg = <0x18012000 0x1000>;
0300
0301 #interrupt-cells = <1>;
0302 interrupt-map-mask = <0 0 0 0>;
0303 interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
0304
0305 linux,pci-domain = <0>;
0306
0307 bus-range = <0x00 0xff>;
0308
0309 #address-cells = <3>;
0310 #size-cells = <2>;
0311 device_type = "pci";
0312
0313 /* Note: The HW does not support I/O resources. So,
0314 * only the memory resource range is being specified.
0315 */
0316 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
0317
0318 status = "disabled";
0319
0320 msi-parent = <&msi0>;
0321 msi0: msi {
0322 compatible = "brcm,iproc-msi";
0323 msi-controller;
0324 interrupt-parent = <&gic>;
0325 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
0327 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
0329 brcm,pcie-msi-inten;
0330 };
0331 };
0332
0333 pcie1: pcie@18013000 {
0334 compatible = "brcm,iproc-pcie";
0335 reg = <0x18013000 0x1000>;
0336
0337 #interrupt-cells = <1>;
0338 interrupt-map-mask = <0 0 0 0>;
0339 interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0340
0341 linux,pci-domain = <1>;
0342
0343 bus-range = <0x00 0xff>;
0344
0345 #address-cells = <3>;
0346 #size-cells = <2>;
0347 device_type = "pci";
0348
0349 /* Note: The HW does not support I/O resources. So,
0350 * only the memory resource range is being specified.
0351 */
0352 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
0353
0354 status = "disabled";
0355
0356 msi-parent = <&msi1>;
0357 msi1: msi {
0358 compatible = "brcm,iproc-msi";
0359 msi-controller;
0360 interrupt-parent = <&gic>;
0361 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
0362 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
0363 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
0364 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
0365 brcm,pcie-msi-inten;
0366 };
0367 };
0368 };
