0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom Corporation nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 #include <dt-bindings/interrupt-controller/arm-gic.h>
0034 #include <dt-bindings/interrupt-controller/irq.h>
0035 #include <dt-bindings/clock/bcm-cygnus.h>
0036
0037 / {
0038 #address-cells = <1>;
0039 #size-cells = <1>;
0040 compatible = "brcm,cygnus";
0041 model = "Broadcom Cygnus SoC";
0042 interrupt-parent = <&gic>;
0043
0044 aliases {
0045 ethernet0 = ð0;
0046 };
0047
0048 memory@0 {
0049 device_type = "memory";
0050 reg = <0 0>;
0051 };
0052
0053 cpus {
0054 #address-cells = <1>;
0055 #size-cells = <0>;
0056
0057 cpu@0 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a9";
0060 next-level-cache = <&L2>;
0061 reg = <0x0>;
0062 };
0063 };
0064
0065 /include/ "bcm-cygnus-clock.dtsi"
0066
0067 pmu {
0068 compatible = "arm,cortex-a9-pmu";
0069 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0070 };
0071
0072 core@19000000 {
0073 compatible = "simple-bus";
0074 ranges = <0x00000000 0x19000000 0x1000000>;
0075 #address-cells = <1>;
0076 #size-cells = <1>;
0077
0078 timer@20200 {
0079 compatible = "arm,cortex-a9-global-timer";
0080 reg = <0x20200 0x100>;
0081 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
0082 clocks = <&periph_clk>;
0083 };
0084
0085 gic: interrupt-controller@21000 {
0086 compatible = "arm,cortex-a9-gic";
0087 #interrupt-cells = <3>;
0088 #address-cells = <0>;
0089 interrupt-controller;
0090 reg = <0x21000 0x1000>,
0091 <0x20100 0x100>;
0092 };
0093
0094 L2: cache-controller@22000 {
0095 compatible = "arm,pl310-cache";
0096 reg = <0x22000 0x1000>;
0097 cache-unified;
0098 cache-level = <2>;
0099 };
0100 };
0101
0102 axi {
0103 compatible = "simple-bus";
0104 ranges;
0105 #address-cells = <1>;
0106 #size-cells = <1>;
0107
0108 otp: otp@301c800 {
0109 compatible = "brcm,ocotp";
0110 reg = <0x0301c800 0x2c>;
0111 brcm,ocotp-size = <2048>;
0112 status = "disabled";
0113 };
0114
0115 pcie_phy: pcie_phy@301d0a0 {
0116 compatible = "brcm,cygnus-pcie-phy";
0117 reg = <0x0301d0a0 0x14>;
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120
0121 pcie0_phy: pcie-phy@0 {
0122 reg = <0>;
0123 #phy-cells = <0>;
0124 };
0125
0126 pcie1_phy: pcie-phy@1 {
0127 reg = <1>;
0128 #phy-cells = <0>;
0129 };
0130 };
0131
0132 pinctrl: pinctrl@301d0c8 {
0133 compatible = "brcm,cygnus-pinmux";
0134 reg = <0x0301d0c8 0x30>,
0135 <0x0301d24c 0x2c>;
0136
0137 spi_0: spi_0 {
0138 function = "spi0";
0139 groups = "spi0_grp";
0140 };
0141
0142 spi_1: spi_1 {
0143 function = "spi1";
0144 groups = "spi1_grp";
0145 };
0146
0147 spi_2: spi_2 {
0148 function = "spi2";
0149 groups = "spi2_grp";
0150 };
0151 };
0152
0153 mailbox: mailbox@3024024 {
0154 compatible = "brcm,iproc-mailbox";
0155 reg = <0x03024024 0x40>;
0156 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0157 #interrupt-cells = <1>;
0158 interrupt-controller;
0159 #mbox-cells = <1>;
0160 };
0161
0162 gpio_crmu: gpio@3024800 {
0163 compatible = "brcm,cygnus-crmu-gpio";
0164 reg = <0x03024800 0x50>,
0165 <0x03024008 0x18>;
0166 ngpios = <6>;
0167 #gpio-cells = <2>;
0168 gpio-controller;
0169 interrupt-controller;
0170 interrupt-parent = <&mailbox>;
0171 interrupts = <0>;
0172 };
0173
0174 mdio: mdio@18002000 {
0175 compatible = "brcm,iproc-mdio";
0176 reg = <0x18002000 0x8>;
0177 #size-cells = <0>;
0178 #address-cells = <1>;
0179 status = "disabled";
0180
0181 gphy0: ethernet-phy@0 {
0182 reg = <0>;
0183 };
0184
0185 gphy1: ethernet-phy@1 {
0186 reg = <1>;
0187 };
0188 };
0189
0190 switch: switch@18007000 {
0191 compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
0192 reg = <0x18007000 0x1000>;
0193 status = "disabled";
0194
0195 ports {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198
0199 port@0 {
0200 reg = <0>;
0201 phy-handle = <&gphy0>;
0202 phy-mode = "rgmii";
0203 };
0204
0205 port@1 {
0206 reg = <1>;
0207 phy-handle = <&gphy1>;
0208 phy-mode = "rgmii";
0209 };
0210
0211 port@8 {
0212 reg = <8>;
0213 label = "cpu";
0214 ethernet = <ð0>;
0215 fixed-link {
0216 speed = <1000>;
0217 full-duplex;
0218 };
0219 };
0220 };
0221 };
0222
0223 i2c0: i2c@18008000 {
0224 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
0225 reg = <0x18008000 0x100>;
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0229 clock-frequency = <100000>;
0230 status = "disabled";
0231 };
0232
0233 wdt0: wdt@18009000 {
0234 compatible = "arm,sp805" , "arm,primecell";
0235 reg = <0x18009000 0x1000>;
0236 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0237 clocks = <&axi81_clk>, <&axi81_clk>;
0238 clock-names = "wdog_clk", "apb_pclk";
0239 };
0240
0241 gpio_ccm: gpio@1800a000 {
0242 compatible = "brcm,cygnus-ccm-gpio";
0243 reg = <0x1800a000 0x50>,
0244 <0x0301d164 0x20>;
0245 ngpios = <24>;
0246 #gpio-cells = <2>;
0247 gpio-controller;
0248 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0249 interrupt-controller;
0250 };
0251
0252 i2c1: i2c@1800b000 {
0253 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
0254 reg = <0x1800b000 0x100>;
0255 #address-cells = <1>;
0256 #size-cells = <0>;
0257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0258 clock-frequency = <100000>;
0259 status = "disabled";
0260 };
0261
0262 pcie0: pcie@18012000 {
0263 compatible = "brcm,iproc-pcie";
0264 reg = <0x18012000 0x1000>;
0265
0266 #interrupt-cells = <1>;
0267 interrupt-map-mask = <0 0 0 0>;
0268 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0269
0270 linux,pci-domain = <0>;
0271
0272 bus-range = <0x00 0xff>;
0273
0274 #address-cells = <3>;
0275 #size-cells = <2>;
0276 device_type = "pci";
0277 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
0278 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
0279
0280 phys = <&pcie0_phy>;
0281 phy-names = "pcie-phy";
0282
0283 status = "disabled";
0284
0285 msi-parent = <&msi0>;
0286 msi0: msi {
0287 compatible = "brcm,iproc-msi";
0288 msi-controller;
0289 interrupt-parent = <&gic>;
0290 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0291 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0293 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0294 };
0295 };
0296
0297 pcie1: pcie@18013000 {
0298 compatible = "brcm,iproc-pcie";
0299 reg = <0x18013000 0x1000>;
0300
0301 #interrupt-cells = <1>;
0302 interrupt-map-mask = <0 0 0 0>;
0303 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0304
0305 linux,pci-domain = <1>;
0306
0307 bus-range = <0x00 0xff>;
0308
0309 #address-cells = <3>;
0310 #size-cells = <2>;
0311 device_type = "pci";
0312 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
0313 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
0314
0315 phys = <&pcie1_phy>;
0316 phy-names = "pcie-phy";
0317
0318 status = "disabled";
0319
0320 msi-parent = <&msi1>;
0321 msi1: msi {
0322 compatible = "brcm,iproc-msi";
0323 msi-controller;
0324 interrupt-parent = <&gic>;
0325 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0327 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0329 };
0330 };
0331
0332 dma0: dma@18018000 {
0333 compatible = "arm,pl330", "arm,primecell";
0334 reg = <0x18018000 0x1000>;
0335 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0336 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0337 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0338 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0339 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0340 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0341 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0342 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0343 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0344 clocks = <&apb_clk>;
0345 clock-names = "apb_pclk";
0346 #dma-cells = <1>;
0347 };
0348
0349 uart0: serial@18020000 {
0350 compatible = "snps,dw-apb-uart";
0351 reg = <0x18020000 0x100>;
0352 reg-shift = <2>;
0353 reg-io-width = <4>;
0354 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0355 clocks = <&axi81_clk>;
0356 clock-frequency = <100000000>;
0357 status = "disabled";
0358 };
0359
0360 uart1: serial@18021000 {
0361 compatible = "snps,dw-apb-uart";
0362 reg = <0x18021000 0x100>;
0363 reg-shift = <2>;
0364 reg-io-width = <4>;
0365 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0366 clocks = <&axi81_clk>;
0367 clock-frequency = <100000000>;
0368 status = "disabled";
0369 };
0370
0371 uart2: serial@18022000 {
0372 compatible = "snps,dw-apb-uart";
0373 reg = <0x18022000 0x100>;
0374 reg-shift = <2>;
0375 reg-io-width = <4>;
0376 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0377 clocks = <&axi81_clk>;
0378 clock-frequency = <100000000>;
0379 status = "disabled";
0380 };
0381
0382 uart3: serial@18023000 {
0383 compatible = "snps,dw-apb-uart";
0384 reg = <0x18023000 0x100>;
0385 reg-shift = <2>;
0386 reg-io-width = <4>;
0387 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0388 clocks = <&axi81_clk>;
0389 clock-frequency = <100000000>;
0390 status = "disabled";
0391 };
0392
0393 spi0: spi@18028000 {
0394 compatible = "arm,pl022", "arm,primecell";
0395 reg = <0x18028000 0x1000>;
0396 #address-cells = <1>;
0397 #size-cells = <0>;
0398 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0399 pinctrl-0 = <&spi_0>;
0400 clocks = <&axi81_clk>, <&axi81_clk>;
0401 clock-names = "sspclk", "apb_pclk";
0402 status = "disabled";
0403 };
0404
0405 spi1: spi@18029000 {
0406 compatible = "arm,pl022", "arm,primecell";
0407 reg = <0x18029000 0x1000>;
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0411 pinctrl-0 = <&spi_1>;
0412 clocks = <&axi81_clk>, <&axi81_clk>;
0413 clock-names = "sspclk", "apb_pclk";
0414 status = "disabled";
0415 };
0416
0417 spi2: spi@1802a000 {
0418 compatible = "arm,pl022", "arm,primecell";
0419 reg = <0x1802a000 0x1000>;
0420 #address-cells = <1>;
0421 #size-cells = <0>;
0422 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0423 pinctrl-0 = <&spi_2>;
0424 clocks = <&axi81_clk>, <&axi81_clk>;
0425 clock-names = "sspclk", "apb_pclk";
0426 status = "disabled";
0427 };
0428
0429 rng: rng@18032000 {
0430 compatible = "brcm,iproc-rng200";
0431 reg = <0x18032000 0x28>;
0432 };
0433
0434 sdhci0: sdhci@18041000 {
0435 compatible = "brcm,sdhci-iproc-cygnus";
0436 reg = <0x18041000 0x100>;
0437 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0438 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
0439 bus-width = <4>;
0440 sdhci,auto-cmd12;
0441 status = "disabled";
0442 };
0443
0444 eth0: ethernet@18042000 {
0445 compatible = "brcm,amac";
0446 reg = <0x18042000 0x1000>,
0447 <0x18110000 0x1000>;
0448 reg-names = "amac_base", "idm_base";
0449 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0450 status = "disabled";
0451 };
0452
0453 sdhci1: sdhci@18043000 {
0454 compatible = "brcm,sdhci-iproc-cygnus";
0455 reg = <0x18043000 0x100>;
0456 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0457 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
0458 bus-width = <4>;
0459 sdhci,auto-cmd12;
0460 status = "disabled";
0461 };
0462
0463 nand_controller: nand-controller@18046000 {
0464 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
0465 reg = <0x18046000 0x600>, <0xf8105408 0x600>,
0466 <0x18046f00 0x20>;
0467 reg-names = "nand", "iproc-idm", "iproc-ext";
0468 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0469
0470 #address-cells = <1>;
0471 #size-cells = <0>;
0472
0473 brcm,nand-has-wp;
0474 };
0475
0476 ehci0: usb@18048000 {
0477 compatible = "generic-ehci";
0478 reg = <0x18048000 0x100>;
0479 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0480 status = "disabled";
0481 };
0482
0483 ohci0: usb@18048800 {
0484 compatible = "generic-ohci";
0485 reg = <0x18048800 0x100>;
0486 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0487 status = "disabled";
0488 };
0489
0490 clcd: clcd@180a0000 {
0491 compatible = "arm,pl111", "arm,primecell";
0492 reg = <0x180a0000 0x1000>;
0493 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0494 interrupt-names = "combined";
0495 clocks = <&axi41_clk>, <&apb_clk>;
0496 clock-names = "clcdclk", "apb_pclk";
0497 status = "disabled";
0498 };
0499
0500 v3d: v3d@180a2000 {
0501 compatible = "brcm,cygnus-v3d";
0502 reg = <0x180a2000 0x1000>;
0503 clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
0504 clock-names = "v3d_clk";
0505 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
0506 status = "disabled";
0507 };
0508
0509 vc4: gpu {
0510 compatible = "brcm,cygnus-vc4";
0511 };
0512
0513 gpio_asiu: gpio@180a5000 {
0514 compatible = "brcm,cygnus-asiu-gpio";
0515 reg = <0x180a5000 0x668>;
0516 ngpios = <146>;
0517 #gpio-cells = <2>;
0518 gpio-controller;
0519
0520 interrupt-controller;
0521 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
0522 gpio-ranges = <&pinctrl 0 42 1>,
0523 <&pinctrl 1 44 3>,
0524 <&pinctrl 4 48 1>,
0525 <&pinctrl 5 50 3>,
0526 <&pinctrl 8 126 1>,
0527 <&pinctrl 9 155 1>,
0528 <&pinctrl 10 152 1>,
0529 <&pinctrl 11 154 1>,
0530 <&pinctrl 12 153 1>,
0531 <&pinctrl 13 127 3>,
0532 <&pinctrl 16 140 1>,
0533 <&pinctrl 17 145 7>,
0534 <&pinctrl 24 130 10>,
0535 <&pinctrl 34 141 4>,
0536 <&pinctrl 38 54 1>,
0537 <&pinctrl 39 56 3>,
0538 <&pinctrl 42 60 3>,
0539 <&pinctrl 45 64 3>,
0540 <&pinctrl 48 68 2>,
0541 <&pinctrl 50 84 6>,
0542 <&pinctrl 56 94 6>,
0543 <&pinctrl 62 72 1>,
0544 <&pinctrl 63 70 1>,
0545 <&pinctrl 64 80 1>,
0546 <&pinctrl 65 74 3>,
0547 <&pinctrl 68 78 1>,
0548 <&pinctrl 69 82 1>,
0549 <&pinctrl 70 156 17>,
0550 <&pinctrl 87 104 12>,
0551 <&pinctrl 99 102 2>,
0552 <&pinctrl 101 90 4>,
0553 <&pinctrl 105 116 6>,
0554 <&pinctrl 111 100 2>,
0555 <&pinctrl 113 122 4>,
0556 <&pinctrl 123 11 1>,
0557 <&pinctrl 124 38 4>,
0558 <&pinctrl 128 43 1>,
0559 <&pinctrl 129 47 1>,
0560 <&pinctrl 130 49 1>,
0561 <&pinctrl 131 53 1>,
0562 <&pinctrl 132 55 1>,
0563 <&pinctrl 133 59 1>,
0564 <&pinctrl 134 63 1>,
0565 <&pinctrl 135 67 1>,
0566 <&pinctrl 136 71 1>,
0567 <&pinctrl 137 73 1>,
0568 <&pinctrl 138 77 1>,
0569 <&pinctrl 139 79 1>,
0570 <&pinctrl 140 81 1>,
0571 <&pinctrl 141 83 1>,
0572 <&pinctrl 142 10 1>;
0573 };
0574
0575 ts_adc_syscon: ts_adc_syscon@180a6000 {
0576 compatible = "brcm,iproc-ts-adc-syscon", "syscon";
0577 reg = <0x180a6000 0xc30>;
0578 };
0579
0580 touchscreen: touchscreen@180a6000 {
0581 compatible = "brcm,iproc-touchscreen";
0582 #address-cells = <1>;
0583 #size-cells = <1>;
0584 ts_syscon = <&ts_adc_syscon>;
0585 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
0586 clock-names = "tsc_clk";
0587 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
0588 status = "disabled";
0589 };
0590
0591 adc: adc@180a6000 {
0592 compatible = "brcm,iproc-static-adc";
0593 #io-channel-cells = <1>;
0594 adc-syscon = <&ts_adc_syscon>;
0595 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
0596 clock-names = "tsc_clk";
0597 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
0598 status = "disabled";
0599 };
0600
0601 pwm: pwm@180aa500 {
0602 compatible = "brcm,kona-pwm";
0603 reg = <0x180aa500 0xc4>;
0604 #pwm-cells = <3>;
0605 clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>;
0606 status = "disabled";
0607 };
0608
0609 keypad: keypad@180ac000 {
0610 compatible = "brcm,bcm-keypad";
0611 reg = <0x180ac000 0x14c>;
0612 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
0613 clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
0614 clock-names = "peri_clk";
0615 clock-frequency = <31250>;
0616 pull-up-enabled;
0617 col-debounce-filter-period = <0>;
0618 status-debounce-filter-period = <0>;
0619 row-output-enabled;
0620 status = "disabled";
0621 };
0622 };
0623 };
