0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom Corporation nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 clocks {
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 ranges;
0037
0038 osc: oscillator {
0039 #clock-cells = <0>;
0040 compatible = "fixed-clock";
0041 clock-frequency = <25000000>;
0042 };
0043
0044 /* Cygnus ARM PLL */
0045 armpll: armpll@19000000 {
0046 #clock-cells = <0>;
0047 compatible = "brcm,cygnus-armpll";
0048 clocks = <&osc>;
0049 reg = <0x19000000 0x1000>;
0050 };
0051
0052 /* peripheral clock for system timer */
0053 periph_clk: arm_periph_clk {
0054 #clock-cells = <0>;
0055 compatible = "fixed-factor-clock";
0056 clocks = <&armpll>;
0057 clock-div = <2>;
0058 clock-mult = <1>;
0059 };
0060
0061 /* APB bus clock */
0062 apb_clk: apb_clk {
0063 #clock-cells = <0>;
0064 compatible = "fixed-factor-clock";
0065 clocks = <&armpll>;
0066 clock-div = <4>;
0067 clock-mult = <1>;
0068 };
0069
0070 genpll: genpll@301d000 {
0071 #clock-cells = <1>;
0072 compatible = "brcm,cygnus-genpll";
0073 reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
0074 clocks = <&osc>;
0075 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
0076 "enet_sw", "audio_125", "can";
0077 };
0078
0079 /* always 1/2 of the axi21 clock */
0080 axi41_clk: axi41_clk {
0081 #clock-cells = <0>;
0082 compatible = "fixed-factor-clock";
0083 clocks = <&genpll 1>;
0084 clock-div = <2>;
0085 clock-mult = <1>;
0086 };
0087
0088 /* always 1/4 of the axi21 clock */
0089 axi81_clk: axi81_clk {
0090 #clock-cells = <0>;
0091 compatible = "fixed-factor-clock";
0092 clocks = <&genpll 1>;
0093 clock-div = <4>;
0094 clock-mult = <1>;
0095 };
0096
0097 lcpll0: lcpll0@301d02c {
0098 #clock-cells = <1>;
0099 compatible = "brcm,cygnus-lcpll0";
0100 reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
0101 clocks = <&osc>;
0102 clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
0103 "usb_phy", "smart_card", "ch5";
0104 };
0105
0106 mipipll: mipipll@180a9800 {
0107 #clock-cells = <1>;
0108 compatible = "brcm,cygnus-mipipll";
0109 reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
0110 clocks = <&osc>;
0111 clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
0112 "ch2_v3d", "ch3_unused", "ch4_unused",
0113 "ch5_unused";
0114 };
0115
0116 asiu_clks: asiu_clks@301d048 {
0117 #clock-cells = <1>;
0118 compatible = "brcm,cygnus-asiu-clk";
0119 reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
0120
0121 clocks = <&osc>;
0122 clock-output-names = "keypad", "adc/touch", "pwm";
0123 };
0124
0125 audiopll: audiopll@180aeb00 {
0126 #clock-cells = <1>;
0127 compatible = "brcm,cygnus-audiopll";
0128 reg = <0x180aeb00 0x68>;
0129 clocks = <&osc>;
0130 clock-output-names = "audiopll", "ch0_audio",
0131 "ch1_audio", "ch2_audio";
0132 };
0133 };
