0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * arch/arm/boot/dts/axm55xx.dtsi
0004 *
0005 * Copyright (C) 2013 LSI
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/lsi,axm5516-clks.h>
0010
0011 / {
0012 #address-cells = <2>;
0013 #size-cells = <2>;
0014 interrupt-parent = <&gic>;
0015
0016 aliases {
0017 serial0 = &serial0;
0018 serial1 = &serial1;
0019 serial2 = &serial2;
0020 serial3 = &serial3;
0021 timer = &timer0;
0022 };
0023
0024 clocks {
0025 compatible = "simple-bus";
0026 #address-cells = <2>;
0027 #size-cells = <2>;
0028 ranges;
0029
0030 clk_ref0: clk_ref0 {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <125000000>;
0034 };
0035
0036 clk_ref1: clk_ref1 {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <125000000>;
0040 };
0041
0042 clk_ref2: clk_ref2 {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 clock-frequency = <125000000>;
0046 };
0047
0048 clks: clock-controller@2010020000 {
0049 compatible = "lsi,axm5516-clks";
0050 #clock-cells = <1>;
0051 reg = <0x20 0x10020000 0 0x20000>;
0052 };
0053 };
0054
0055 gic: interrupt-controller@2001001000 {
0056 compatible = "arm,cortex-a15-gic";
0057 #interrupt-cells = <3>;
0058 #address-cells = <0>;
0059 interrupt-controller;
0060 reg = <0x20 0x01001000 0 0x1000>,
0061 <0x20 0x01002000 0 0x2000>,
0062 <0x20 0x01004000 0 0x2000>,
0063 <0x20 0x01006000 0 0x2000>;
0064 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
0065 IRQ_TYPE_LEVEL_HIGH)>;
0066 };
0067
0068 timer {
0069 compatible = "arm,armv7-timer";
0070 interrupts =
0071 <GIC_PPI 13
0072 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0073 <GIC_PPI 14
0074 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0075 <GIC_PPI 11
0076 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0077 <GIC_PPI 10
0078 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0079 };
0080
0081
0082 pmu {
0083 compatible = "arm,cortex-a15-pmu";
0084 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0085 };
0086
0087 soc {
0088 compatible = "simple-bus";
0089 device_type = "soc";
0090 #address-cells = <2>;
0091 #size-cells = <2>;
0092 interrupt-parent = <&gic>;
0093 ranges;
0094
0095 syscon: syscon@2010030000 {
0096 compatible = "lsi,axxia-syscon", "syscon";
0097 reg = <0x20 0x10030000 0 0x2000>;
0098 };
0099
0100 reset: reset@2010031000 {
0101 compatible = "lsi,axm55xx-reset";
0102 syscon = <&syscon>;
0103 };
0104
0105 amba {
0106 compatible = "simple-bus";
0107 #address-cells = <2>;
0108 #size-cells = <2>;
0109 ranges;
0110
0111 serial0: uart@2010080000 {
0112 compatible = "arm,pl011", "arm,primecell";
0113 reg = <0x20 0x10080000 0 0x1000>;
0114 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0115 clocks = <&clks AXXIA_CLK_PER>;
0116 clock-names = "apb_pclk";
0117 status = "disabled";
0118 };
0119
0120 serial1: uart@2010081000 {
0121 compatible = "arm,pl011", "arm,primecell";
0122 reg = <0x20 0x10081000 0 0x1000>;
0123 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0124 clocks = <&clks AXXIA_CLK_PER>;
0125 clock-names = "apb_pclk";
0126 status = "disabled";
0127 };
0128
0129 serial2: uart@2010082000 {
0130 compatible = "arm,pl011", "arm,primecell";
0131 reg = <0x20 0x10082000 0 0x1000>;
0132 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0133 clocks = <&clks AXXIA_CLK_PER>;
0134 clock-names = "apb_pclk";
0135 status = "disabled";
0136 };
0137
0138 serial3: uart@2010083000 {
0139 compatible = "arm,pl011", "arm,primecell";
0140 reg = <0x20 0x10083000 0 0x1000>;
0141 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0142 clocks = <&clks AXXIA_CLK_PER>;
0143 clock-names = "apb_pclk";
0144 status = "disabled";
0145 };
0146
0147 timer0: timer@2010091000 {
0148 compatible = "arm,sp804", "arm,primecell";
0149 reg = <0x20 0x10091000 0 0x1000>;
0150 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0159 clocks = <&clks AXXIA_CLK_PER>;
0160 clock-names = "apb_pclk";
0161 status = "okay";
0162 };
0163
0164 gpio0: gpio@2010092000 {
0165 #gpio-cells = <2>;
0166 compatible = "arm,pl061", "arm,primecell";
0167 gpio-controller;
0168 reg = <0x20 0x10092000 0x00 0x1000>;
0169 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0170 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0173 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0175 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0177 clocks = <&clks AXXIA_CLK_PER>;
0178 clock-names = "apb_pclk";
0179 status = "disabled";
0180 };
0181
0182 gpio1: gpio@2010093000 {
0183 #gpio-cells = <2>;
0184 compatible = "arm,pl061", "arm,primecell";
0185 gpio-controller;
0186 reg = <0x20 0x10093000 0x00 0x1000>;
0187 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0188 clocks = <&clks AXXIA_CLK_PER>;
0189 clock-names = "apb_pclk";
0190 status = "disabled";
0191 };
0192 };
0193 };
0194 };
0195
0196 /*
0197 Local Variables:
0198 mode: C
0199 End:
0200 */
