0001 // SPDX-License-Identifier: GPL-2.0+
0002 #include <dt-bindings/clock/aspeed-clock.h>
0003 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
0004
0005 / {
0006 model = "Aspeed BMC";
0007 compatible = "aspeed,ast2500";
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 interrupt-parent = <&vic>;
0011
0012 aliases {
0013 i2c0 = &i2c0;
0014 i2c1 = &i2c1;
0015 i2c2 = &i2c2;
0016 i2c3 = &i2c3;
0017 i2c4 = &i2c4;
0018 i2c5 = &i2c5;
0019 i2c6 = &i2c6;
0020 i2c7 = &i2c7;
0021 i2c8 = &i2c8;
0022 i2c9 = &i2c9;
0023 i2c10 = &i2c10;
0024 i2c11 = &i2c11;
0025 i2c12 = &i2c12;
0026 i2c13 = &i2c13;
0027 serial0 = &uart1;
0028 serial1 = &uart2;
0029 serial2 = &uart3;
0030 serial3 = &uart4;
0031 serial4 = &uart5;
0032 serial5 = &vuart;
0033 };
0034
0035 cpus {
0036 #address-cells = <1>;
0037 #size-cells = <0>;
0038
0039 cpu@0 {
0040 compatible = "arm,arm1176jzf-s";
0041 device_type = "cpu";
0042 reg = <0>;
0043 };
0044 };
0045
0046 memory@80000000 {
0047 device_type = "memory";
0048 reg = <0x80000000 0>;
0049 };
0050
0051 ahb {
0052 compatible = "simple-bus";
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055 ranges;
0056
0057 fmc: spi@1e620000 {
0058 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
0059 #address-cells = <1>;
0060 #size-cells = <0>;
0061 compatible = "aspeed,ast2500-fmc";
0062 clocks = <&syscon ASPEED_CLK_AHB>;
0063 status = "disabled";
0064 interrupts = <19>;
0065 flash@0 {
0066 reg = < 0 >;
0067 compatible = "jedec,spi-nor";
0068 spi-max-frequency = <50000000>;
0069 spi-rx-bus-width = <2>;
0070 status = "disabled";
0071 };
0072 flash@1 {
0073 reg = < 1 >;
0074 compatible = "jedec,spi-nor";
0075 spi-max-frequency = <50000000>;
0076 spi-rx-bus-width = <2>;
0077 status = "disabled";
0078 };
0079 flash@2 {
0080 reg = < 2 >;
0081 compatible = "jedec,spi-nor";
0082 spi-max-frequency = <50000000>;
0083 spi-rx-bus-width = <2>;
0084 status = "disabled";
0085 };
0086 };
0087
0088 spi1: spi@1e630000 {
0089 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
0090 #address-cells = <1>;
0091 #size-cells = <0>;
0092 compatible = "aspeed,ast2500-spi";
0093 clocks = <&syscon ASPEED_CLK_AHB>;
0094 status = "disabled";
0095 flash@0 {
0096 reg = < 0 >;
0097 compatible = "jedec,spi-nor";
0098 spi-max-frequency = <50000000>;
0099 spi-rx-bus-width = <2>;
0100 status = "disabled";
0101 };
0102 flash@1 {
0103 reg = < 1 >;
0104 compatible = "jedec,spi-nor";
0105 spi-max-frequency = <50000000>;
0106 spi-rx-bus-width = <2>;
0107 status = "disabled";
0108 };
0109 };
0110
0111 spi2: spi@1e631000 {
0112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
0113 #address-cells = <1>;
0114 #size-cells = <0>;
0115 compatible = "aspeed,ast2500-spi";
0116 clocks = <&syscon ASPEED_CLK_AHB>;
0117 status = "disabled";
0118 flash@0 {
0119 reg = < 0 >;
0120 compatible = "jedec,spi-nor";
0121 spi-max-frequency = <50000000>;
0122 spi-rx-bus-width = <2>;
0123 status = "disabled";
0124 };
0125 flash@1 {
0126 reg = < 1 >;
0127 compatible = "jedec,spi-nor";
0128 spi-max-frequency = <50000000>;
0129 spi-rx-bus-width = <2>;
0130 status = "disabled";
0131 };
0132 };
0133
0134 vic: interrupt-controller@1e6c0080 {
0135 compatible = "aspeed,ast2400-vic";
0136 interrupt-controller;
0137 #interrupt-cells = <1>;
0138 valid-sources = <0xfefff7ff 0x0807ffff>;
0139 reg = <0x1e6c0080 0x80>;
0140 };
0141
0142 cvic: copro-interrupt-controller@1e6c2000 {
0143 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
0144 valid-sources = <0xffffffff>;
0145 copro-sw-interrupts = <1>;
0146 reg = <0x1e6c2000 0x80>;
0147 };
0148
0149 mac0: ethernet@1e660000 {
0150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
0151 reg = <0x1e660000 0x180>;
0152 interrupts = <2>;
0153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
0154 status = "disabled";
0155 };
0156
0157 mac1: ethernet@1e680000 {
0158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
0159 reg = <0x1e680000 0x180>;
0160 interrupts = <3>;
0161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
0162 status = "disabled";
0163 };
0164
0165 ehci0: usb@1e6a1000 {
0166 compatible = "aspeed,ast2500-ehci", "generic-ehci";
0167 reg = <0x1e6a1000 0x100>;
0168 interrupts = <5>;
0169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
0170 pinctrl-names = "default";
0171 pinctrl-0 = <&pinctrl_usb2ah_default>;
0172 status = "disabled";
0173 };
0174
0175 ehci1: usb@1e6a3000 {
0176 compatible = "aspeed,ast2500-ehci", "generic-ehci";
0177 reg = <0x1e6a3000 0x100>;
0178 interrupts = <13>;
0179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&pinctrl_usb2bh_default>;
0182 status = "disabled";
0183 };
0184
0185 uhci: usb@1e6b0000 {
0186 compatible = "aspeed,ast2500-uhci", "generic-uhci";
0187 reg = <0x1e6b0000 0x100>;
0188 interrupts = <14>;
0189 #ports = <2>;
0190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
0191 status = "disabled";
0192 /*
0193 * No default pinmux, it will follow EHCI, use an explicit pinmux
0194 * override if you don't enable EHCI
0195 */
0196 };
0197
0198 vhub: usb-vhub@1e6a0000 {
0199 compatible = "aspeed,ast2500-usb-vhub";
0200 reg = <0x1e6a0000 0x300>;
0201 interrupts = <5>;
0202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
0203 aspeed,vhub-downstream-ports = <5>;
0204 aspeed,vhub-generic-endpoints = <15>;
0205 pinctrl-names = "default";
0206 pinctrl-0 = <&pinctrl_usb2ad_default>;
0207 status = "disabled";
0208 };
0209
0210 apb {
0211 compatible = "simple-bus";
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 ranges;
0215
0216 edac: memory-controller@1e6e0000 {
0217 compatible = "aspeed,ast2500-sdram-edac";
0218 reg = <0x1e6e0000 0x174>;
0219 interrupts = <0>;
0220 status = "disabled";
0221 };
0222
0223 syscon: syscon@1e6e2000 {
0224 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
0225 reg = <0x1e6e2000 0x1a8>;
0226 #address-cells = <1>;
0227 #size-cells = <1>;
0228 ranges = <0 0x1e6e2000 0x1000>;
0229 #clock-cells = <1>;
0230 #reset-cells = <1>;
0231
0232 scu_ic: interrupt-controller@18 {
0233 #interrupt-cells = <1>;
0234 compatible = "aspeed,ast2500-scu-ic";
0235 reg = <0x18 0x4>;
0236 interrupts = <21>;
0237 interrupt-controller;
0238 };
0239
0240 p2a: p2a-control@2c {
0241 compatible = "aspeed,ast2500-p2a-ctrl";
0242 reg = <0x2c 0x4>;
0243 status = "disabled";
0244 };
0245
0246 silicon-id@7c {
0247 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
0248 reg = <0x7c 0x4 0x150 0x8>;
0249 };
0250
0251 pinctrl: pinctrl@80 {
0252 compatible = "aspeed,ast2500-pinctrl";
0253 reg = <0x80 0x18>, <0xa0 0x10>;
0254 aspeed,external-nodes = <&gfx>, <&lhc>;
0255 };
0256 };
0257
0258 rng: hwrng@1e6e2078 {
0259 compatible = "timeriomem_rng";
0260 reg = <0x1e6e2078 0x4>;
0261 period = <1>;
0262 quality = <100>;
0263 };
0264
0265 gfx: display@1e6e6000 {
0266 compatible = "aspeed,ast2500-gfx", "syscon";
0267 reg = <0x1e6e6000 0x1000>;
0268 reg-io-width = <4>;
0269 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
0270 resets = <&syscon ASPEED_RESET_CRT1>;
0271 syscon = <&syscon>;
0272 status = "disabled";
0273 interrupts = <0x19>;
0274 };
0275
0276 xdma: xdma@1e6e7000 {
0277 compatible = "aspeed,ast2500-xdma";
0278 reg = <0x1e6e7000 0x100>;
0279 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
0280 resets = <&syscon ASPEED_RESET_XDMA>;
0281 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
0282 aspeed,pcie-device = "bmc";
0283 aspeed,scu = <&syscon>;
0284 status = "disabled";
0285 };
0286
0287 adc: adc@1e6e9000 {
0288 compatible = "aspeed,ast2500-adc";
0289 reg = <0x1e6e9000 0xb0>;
0290 clocks = <&syscon ASPEED_CLK_APB>;
0291 resets = <&syscon ASPEED_RESET_ADC>;
0292 #io-channel-cells = <1>;
0293 status = "disabled";
0294 };
0295
0296 video: video@1e700000 {
0297 compatible = "aspeed,ast2500-video-engine";
0298 reg = <0x1e700000 0x1000>;
0299 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
0300 <&syscon ASPEED_CLK_GATE_ECLK>;
0301 clock-names = "vclk", "eclk";
0302 interrupts = <7>;
0303 status = "disabled";
0304 };
0305
0306 sram: sram@1e720000 {
0307 compatible = "mmio-sram";
0308 reg = <0x1e720000 0x9000>; // 36K
0309 };
0310
0311 sdmmc: sd-controller@1e740000 {
0312 compatible = "aspeed,ast2500-sd-controller";
0313 reg = <0x1e740000 0x100>;
0314 #address-cells = <1>;
0315 #size-cells = <1>;
0316 ranges = <0 0x1e740000 0x10000>;
0317 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
0318 status = "disabled";
0319
0320 sdhci0: sdhci@100 {
0321 compatible = "aspeed,ast2500-sdhci";
0322 reg = <0x100 0x100>;
0323 interrupts = <26>;
0324 sdhci,auto-cmd12;
0325 clocks = <&syscon ASPEED_CLK_SDIO>;
0326 status = "disabled";
0327 };
0328
0329 sdhci1: sdhci@200 {
0330 compatible = "aspeed,ast2500-sdhci";
0331 reg = <0x200 0x100>;
0332 interrupts = <26>;
0333 sdhci,auto-cmd12;
0334 clocks = <&syscon ASPEED_CLK_SDIO>;
0335 status = "disabled";
0336 };
0337 };
0338
0339 gpio: gpio@1e780000 {
0340 #gpio-cells = <2>;
0341 gpio-controller;
0342 compatible = "aspeed,ast2500-gpio";
0343 reg = <0x1e780000 0x200>;
0344 interrupts = <20>;
0345 gpio-ranges = <&pinctrl 0 0 232>;
0346 clocks = <&syscon ASPEED_CLK_APB>;
0347 interrupt-controller;
0348 #interrupt-cells = <2>;
0349 };
0350
0351 sgpio: sgpio@1e780200 {
0352 #gpio-cells = <2>;
0353 compatible = "aspeed,ast2500-sgpio";
0354 gpio-controller;
0355 interrupts = <40>;
0356 reg = <0x1e780200 0x0100>;
0357 clocks = <&syscon ASPEED_CLK_APB>;
0358 interrupt-controller;
0359 bus-frequency = <12000000>;
0360 pinctrl-names = "default";
0361 pinctrl-0 = <&pinctrl_sgpm_default>;
0362 status = "disabled";
0363 };
0364
0365 rtc: rtc@1e781000 {
0366 compatible = "aspeed,ast2500-rtc";
0367 reg = <0x1e781000 0x18>;
0368 status = "disabled";
0369 };
0370
0371 timer: timer@1e782000 {
0372 /* This timer is a Faraday FTTMR010 derivative */
0373 compatible = "aspeed,ast2400-timer";
0374 reg = <0x1e782000 0x90>;
0375 interrupts = <16 17 18 35 36 37 38 39>;
0376 clocks = <&syscon ASPEED_CLK_APB>;
0377 clock-names = "PCLK";
0378 };
0379
0380 uart1: serial@1e783000 {
0381 compatible = "ns16550a";
0382 reg = <0x1e783000 0x20>;
0383 reg-shift = <2>;
0384 interrupts = <9>;
0385 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
0386 resets = <&lpc_reset 4>;
0387 no-loopback-test;
0388 status = "disabled";
0389 };
0390
0391 uart5: serial@1e784000 {
0392 compatible = "ns16550a";
0393 reg = <0x1e784000 0x20>;
0394 reg-shift = <2>;
0395 interrupts = <10>;
0396 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
0397 no-loopback-test;
0398 status = "disabled";
0399 };
0400
0401 wdt1: watchdog@1e785000 {
0402 compatible = "aspeed,ast2500-wdt";
0403 reg = <0x1e785000 0x20>;
0404 clocks = <&syscon ASPEED_CLK_APB>;
0405 };
0406
0407 wdt2: watchdog@1e785020 {
0408 compatible = "aspeed,ast2500-wdt";
0409 reg = <0x1e785020 0x20>;
0410 clocks = <&syscon ASPEED_CLK_APB>;
0411 };
0412
0413 wdt3: watchdog@1e785040 {
0414 compatible = "aspeed,ast2500-wdt";
0415 reg = <0x1e785040 0x20>;
0416 clocks = <&syscon ASPEED_CLK_APB>;
0417 status = "disabled";
0418 };
0419
0420 pwm_tacho: pwm-tacho-controller@1e786000 {
0421 compatible = "aspeed,ast2500-pwm-tacho";
0422 #address-cells = <1>;
0423 #size-cells = <0>;
0424 reg = <0x1e786000 0x1000>;
0425 clocks = <&syscon ASPEED_CLK_24M>;
0426 resets = <&syscon ASPEED_RESET_PWM>;
0427 status = "disabled";
0428 };
0429
0430 vuart: serial@1e787000 {
0431 compatible = "aspeed,ast2500-vuart";
0432 reg = <0x1e787000 0x40>;
0433 reg-shift = <2>;
0434 interrupts = <8>;
0435 clocks = <&syscon ASPEED_CLK_APB>;
0436 no-loopback-test;
0437 status = "disabled";
0438 };
0439
0440 lpc: lpc@1e789000 {
0441 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
0442 reg = <0x1e789000 0x1000>;
0443 reg-io-width = <4>;
0444
0445 #address-cells = <1>;
0446 #size-cells = <1>;
0447 ranges = <0x0 0x1e789000 0x1000>;
0448
0449 kcs1: kcs@24 {
0450 compatible = "aspeed,ast2500-kcs-bmc-v2";
0451 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
0452 interrupts = <8>;
0453 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0454 status = "disabled";
0455 };
0456
0457 kcs2: kcs@28 {
0458 compatible = "aspeed,ast2500-kcs-bmc-v2";
0459 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
0460 interrupts = <8>;
0461 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0462 status = "disabled";
0463 };
0464
0465 kcs3: kcs@2c {
0466 compatible = "aspeed,ast2500-kcs-bmc-v2";
0467 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
0468 interrupts = <8>;
0469 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0470 status = "disabled";
0471 };
0472
0473 kcs4: kcs@114 {
0474 compatible = "aspeed,ast2500-kcs-bmc-v2";
0475 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
0476 interrupts = <8>;
0477 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0478 status = "disabled";
0479 };
0480
0481 lpc_ctrl: lpc-ctrl@80 {
0482 compatible = "aspeed,ast2500-lpc-ctrl";
0483 reg = <0x80 0x10>;
0484 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0485 status = "disabled";
0486 };
0487
0488 lpc_snoop: lpc-snoop@90 {
0489 compatible = "aspeed,ast2500-lpc-snoop";
0490 reg = <0x90 0x8>;
0491 interrupts = <8>;
0492 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0493 status = "disabled";
0494 };
0495
0496 lpc_reset: reset-controller@98 {
0497 compatible = "aspeed,ast2500-lpc-reset";
0498 reg = <0x98 0x4>;
0499 #reset-cells = <1>;
0500 };
0501
0502 uart_routing: uart-routing@9c {
0503 compatible = "aspeed,ast2500-uart-routing";
0504 reg = <0x9c 0x4>;
0505 status = "disabled";
0506 };
0507
0508 lhc: lhc@a0 {
0509 compatible = "aspeed,ast2500-lhc";
0510 reg = <0xa0 0x24 0xc8 0x8>;
0511 };
0512
0513
0514 ibt: ibt@140 {
0515 compatible = "aspeed,ast2500-ibt-bmc";
0516 reg = <0x140 0x18>;
0517 interrupts = <8>;
0518 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0519 status = "disabled";
0520 };
0521 };
0522
0523 peci0: peci-controller@1e78b000 {
0524 compatible = "aspeed,ast2500-peci";
0525 reg = <0x1e78b000 0x60>;
0526 interrupts = <15>;
0527 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
0528 resets = <&syscon ASPEED_RESET_PECI>;
0529 cmd-timeout-ms = <1000>;
0530 clock-frequency = <1000000>;
0531 status = "disabled";
0532 };
0533
0534 uart2: serial@1e78d000 {
0535 compatible = "ns16550a";
0536 reg = <0x1e78d000 0x20>;
0537 reg-shift = <2>;
0538 interrupts = <32>;
0539 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
0540 resets = <&lpc_reset 5>;
0541 no-loopback-test;
0542 status = "disabled";
0543 };
0544
0545 uart3: serial@1e78e000 {
0546 compatible = "ns16550a";
0547 reg = <0x1e78e000 0x20>;
0548 reg-shift = <2>;
0549 interrupts = <33>;
0550 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
0551 resets = <&lpc_reset 6>;
0552 no-loopback-test;
0553 status = "disabled";
0554 };
0555
0556 uart4: serial@1e78f000 {
0557 compatible = "ns16550a";
0558 reg = <0x1e78f000 0x20>;
0559 reg-shift = <2>;
0560 interrupts = <34>;
0561 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
0562 resets = <&lpc_reset 7>;
0563 no-loopback-test;
0564 status = "disabled";
0565 };
0566
0567 i2c: bus@1e78a000 {
0568 compatible = "simple-bus";
0569 #address-cells = <1>;
0570 #size-cells = <1>;
0571 ranges = <0 0x1e78a000 0x1000>;
0572 };
0573 };
0574 };
0575 };
0576
0577 &i2c {
0578 i2c_ic: interrupt-controller@0 {
0579 #interrupt-cells = <1>;
0580 compatible = "aspeed,ast2500-i2c-ic";
0581 reg = <0x0 0x40>;
0582 interrupts = <12>;
0583 interrupt-controller;
0584 };
0585
0586 i2c0: i2c-bus@40 {
0587 #address-cells = <1>;
0588 #size-cells = <0>;
0589 #interrupt-cells = <1>;
0590
0591 reg = <0x40 0x40>;
0592 compatible = "aspeed,ast2500-i2c-bus";
0593 clocks = <&syscon ASPEED_CLK_APB>;
0594 resets = <&syscon ASPEED_RESET_I2C>;
0595 bus-frequency = <100000>;
0596 interrupts = <0>;
0597 interrupt-parent = <&i2c_ic>;
0598 status = "disabled";
0599 /* Does not need pinctrl properties */
0600 };
0601
0602 i2c1: i2c-bus@80 {
0603 #address-cells = <1>;
0604 #size-cells = <0>;
0605 #interrupt-cells = <1>;
0606
0607 reg = <0x80 0x40>;
0608 compatible = "aspeed,ast2500-i2c-bus";
0609 clocks = <&syscon ASPEED_CLK_APB>;
0610 resets = <&syscon ASPEED_RESET_I2C>;
0611 bus-frequency = <100000>;
0612 interrupts = <1>;
0613 interrupt-parent = <&i2c_ic>;
0614 status = "disabled";
0615 /* Does not need pinctrl properties */
0616 };
0617
0618 i2c2: i2c-bus@c0 {
0619 #address-cells = <1>;
0620 #size-cells = <0>;
0621 #interrupt-cells = <1>;
0622
0623 reg = <0xc0 0x40>;
0624 compatible = "aspeed,ast2500-i2c-bus";
0625 clocks = <&syscon ASPEED_CLK_APB>;
0626 resets = <&syscon ASPEED_RESET_I2C>;
0627 bus-frequency = <100000>;
0628 interrupts = <2>;
0629 interrupt-parent = <&i2c_ic>;
0630 pinctrl-names = "default";
0631 pinctrl-0 = <&pinctrl_i2c3_default>;
0632 status = "disabled";
0633 };
0634
0635 i2c3: i2c-bus@100 {
0636 #address-cells = <1>;
0637 #size-cells = <0>;
0638 #interrupt-cells = <1>;
0639
0640 reg = <0x100 0x40>;
0641 compatible = "aspeed,ast2500-i2c-bus";
0642 clocks = <&syscon ASPEED_CLK_APB>;
0643 resets = <&syscon ASPEED_RESET_I2C>;
0644 bus-frequency = <100000>;
0645 interrupts = <3>;
0646 interrupt-parent = <&i2c_ic>;
0647 pinctrl-names = "default";
0648 pinctrl-0 = <&pinctrl_i2c4_default>;
0649 status = "disabled";
0650 };
0651
0652 i2c4: i2c-bus@140 {
0653 #address-cells = <1>;
0654 #size-cells = <0>;
0655 #interrupt-cells = <1>;
0656
0657 reg = <0x140 0x40>;
0658 compatible = "aspeed,ast2500-i2c-bus";
0659 clocks = <&syscon ASPEED_CLK_APB>;
0660 resets = <&syscon ASPEED_RESET_I2C>;
0661 bus-frequency = <100000>;
0662 interrupts = <4>;
0663 interrupt-parent = <&i2c_ic>;
0664 pinctrl-names = "default";
0665 pinctrl-0 = <&pinctrl_i2c5_default>;
0666 status = "disabled";
0667 };
0668
0669 i2c5: i2c-bus@180 {
0670 #address-cells = <1>;
0671 #size-cells = <0>;
0672 #interrupt-cells = <1>;
0673
0674 reg = <0x180 0x40>;
0675 compatible = "aspeed,ast2500-i2c-bus";
0676 clocks = <&syscon ASPEED_CLK_APB>;
0677 resets = <&syscon ASPEED_RESET_I2C>;
0678 bus-frequency = <100000>;
0679 interrupts = <5>;
0680 interrupt-parent = <&i2c_ic>;
0681 pinctrl-names = "default";
0682 pinctrl-0 = <&pinctrl_i2c6_default>;
0683 status = "disabled";
0684 };
0685
0686 i2c6: i2c-bus@1c0 {
0687 #address-cells = <1>;
0688 #size-cells = <0>;
0689 #interrupt-cells = <1>;
0690
0691 reg = <0x1c0 0x40>;
0692 compatible = "aspeed,ast2500-i2c-bus";
0693 clocks = <&syscon ASPEED_CLK_APB>;
0694 resets = <&syscon ASPEED_RESET_I2C>;
0695 bus-frequency = <100000>;
0696 interrupts = <6>;
0697 interrupt-parent = <&i2c_ic>;
0698 pinctrl-names = "default";
0699 pinctrl-0 = <&pinctrl_i2c7_default>;
0700 status = "disabled";
0701 };
0702
0703 i2c7: i2c-bus@300 {
0704 #address-cells = <1>;
0705 #size-cells = <0>;
0706 #interrupt-cells = <1>;
0707
0708 reg = <0x300 0x40>;
0709 compatible = "aspeed,ast2500-i2c-bus";
0710 clocks = <&syscon ASPEED_CLK_APB>;
0711 resets = <&syscon ASPEED_RESET_I2C>;
0712 bus-frequency = <100000>;
0713 interrupts = <7>;
0714 interrupt-parent = <&i2c_ic>;
0715 pinctrl-names = "default";
0716 pinctrl-0 = <&pinctrl_i2c8_default>;
0717 status = "disabled";
0718 };
0719
0720 i2c8: i2c-bus@340 {
0721 #address-cells = <1>;
0722 #size-cells = <0>;
0723 #interrupt-cells = <1>;
0724
0725 reg = <0x340 0x40>;
0726 compatible = "aspeed,ast2500-i2c-bus";
0727 clocks = <&syscon ASPEED_CLK_APB>;
0728 resets = <&syscon ASPEED_RESET_I2C>;
0729 bus-frequency = <100000>;
0730 interrupts = <8>;
0731 interrupt-parent = <&i2c_ic>;
0732 pinctrl-names = "default";
0733 pinctrl-0 = <&pinctrl_i2c9_default>;
0734 status = "disabled";
0735 };
0736
0737 i2c9: i2c-bus@380 {
0738 #address-cells = <1>;
0739 #size-cells = <0>;
0740 #interrupt-cells = <1>;
0741
0742 reg = <0x380 0x40>;
0743 compatible = "aspeed,ast2500-i2c-bus";
0744 clocks = <&syscon ASPEED_CLK_APB>;
0745 resets = <&syscon ASPEED_RESET_I2C>;
0746 bus-frequency = <100000>;
0747 interrupts = <9>;
0748 interrupt-parent = <&i2c_ic>;
0749 pinctrl-names = "default";
0750 pinctrl-0 = <&pinctrl_i2c10_default>;
0751 status = "disabled";
0752 };
0753
0754 i2c10: i2c-bus@3c0 {
0755 #address-cells = <1>;
0756 #size-cells = <0>;
0757 #interrupt-cells = <1>;
0758
0759 reg = <0x3c0 0x40>;
0760 compatible = "aspeed,ast2500-i2c-bus";
0761 clocks = <&syscon ASPEED_CLK_APB>;
0762 resets = <&syscon ASPEED_RESET_I2C>;
0763 bus-frequency = <100000>;
0764 interrupts = <10>;
0765 interrupt-parent = <&i2c_ic>;
0766 pinctrl-names = "default";
0767 pinctrl-0 = <&pinctrl_i2c11_default>;
0768 status = "disabled";
0769 };
0770
0771 i2c11: i2c-bus@400 {
0772 #address-cells = <1>;
0773 #size-cells = <0>;
0774 #interrupt-cells = <1>;
0775
0776 reg = <0x400 0x40>;
0777 compatible = "aspeed,ast2500-i2c-bus";
0778 clocks = <&syscon ASPEED_CLK_APB>;
0779 resets = <&syscon ASPEED_RESET_I2C>;
0780 bus-frequency = <100000>;
0781 interrupts = <11>;
0782 interrupt-parent = <&i2c_ic>;
0783 pinctrl-names = "default";
0784 pinctrl-0 = <&pinctrl_i2c12_default>;
0785 status = "disabled";
0786 };
0787
0788 i2c12: i2c-bus@440 {
0789 #address-cells = <1>;
0790 #size-cells = <0>;
0791 #interrupt-cells = <1>;
0792
0793 reg = <0x440 0x40>;
0794 compatible = "aspeed,ast2500-i2c-bus";
0795 clocks = <&syscon ASPEED_CLK_APB>;
0796 resets = <&syscon ASPEED_RESET_I2C>;
0797 bus-frequency = <100000>;
0798 interrupts = <12>;
0799 interrupt-parent = <&i2c_ic>;
0800 pinctrl-names = "default";
0801 pinctrl-0 = <&pinctrl_i2c13_default>;
0802 status = "disabled";
0803 };
0804
0805 i2c13: i2c-bus@480 {
0806 #address-cells = <1>;
0807 #size-cells = <0>;
0808 #interrupt-cells = <1>;
0809
0810 reg = <0x480 0x40>;
0811 compatible = "aspeed,ast2500-i2c-bus";
0812 clocks = <&syscon ASPEED_CLK_APB>;
0813 resets = <&syscon ASPEED_RESET_I2C>;
0814 bus-frequency = <100000>;
0815 interrupts = <13>;
0816 interrupt-parent = <&i2c_ic>;
0817 pinctrl-names = "default";
0818 pinctrl-0 = <&pinctrl_i2c14_default>;
0819 status = "disabled";
0820 };
0821 };
0822
0823 &pinctrl {
0824 pinctrl_acpi_default: acpi_default {
0825 function = "ACPI";
0826 groups = "ACPI";
0827 };
0828
0829 pinctrl_adc0_default: adc0_default {
0830 function = "ADC0";
0831 groups = "ADC0";
0832 };
0833
0834 pinctrl_adc1_default: adc1_default {
0835 function = "ADC1";
0836 groups = "ADC1";
0837 };
0838
0839 pinctrl_adc10_default: adc10_default {
0840 function = "ADC10";
0841 groups = "ADC10";
0842 };
0843
0844 pinctrl_adc11_default: adc11_default {
0845 function = "ADC11";
0846 groups = "ADC11";
0847 };
0848
0849 pinctrl_adc12_default: adc12_default {
0850 function = "ADC12";
0851 groups = "ADC12";
0852 };
0853
0854 pinctrl_adc13_default: adc13_default {
0855 function = "ADC13";
0856 groups = "ADC13";
0857 };
0858
0859 pinctrl_adc14_default: adc14_default {
0860 function = "ADC14";
0861 groups = "ADC14";
0862 };
0863
0864 pinctrl_adc15_default: adc15_default {
0865 function = "ADC15";
0866 groups = "ADC15";
0867 };
0868
0869 pinctrl_adc2_default: adc2_default {
0870 function = "ADC2";
0871 groups = "ADC2";
0872 };
0873
0874 pinctrl_adc3_default: adc3_default {
0875 function = "ADC3";
0876 groups = "ADC3";
0877 };
0878
0879 pinctrl_adc4_default: adc4_default {
0880 function = "ADC4";
0881 groups = "ADC4";
0882 };
0883
0884 pinctrl_adc5_default: adc5_default {
0885 function = "ADC5";
0886 groups = "ADC5";
0887 };
0888
0889 pinctrl_adc6_default: adc6_default {
0890 function = "ADC6";
0891 groups = "ADC6";
0892 };
0893
0894 pinctrl_adc7_default: adc7_default {
0895 function = "ADC7";
0896 groups = "ADC7";
0897 };
0898
0899 pinctrl_adc8_default: adc8_default {
0900 function = "ADC8";
0901 groups = "ADC8";
0902 };
0903
0904 pinctrl_adc9_default: adc9_default {
0905 function = "ADC9";
0906 groups = "ADC9";
0907 };
0908
0909 pinctrl_bmcint_default: bmcint_default {
0910 function = "BMCINT";
0911 groups = "BMCINT";
0912 };
0913
0914 pinctrl_ddcclk_default: ddcclk_default {
0915 function = "DDCCLK";
0916 groups = "DDCCLK";
0917 };
0918
0919 pinctrl_ddcdat_default: ddcdat_default {
0920 function = "DDCDAT";
0921 groups = "DDCDAT";
0922 };
0923
0924 pinctrl_espi_default: espi_default {
0925 function = "ESPI";
0926 groups = "ESPI";
0927 };
0928
0929 pinctrl_fwspics1_default: fwspics1_default {
0930 function = "FWSPICS1";
0931 groups = "FWSPICS1";
0932 };
0933
0934 pinctrl_fwspics2_default: fwspics2_default {
0935 function = "FWSPICS2";
0936 groups = "FWSPICS2";
0937 };
0938
0939 pinctrl_gpid0_default: gpid0_default {
0940 function = "GPID0";
0941 groups = "GPID0";
0942 };
0943
0944 pinctrl_gpid2_default: gpid2_default {
0945 function = "GPID2";
0946 groups = "GPID2";
0947 };
0948
0949 pinctrl_gpid4_default: gpid4_default {
0950 function = "GPID4";
0951 groups = "GPID4";
0952 };
0953
0954 pinctrl_gpid6_default: gpid6_default {
0955 function = "GPID6";
0956 groups = "GPID6";
0957 };
0958
0959 pinctrl_gpie0_default: gpie0_default {
0960 function = "GPIE0";
0961 groups = "GPIE0";
0962 };
0963
0964 pinctrl_gpie2_default: gpie2_default {
0965 function = "GPIE2";
0966 groups = "GPIE2";
0967 };
0968
0969 pinctrl_gpie4_default: gpie4_default {
0970 function = "GPIE4";
0971 groups = "GPIE4";
0972 };
0973
0974 pinctrl_gpie6_default: gpie6_default {
0975 function = "GPIE6";
0976 groups = "GPIE6";
0977 };
0978
0979 pinctrl_i2c10_default: i2c10_default {
0980 function = "I2C10";
0981 groups = "I2C10";
0982 };
0983
0984 pinctrl_i2c11_default: i2c11_default {
0985 function = "I2C11";
0986 groups = "I2C11";
0987 };
0988
0989 pinctrl_i2c12_default: i2c12_default {
0990 function = "I2C12";
0991 groups = "I2C12";
0992 };
0993
0994 pinctrl_i2c13_default: i2c13_default {
0995 function = "I2C13";
0996 groups = "I2C13";
0997 };
0998
0999 pinctrl_i2c14_default: i2c14_default {
1000 function = "I2C14";
1001 groups = "I2C14";
1002 };
1003
1004 pinctrl_i2c3_default: i2c3_default {
1005 function = "I2C3";
1006 groups = "I2C3";
1007 };
1008
1009 pinctrl_i2c4_default: i2c4_default {
1010 function = "I2C4";
1011 groups = "I2C4";
1012 };
1013
1014 pinctrl_i2c5_default: i2c5_default {
1015 function = "I2C5";
1016 groups = "I2C5";
1017 };
1018
1019 pinctrl_i2c6_default: i2c6_default {
1020 function = "I2C6";
1021 groups = "I2C6";
1022 };
1023
1024 pinctrl_i2c7_default: i2c7_default {
1025 function = "I2C7";
1026 groups = "I2C7";
1027 };
1028
1029 pinctrl_i2c8_default: i2c8_default {
1030 function = "I2C8";
1031 groups = "I2C8";
1032 };
1033
1034 pinctrl_i2c9_default: i2c9_default {
1035 function = "I2C9";
1036 groups = "I2C9";
1037 };
1038
1039 pinctrl_lad0_default: lad0_default {
1040 function = "LAD0";
1041 groups = "LAD0";
1042 };
1043
1044 pinctrl_lad1_default: lad1_default {
1045 function = "LAD1";
1046 groups = "LAD1";
1047 };
1048
1049 pinctrl_lad2_default: lad2_default {
1050 function = "LAD2";
1051 groups = "LAD2";
1052 };
1053
1054 pinctrl_lad3_default: lad3_default {
1055 function = "LAD3";
1056 groups = "LAD3";
1057 };
1058
1059 pinctrl_lclk_default: lclk_default {
1060 function = "LCLK";
1061 groups = "LCLK";
1062 };
1063
1064 pinctrl_lframe_default: lframe_default {
1065 function = "LFRAME";
1066 groups = "LFRAME";
1067 };
1068
1069 pinctrl_lpchc_default: lpchc_default {
1070 function = "LPCHC";
1071 groups = "LPCHC";
1072 };
1073
1074 pinctrl_lpcpd_default: lpcpd_default {
1075 function = "LPCPD";
1076 groups = "LPCPD";
1077 };
1078
1079 pinctrl_lpcplus_default: lpcplus_default {
1080 function = "LPCPLUS";
1081 groups = "LPCPLUS";
1082 };
1083
1084 pinctrl_lpcpme_default: lpcpme_default {
1085 function = "LPCPME";
1086 groups = "LPCPME";
1087 };
1088
1089 pinctrl_lpcrst_default: lpcrst_default {
1090 function = "LPCRST";
1091 groups = "LPCRST";
1092 };
1093
1094 pinctrl_lpcsmi_default: lpcsmi_default {
1095 function = "LPCSMI";
1096 groups = "LPCSMI";
1097 };
1098
1099 pinctrl_lsirq_default: lsirq_default {
1100 function = "LSIRQ";
1101 groups = "LSIRQ";
1102 };
1103
1104 pinctrl_mac1link_default: mac1link_default {
1105 function = "MAC1LINK";
1106 groups = "MAC1LINK";
1107 };
1108
1109 pinctrl_mac2link_default: mac2link_default {
1110 function = "MAC2LINK";
1111 groups = "MAC2LINK";
1112 };
1113
1114 pinctrl_mdio1_default: mdio1_default {
1115 function = "MDIO1";
1116 groups = "MDIO1";
1117 };
1118
1119 pinctrl_mdio2_default: mdio2_default {
1120 function = "MDIO2";
1121 groups = "MDIO2";
1122 };
1123
1124 pinctrl_ncts1_default: ncts1_default {
1125 function = "NCTS1";
1126 groups = "NCTS1";
1127 };
1128
1129 pinctrl_ncts2_default: ncts2_default {
1130 function = "NCTS2";
1131 groups = "NCTS2";
1132 };
1133
1134 pinctrl_ncts3_default: ncts3_default {
1135 function = "NCTS3";
1136 groups = "NCTS3";
1137 };
1138
1139 pinctrl_ncts4_default: ncts4_default {
1140 function = "NCTS4";
1141 groups = "NCTS4";
1142 };
1143
1144 pinctrl_ndcd1_default: ndcd1_default {
1145 function = "NDCD1";
1146 groups = "NDCD1";
1147 };
1148
1149 pinctrl_ndcd2_default: ndcd2_default {
1150 function = "NDCD2";
1151 groups = "NDCD2";
1152 };
1153
1154 pinctrl_ndcd3_default: ndcd3_default {
1155 function = "NDCD3";
1156 groups = "NDCD3";
1157 };
1158
1159 pinctrl_ndcd4_default: ndcd4_default {
1160 function = "NDCD4";
1161 groups = "NDCD4";
1162 };
1163
1164 pinctrl_ndsr1_default: ndsr1_default {
1165 function = "NDSR1";
1166 groups = "NDSR1";
1167 };
1168
1169 pinctrl_ndsr2_default: ndsr2_default {
1170 function = "NDSR2";
1171 groups = "NDSR2";
1172 };
1173
1174 pinctrl_ndsr3_default: ndsr3_default {
1175 function = "NDSR3";
1176 groups = "NDSR3";
1177 };
1178
1179 pinctrl_ndsr4_default: ndsr4_default {
1180 function = "NDSR4";
1181 groups = "NDSR4";
1182 };
1183
1184 pinctrl_ndtr1_default: ndtr1_default {
1185 function = "NDTR1";
1186 groups = "NDTR1";
1187 };
1188
1189 pinctrl_ndtr2_default: ndtr2_default {
1190 function = "NDTR2";
1191 groups = "NDTR2";
1192 };
1193
1194 pinctrl_ndtr3_default: ndtr3_default {
1195 function = "NDTR3";
1196 groups = "NDTR3";
1197 };
1198
1199 pinctrl_ndtr4_default: ndtr4_default {
1200 function = "NDTR4";
1201 groups = "NDTR4";
1202 };
1203
1204 pinctrl_nri1_default: nri1_default {
1205 function = "NRI1";
1206 groups = "NRI1";
1207 };
1208
1209 pinctrl_nri2_default: nri2_default {
1210 function = "NRI2";
1211 groups = "NRI2";
1212 };
1213
1214 pinctrl_nri3_default: nri3_default {
1215 function = "NRI3";
1216 groups = "NRI3";
1217 };
1218
1219 pinctrl_nri4_default: nri4_default {
1220 function = "NRI4";
1221 groups = "NRI4";
1222 };
1223
1224 pinctrl_nrts1_default: nrts1_default {
1225 function = "NRTS1";
1226 groups = "NRTS1";
1227 };
1228
1229 pinctrl_nrts2_default: nrts2_default {
1230 function = "NRTS2";
1231 groups = "NRTS2";
1232 };
1233
1234 pinctrl_nrts3_default: nrts3_default {
1235 function = "NRTS3";
1236 groups = "NRTS3";
1237 };
1238
1239 pinctrl_nrts4_default: nrts4_default {
1240 function = "NRTS4";
1241 groups = "NRTS4";
1242 };
1243
1244 pinctrl_oscclk_default: oscclk_default {
1245 function = "OSCCLK";
1246 groups = "OSCCLK";
1247 };
1248
1249 pinctrl_pewake_default: pewake_default {
1250 function = "PEWAKE";
1251 groups = "PEWAKE";
1252 };
1253
1254 pinctrl_pnor_default: pnor_default {
1255 function = "PNOR";
1256 groups = "PNOR";
1257 };
1258
1259 pinctrl_pwm0_default: pwm0_default {
1260 function = "PWM0";
1261 groups = "PWM0";
1262 };
1263
1264 pinctrl_pwm1_default: pwm1_default {
1265 function = "PWM1";
1266 groups = "PWM1";
1267 };
1268
1269 pinctrl_pwm2_default: pwm2_default {
1270 function = "PWM2";
1271 groups = "PWM2";
1272 };
1273
1274 pinctrl_pwm3_default: pwm3_default {
1275 function = "PWM3";
1276 groups = "PWM3";
1277 };
1278
1279 pinctrl_pwm4_default: pwm4_default {
1280 function = "PWM4";
1281 groups = "PWM4";
1282 };
1283
1284 pinctrl_pwm5_default: pwm5_default {
1285 function = "PWM5";
1286 groups = "PWM5";
1287 };
1288
1289 pinctrl_pwm6_default: pwm6_default {
1290 function = "PWM6";
1291 groups = "PWM6";
1292 };
1293
1294 pinctrl_pwm7_default: pwm7_default {
1295 function = "PWM7";
1296 groups = "PWM7";
1297 };
1298
1299 pinctrl_rgmii1_default: rgmii1_default {
1300 function = "RGMII1";
1301 groups = "RGMII1";
1302 };
1303
1304 pinctrl_rgmii2_default: rgmii2_default {
1305 function = "RGMII2";
1306 groups = "RGMII2";
1307 };
1308
1309 pinctrl_rmii1_default: rmii1_default {
1310 function = "RMII1";
1311 groups = "RMII1";
1312 };
1313
1314 pinctrl_rmii2_default: rmii2_default {
1315 function = "RMII2";
1316 groups = "RMII2";
1317 };
1318
1319 pinctrl_rxd1_default: rxd1_default {
1320 function = "RXD1";
1321 groups = "RXD1";
1322 };
1323
1324 pinctrl_rxd2_default: rxd2_default {
1325 function = "RXD2";
1326 groups = "RXD2";
1327 };
1328
1329 pinctrl_rxd3_default: rxd3_default {
1330 function = "RXD3";
1331 groups = "RXD3";
1332 };
1333
1334 pinctrl_rxd4_default: rxd4_default {
1335 function = "RXD4";
1336 groups = "RXD4";
1337 };
1338
1339 pinctrl_salt1_default: salt1_default {
1340 function = "SALT1";
1341 groups = "SALT1";
1342 };
1343
1344 pinctrl_salt10_default: salt10_default {
1345 function = "SALT10";
1346 groups = "SALT10";
1347 };
1348
1349 pinctrl_salt11_default: salt11_default {
1350 function = "SALT11";
1351 groups = "SALT11";
1352 };
1353
1354 pinctrl_salt12_default: salt12_default {
1355 function = "SALT12";
1356 groups = "SALT12";
1357 };
1358
1359 pinctrl_salt13_default: salt13_default {
1360 function = "SALT13";
1361 groups = "SALT13";
1362 };
1363
1364 pinctrl_salt14_default: salt14_default {
1365 function = "SALT14";
1366 groups = "SALT14";
1367 };
1368
1369 pinctrl_salt2_default: salt2_default {
1370 function = "SALT2";
1371 groups = "SALT2";
1372 };
1373
1374 pinctrl_salt3_default: salt3_default {
1375 function = "SALT3";
1376 groups = "SALT3";
1377 };
1378
1379 pinctrl_salt4_default: salt4_default {
1380 function = "SALT4";
1381 groups = "SALT4";
1382 };
1383
1384 pinctrl_salt5_default: salt5_default {
1385 function = "SALT5";
1386 groups = "SALT5";
1387 };
1388
1389 pinctrl_salt6_default: salt6_default {
1390 function = "SALT6";
1391 groups = "SALT6";
1392 };
1393
1394 pinctrl_salt7_default: salt7_default {
1395 function = "SALT7";
1396 groups = "SALT7";
1397 };
1398
1399 pinctrl_salt8_default: salt8_default {
1400 function = "SALT8";
1401 groups = "SALT8";
1402 };
1403
1404 pinctrl_salt9_default: salt9_default {
1405 function = "SALT9";
1406 groups = "SALT9";
1407 };
1408
1409 pinctrl_scl1_default: scl1_default {
1410 function = "SCL1";
1411 groups = "SCL1";
1412 };
1413
1414 pinctrl_scl2_default: scl2_default {
1415 function = "SCL2";
1416 groups = "SCL2";
1417 };
1418
1419 pinctrl_sd1_default: sd1_default {
1420 function = "SD1";
1421 groups = "SD1";
1422 };
1423
1424 pinctrl_sd2_default: sd2_default {
1425 function = "SD2";
1426 groups = "SD2";
1427 };
1428
1429 pinctrl_sda1_default: sda1_default {
1430 function = "SDA1";
1431 groups = "SDA1";
1432 };
1433
1434 pinctrl_sda2_default: sda2_default {
1435 function = "SDA2";
1436 groups = "SDA2";
1437 };
1438
1439 pinctrl_sgpm_default: sgpm_default {
1440 function = "SGPM";
1441 groups = "SGPM";
1442 };
1443
1444 pinctrl_sgps1_default: sgps1_default {
1445 function = "SGPS1";
1446 groups = "SGPS1";
1447 };
1448
1449 pinctrl_sgps2_default: sgps2_default {
1450 function = "SGPS2";
1451 groups = "SGPS2";
1452 };
1453
1454 pinctrl_sioonctrl_default: sioonctrl_default {
1455 function = "SIOONCTRL";
1456 groups = "SIOONCTRL";
1457 };
1458
1459 pinctrl_siopbi_default: siopbi_default {
1460 function = "SIOPBI";
1461 groups = "SIOPBI";
1462 };
1463
1464 pinctrl_siopbo_default: siopbo_default {
1465 function = "SIOPBO";
1466 groups = "SIOPBO";
1467 };
1468
1469 pinctrl_siopwreq_default: siopwreq_default {
1470 function = "SIOPWREQ";
1471 groups = "SIOPWREQ";
1472 };
1473
1474 pinctrl_siopwrgd_default: siopwrgd_default {
1475 function = "SIOPWRGD";
1476 groups = "SIOPWRGD";
1477 };
1478
1479 pinctrl_sios3_default: sios3_default {
1480 function = "SIOS3";
1481 groups = "SIOS3";
1482 };
1483
1484 pinctrl_sios5_default: sios5_default {
1485 function = "SIOS5";
1486 groups = "SIOS5";
1487 };
1488
1489 pinctrl_siosci_default: siosci_default {
1490 function = "SIOSCI";
1491 groups = "SIOSCI";
1492 };
1493
1494 pinctrl_spi1_default: spi1_default {
1495 function = "SPI1";
1496 groups = "SPI1";
1497 };
1498
1499 pinctrl_spi1cs1_default: spi1cs1_default {
1500 function = "SPI1CS1";
1501 groups = "SPI1CS1";
1502 };
1503
1504 pinctrl_spi1debug_default: spi1debug_default {
1505 function = "SPI1DEBUG";
1506 groups = "SPI1DEBUG";
1507 };
1508
1509 pinctrl_spi1passthru_default: spi1passthru_default {
1510 function = "SPI1PASSTHRU";
1511 groups = "SPI1PASSTHRU";
1512 };
1513
1514 pinctrl_spi2ck_default: spi2ck_default {
1515 function = "SPI2CK";
1516 groups = "SPI2CK";
1517 };
1518
1519 pinctrl_spi2cs0_default: spi2cs0_default {
1520 function = "SPI2CS0";
1521 groups = "SPI2CS0";
1522 };
1523
1524 pinctrl_spi2cs1_default: spi2cs1_default {
1525 function = "SPI2CS1";
1526 groups = "SPI2CS1";
1527 };
1528
1529 pinctrl_spi2miso_default: spi2miso_default {
1530 function = "SPI2MISO";
1531 groups = "SPI2MISO";
1532 };
1533
1534 pinctrl_spi2mosi_default: spi2mosi_default {
1535 function = "SPI2MOSI";
1536 groups = "SPI2MOSI";
1537 };
1538
1539 pinctrl_timer3_default: timer3_default {
1540 function = "TIMER3";
1541 groups = "TIMER3";
1542 };
1543
1544 pinctrl_timer4_default: timer4_default {
1545 function = "TIMER4";
1546 groups = "TIMER4";
1547 };
1548
1549 pinctrl_timer5_default: timer5_default {
1550 function = "TIMER5";
1551 groups = "TIMER5";
1552 };
1553
1554 pinctrl_timer6_default: timer6_default {
1555 function = "TIMER6";
1556 groups = "TIMER6";
1557 };
1558
1559 pinctrl_timer7_default: timer7_default {
1560 function = "TIMER7";
1561 groups = "TIMER7";
1562 };
1563
1564 pinctrl_timer8_default: timer8_default {
1565 function = "TIMER8";
1566 groups = "TIMER8";
1567 };
1568
1569 pinctrl_txd1_default: txd1_default {
1570 function = "TXD1";
1571 groups = "TXD1";
1572 };
1573
1574 pinctrl_txd2_default: txd2_default {
1575 function = "TXD2";
1576 groups = "TXD2";
1577 };
1578
1579 pinctrl_txd3_default: txd3_default {
1580 function = "TXD3";
1581 groups = "TXD3";
1582 };
1583
1584 pinctrl_txd4_default: txd4_default {
1585 function = "TXD4";
1586 groups = "TXD4";
1587 };
1588
1589 pinctrl_uart6_default: uart6_default {
1590 function = "UART6";
1591 groups = "UART6";
1592 };
1593
1594 pinctrl_usbcki_default: usbcki_default {
1595 function = "USBCKI";
1596 groups = "USBCKI";
1597 };
1598
1599 pinctrl_usb2ah_default: usb2ah_default {
1600 function = "USB2AH";
1601 groups = "USB2AH";
1602 };
1603
1604 pinctrl_usb2ad_default: usb2ad_default {
1605 function = "USB2AD";
1606 groups = "USB2AD";
1607 };
1608
1609 pinctrl_usb11bhid_default: usb11bhid_default {
1610 function = "USB11BHID";
1611 groups = "USB11BHID";
1612 };
1613
1614 pinctrl_usb2bh_default: usb2bh_default {
1615 function = "USB2BH";
1616 groups = "USB2BH";
1617 };
1618
1619 pinctrl_vgabiosrom_default: vgabiosrom_default {
1620 function = "VGABIOSROM";
1621 groups = "VGABIOSROM";
1622 };
1623
1624 pinctrl_vgahs_default: vgahs_default {
1625 function = "VGAHS";
1626 groups = "VGAHS";
1627 };
1628
1629 pinctrl_vgavs_default: vgavs_default {
1630 function = "VGAVS";
1631 groups = "VGAVS";
1632 };
1633
1634 pinctrl_vpi24_default: vpi24_default {
1635 function = "VPI24";
1636 groups = "VPI24";
1637 };
1638
1639 pinctrl_vpo_default: vpo_default {
1640 function = "VPO";
1641 groups = "VPO";
1642 };
1643
1644 pinctrl_wdtrst1_default: wdtrst1_default {
1645 function = "WDTRST1";
1646 groups = "WDTRST1";
1647 };
1648
1649 pinctrl_wdtrst2_default: wdtrst2_default {
1650 function = "WDTRST2";
1651 groups = "WDTRST2";
1652 };
1653 };
