0001 // SPDX-License-Identifier: GPL-2.0+
0002 // Copyright (C) 2021 YADRO
0003 /dts-v1/;
0004
0005 #include "aspeed-bmc-vegman.dtsi"
0006
0007 / {
0008 model = "YADRO VEGMAN Sx20 BMC";
0009 compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500";
0010 };
0011
0012 &gpio {
0013 status = "okay";
0014 gpio-line-names =
0015 /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
0016 /*B0-B7*/ "","","","","","","","",
0017 /*C0-C7*/ "","","","","","","","",
0018 /*D0-D7*/ "","","","","","","","",
0019 /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","",
0020 /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","",
0021 /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","",
0022 /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
0023 /*I0-I7*/ "","","","","","","","",
0024 /*J0-J7*/ "","","","","","","","",
0025 /*K0-K7*/ "","","","","","","","",
0026 /*L0-L7*/ "","","","","","","","",
0027 /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","",
0028 /*N0-N7*/ "","","","","","","","",
0029 /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL",
0030 /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","",
0031 /*Q0-Q7*/ "","","","","","","","",
0032 /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
0033 /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
0034 /*T0-T7*/ "","","","","","","","",
0035 /*U0-U7*/ "","","","","","","","",
0036 /*V0-V7*/ "","","","","","","","",
0037 /*W0-W7*/ "","","","","","","","",
0038 /*X0-X7*/ "","","","","","","","",
0039 /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
0040 /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
0041 /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
0042 /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","",
0043 /*AC0-AC7*/ "","","","","","","","";
0044 };
0045
0046 &sgpio {
0047 ngpios = <80>;
0048 bus-frequency = <2000000>;
0049 status = "okay";
0050 /* SGPIO lines. even: input, odd: output */
0051 gpio-line-names =
0052 /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
0053 /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
0054 /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
0055 /*D0-D7*/ "","","","","","","","","","","","","","","","",
0056 /*E0-E7*/ "","","","","","","","","","","","","","","","",
0057 /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
0058 /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
0059 /*H0-H7*/ "","","","","","","","","","","","","","","","",
0060 /*I0-I7*/ "","","","","","","","","","","","","","","","",
0061 /*J0-J7*/ "","","","","","","","","","","","","","","","";
0062 };
0063
0064 &i2c11 {
0065 /* SMB_BMC_MGMT_LVC3 */
0066 gpio@21 {
0067 compatible = "nxp,pcal9535";
0068 reg = <0x21>;
0069 gpio-controller;
0070 #gpio-cells = <2>;
0071 gpio-line-names =
0072 /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT",
0073 /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT";
0074 };
0075 gpio@27 {
0076 compatible = "nxp,pca9698";
0077 reg = <0x27>;
0078 gpio-controller;
0079 #gpio-cells = <2>;
0080 gpio-line-names =
0081 /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
0082 /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
0083 /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1",
0084 /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1",
0085 /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", "";
0086 };
0087 };
0088
0089 &i2c13 {
0090 /* SMB_PCIE2_STBY_LVC3 */
0091 mux-expa@73 {
0092 compatible = "nxp,pca9545";
0093 reg = <0x73>;
0094 #address-cells = <1>;
0095 #size-cells = <0>;
0096 i2c-mux-idle-disconnect;
0097 };
0098 mux-sata@71 {
0099 compatible = "nxp,pca9543";
0100 reg = <0x71>;
0101 #address-cells = <1>;
0102 #size-cells = <0>;
0103 i2c-mux-idle-disconnect;
0104 };
0105 };
0106
0107 &i2c2 {
0108 /* SMB_PCIE_STBY_LVC3 */
0109 mux-expb@71 {
0110 compatible = "nxp,pca9545";
0111 reg = <0x71>;
0112 #address-cells = <1>;
0113 #size-cells = <0>;
0114 i2c-mux-idle-disconnect;
0115 };
0116 };
0117
0118 &pwm_tacho {
0119 status = "okay";
0120 pinctrl-names = "default";
0121 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
0122 &pinctrl_pwm2_default &pinctrl_pwm3_default
0123 &pinctrl_pwm4_default &pinctrl_pwm5_default
0124 &pinctrl_pwm6_default>;
0125
0126 fan@0 {
0127 reg = <0x00>;
0128 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
0129 };
0130 fan@1 {
0131 reg = <0x01>;
0132 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
0133 };
0134 fan@2 {
0135 reg = <0x02>;
0136 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
0137 };
0138 fan@3 {
0139 reg = <0x03>;
0140 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
0141 };
0142 fan@4 {
0143 reg = <0x04>;
0144 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
0145 };
0146 fan@5 {
0147 reg = <0x05>;
0148 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
0149 };
0150 fan@6 {
0151 reg = <0x06>;
0152 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
0153 };
0154 };
