0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada XP family SoC
0004 *
0005 * Copyright (C) 2012 Marvell
0006 *
0007 * Lior Amsalem <alior@marvell.com>
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 * Ben Dooks <ben.dooks@codethink.co.uk>
0011 *
0012 * Contains definitions specific to the Armada XP SoC that are not
0013 * common to all Armada SoCs.
0014 */
0015
0016 #include "armada-370-xp.dtsi"
0017
0018 / {
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 model = "Marvell Armada XP family SoC";
0023 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
0024
0025 aliases {
0026 serial2 = &uart2;
0027 serial3 = &uart3;
0028 };
0029
0030 soc {
0031 compatible = "marvell,armadaxp-mbus", "simple-bus";
0032
0033 bootrom {
0034 compatible = "marvell,bootrom";
0035 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
0036 };
0037
0038 internal-regs {
0039 sdramc: sdramc@1400 {
0040 compatible = "marvell,armada-xp-sdram-controller";
0041 reg = <0x1400 0x500>;
0042 };
0043
0044 L2: l2-cache@8000 {
0045 compatible = "marvell,aurora-system-cache";
0046 reg = <0x08000 0x1000>;
0047 cache-id-part = <0x100>;
0048 cache-level = <2>;
0049 cache-unified;
0050 wt-override;
0051 };
0052
0053 uart2: serial@12200 {
0054 compatible = "snps,dw-apb-uart";
0055 pinctrl-0 = <&uart2_pins>;
0056 pinctrl-names = "default";
0057 reg = <0x12200 0x100>;
0058 reg-shift = <2>;
0059 interrupts = <43>;
0060 reg-io-width = <1>;
0061 clocks = <&coreclk 0>;
0062 status = "disabled";
0063 };
0064
0065 uart3: serial@12300 {
0066 compatible = "snps,dw-apb-uart";
0067 pinctrl-0 = <&uart3_pins>;
0068 pinctrl-names = "default";
0069 reg = <0x12300 0x100>;
0070 reg-shift = <2>;
0071 interrupts = <44>;
0072 reg-io-width = <1>;
0073 clocks = <&coreclk 0>;
0074 status = "disabled";
0075 };
0076
0077 systemc: system-controller@18200 {
0078 compatible = "marvell,armada-370-xp-system-controller";
0079 reg = <0x18200 0x500>;
0080 };
0081
0082 gateclk: clock-gating-control@18220 {
0083 compatible = "marvell,armada-xp-gating-clock";
0084 reg = <0x18220 0x4>;
0085 clocks = <&coreclk 0>;
0086 #clock-cells = <1>;
0087 };
0088
0089 coreclk: mvebu-sar@18230 {
0090 compatible = "marvell,armada-xp-core-clock";
0091 reg = <0x18230 0x08>;
0092 #clock-cells = <1>;
0093 };
0094
0095 thermal: thermal@182b0 {
0096 compatible = "marvell,armadaxp-thermal";
0097 reg = <0x182b0 0x4
0098 0x184d0 0x4>;
0099 status = "okay";
0100 };
0101
0102 cpuclk: clock-complex@18700 {
0103 #clock-cells = <1>;
0104 compatible = "marvell,armada-xp-cpu-clock";
0105 reg = <0x18700 0x24>, <0x1c054 0x10>;
0106 clocks = <&coreclk 1>;
0107 };
0108
0109 cpu-config@21000 {
0110 compatible = "marvell,armada-xp-cpu-config";
0111 reg = <0x21000 0x8>;
0112 };
0113
0114 eth2: ethernet@30000 {
0115 compatible = "marvell,armada-xp-neta";
0116 reg = <0x30000 0x4000>;
0117 interrupts = <12>;
0118 clocks = <&gateclk 2>;
0119 status = "disabled";
0120 };
0121
0122 usb2: usb@52000 {
0123 compatible = "marvell,orion-ehci";
0124 reg = <0x52000 0x500>;
0125 interrupts = <47>;
0126 clocks = <&gateclk 20>;
0127 status = "disabled";
0128 };
0129
0130 xor1: xor@60900 {
0131 compatible = "marvell,orion-xor";
0132 reg = <0x60900 0x100
0133 0x60b00 0x100>;
0134 clocks = <&gateclk 22>;
0135 status = "okay";
0136
0137 xor10 {
0138 interrupts = <51>;
0139 dmacap,memcpy;
0140 dmacap,xor;
0141 };
0142 xor11 {
0143 interrupts = <52>;
0144 dmacap,memcpy;
0145 dmacap,xor;
0146 dmacap,memset;
0147 };
0148 };
0149
0150 ethernet@70000 {
0151 compatible = "marvell,armada-xp-neta";
0152 };
0153
0154 ethernet@74000 {
0155 compatible = "marvell,armada-xp-neta";
0156 };
0157
0158 cesa: crypto@90000 {
0159 compatible = "marvell,armada-xp-crypto";
0160 reg = <0x90000 0x10000>;
0161 reg-names = "regs";
0162 interrupts = <48>, <49>;
0163 clocks = <&gateclk 23>, <&gateclk 23>;
0164 clock-names = "cesa0", "cesa1";
0165 marvell,crypto-srams = <&crypto_sram0>,
0166 <&crypto_sram1>;
0167 marvell,crypto-sram-size = <0x800>;
0168 };
0169
0170 bm: bm@c0000 {
0171 compatible = "marvell,armada-380-neta-bm";
0172 reg = <0xc0000 0xac>;
0173 clocks = <&gateclk 13>;
0174 internal-mem = <&bm_bppi>;
0175 status = "disabled";
0176 };
0177
0178 xor0: xor@f0900 {
0179 compatible = "marvell,orion-xor";
0180 reg = <0xF0900 0x100
0181 0xF0B00 0x100>;
0182 clocks = <&gateclk 28>;
0183 status = "okay";
0184
0185 xor00 {
0186 interrupts = <94>;
0187 dmacap,memcpy;
0188 dmacap,xor;
0189 };
0190 xor01 {
0191 interrupts = <95>;
0192 dmacap,memcpy;
0193 dmacap,xor;
0194 dmacap,memset;
0195 };
0196 };
0197 };
0198
0199 crypto_sram0: sa-sram0 {
0200 compatible = "mmio-sram";
0201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
0202 clocks = <&gateclk 23>;
0203 #address-cells = <1>;
0204 #size-cells = <1>;
0205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
0206 };
0207
0208 crypto_sram1: sa-sram1 {
0209 compatible = "mmio-sram";
0210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
0211 clocks = <&gateclk 23>;
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
0215 };
0216
0217 bm_bppi: bm-bppi {
0218 compatible = "mmio-sram";
0219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
0220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
0221 #address-cells = <1>;
0222 #size-cells = <1>;
0223 clocks = <&gateclk 13>;
0224 no-memory-wc;
0225 status = "disabled";
0226 };
0227 };
0228
0229 clocks {
0230 /* 25 MHz reference crystal */
0231 refclk: oscillator {
0232 compatible = "fixed-clock";
0233 #clock-cells = <0>;
0234 clock-frequency = <25000000>;
0235 };
0236 };
0237 };
0238
0239 &i2c0 {
0240 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
0241 reg = <0x11000 0x100>;
0242 };
0243
0244 &i2c1 {
0245 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
0246 reg = <0x11100 0x100>;
0247 };
0248
0249 &mpic {
0250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
0251 };
0252
0253 &timer {
0254 compatible = "marvell,armada-xp-timer";
0255 clocks = <&coreclk 2>, <&refclk>;
0256 clock-names = "nbclk", "fixed";
0257 };
0258
0259 &watchdog {
0260 compatible = "marvell,armada-xp-wdt";
0261 clocks = <&coreclk 2>, <&refclk>;
0262 clock-names = "nbclk", "fixed";
0263 };
0264
0265 &cpurst {
0266 reg = <0x20800 0x20>;
0267 };
0268
0269 &usb0 {
0270 clocks = <&gateclk 18>;
0271 };
0272
0273 &usb1 {
0274 clocks = <&gateclk 19>;
0275 };
0276
0277 &pinctrl {
0278 ge0_gmii_pins: ge0-gmii-pins {
0279 marvell,pins =
0280 "mpp0", "mpp1", "mpp2", "mpp3",
0281 "mpp4", "mpp5", "mpp6", "mpp7",
0282 "mpp8", "mpp9", "mpp10", "mpp11",
0283 "mpp12", "mpp13", "mpp14", "mpp15",
0284 "mpp16", "mpp17", "mpp18", "mpp19",
0285 "mpp20", "mpp21", "mpp22", "mpp23";
0286 marvell,function = "ge0";
0287 };
0288
0289 ge0_rgmii_pins: ge0-rgmii-pins {
0290 marvell,pins =
0291 "mpp0", "mpp1", "mpp2", "mpp3",
0292 "mpp4", "mpp5", "mpp6", "mpp7",
0293 "mpp8", "mpp9", "mpp10", "mpp11";
0294 marvell,function = "ge0";
0295 };
0296
0297 ge1_rgmii_pins: ge1-rgmii-pins {
0298 marvell,pins =
0299 "mpp12", "mpp13", "mpp14", "mpp15",
0300 "mpp16", "mpp17", "mpp18", "mpp19",
0301 "mpp20", "mpp21", "mpp22", "mpp23";
0302 marvell,function = "ge1";
0303 };
0304
0305 sdio_pins: sdio-pins {
0306 marvell,pins = "mpp30", "mpp31", "mpp32",
0307 "mpp33", "mpp34", "mpp35";
0308 marvell,function = "sd0";
0309 };
0310
0311 spi0_pins: spi0-pins {
0312 marvell,pins = "mpp36", "mpp37",
0313 "mpp38", "mpp39";
0314 marvell,function = "spi0";
0315 };
0316
0317 spi1_pins: spi1-pins {
0318 marvell,pins = "mpp13", "mpp14",
0319 "mpp16", "mpp17";
0320 marvell,function = "spi1";
0321 };
0322
0323 uart2_pins: uart2-pins {
0324 marvell,pins = "mpp42", "mpp43";
0325 marvell,function = "uart2";
0326 };
0327
0328 uart3_pins: uart3-pins {
0329 marvell,pins = "mpp44", "mpp45";
0330 marvell,function = "uart3";
0331 };
0332 };
0333
0334 &spi0 {
0335 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
0336 pinctrl-0 = <&spi0_pins>;
0337 pinctrl-names = "default";
0338 };
0339
0340 &spi1 {
0341 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
0342 pinctrl-0 = <&spi1_pins>;
0343 pinctrl-names = "default";
0344 };
