0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada XP family SoC
0004 *
0005 * Copyright (C) 2012 Marvell
0006 *
0007 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008 *
0009 * Contains definitions specific to the Armada XP MV78460 SoC that are not
0010 * common to all Armada XP SoCs.
0011 */
0012
0013 #include "armada-xp.dtsi"
0014
0015 / {
0016 model = "Marvell Armada XP MV78460 SoC";
0017 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
0018
0019 aliases {
0020 gpio0 = &gpio0;
0021 gpio1 = &gpio1;
0022 gpio2 = &gpio2;
0023 };
0024
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029 enable-method = "marvell,armada-xp-smp";
0030
0031 cpu@0 {
0032 device_type = "cpu";
0033 compatible = "marvell,sheeva-v7";
0034 reg = <0>;
0035 clocks = <&cpuclk 0>;
0036 clock-latency = <1000000>;
0037 };
0038
0039 cpu@1 {
0040 device_type = "cpu";
0041 compatible = "marvell,sheeva-v7";
0042 reg = <1>;
0043 clocks = <&cpuclk 1>;
0044 clock-latency = <1000000>;
0045 };
0046
0047 cpu@2 {
0048 device_type = "cpu";
0049 compatible = "marvell,sheeva-v7";
0050 reg = <2>;
0051 clocks = <&cpuclk 2>;
0052 clock-latency = <1000000>;
0053 };
0054
0055 cpu@3 {
0056 device_type = "cpu";
0057 compatible = "marvell,sheeva-v7";
0058 reg = <3>;
0059 clocks = <&cpuclk 3>;
0060 clock-latency = <1000000>;
0061 };
0062 };
0063
0064 soc {
0065 /*
0066 * MV78460 has 4 PCIe units Gen2.0: Two units can be
0067 * configured as x4 or quad x1 lanes. Two units are
0068 * x4/x1.
0069 */
0070 pciec: pcie@82000000 {
0071 compatible = "marvell,armada-xp-pcie";
0072 status = "disabled";
0073 device_type = "pci";
0074
0075 #address-cells = <3>;
0076 #size-cells = <2>;
0077
0078 msi-parent = <&mpic>;
0079 bus-range = <0x00 0xff>;
0080
0081 ranges =
0082 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0083 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0084 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0085 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0086 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0087 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0088 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0089 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0090 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0091 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0092 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0093 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0094 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0095 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0096 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0097 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0098 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0099 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0100
0101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0103 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0104 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0105 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0106 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0107 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0108 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0109
0110 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0111 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
0112
0113 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0114 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
0115
0116 pcie1: pcie@1,0 {
0117 device_type = "pci";
0118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0119 reg = <0x0800 0 0 0 0>;
0120 #address-cells = <3>;
0121 #size-cells = <2>;
0122 #interrupt-cells = <1>;
0123 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0124 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0125 bus-range = <0x00 0xff>;
0126 interrupt-map-mask = <0 0 0 0>;
0127 interrupt-map = <0 0 0 0 &mpic 58>;
0128 marvell,pcie-port = <0>;
0129 marvell,pcie-lane = <0>;
0130 clocks = <&gateclk 5>;
0131 status = "disabled";
0132 };
0133
0134 pcie2: pcie@2,0 {
0135 device_type = "pci";
0136 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
0137 reg = <0x1000 0 0 0 0>;
0138 #address-cells = <3>;
0139 #size-cells = <2>;
0140 #interrupt-cells = <1>;
0141 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0142 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0143 bus-range = <0x00 0xff>;
0144 interrupt-map-mask = <0 0 0 0>;
0145 interrupt-map = <0 0 0 0 &mpic 59>;
0146 marvell,pcie-port = <0>;
0147 marvell,pcie-lane = <1>;
0148 clocks = <&gateclk 6>;
0149 status = "disabled";
0150 };
0151
0152 pcie3: pcie@3,0 {
0153 device_type = "pci";
0154 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
0155 reg = <0x1800 0 0 0 0>;
0156 #address-cells = <3>;
0157 #size-cells = <2>;
0158 #interrupt-cells = <1>;
0159 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0160 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0161 bus-range = <0x00 0xff>;
0162 interrupt-map-mask = <0 0 0 0>;
0163 interrupt-map = <0 0 0 0 &mpic 60>;
0164 marvell,pcie-port = <0>;
0165 marvell,pcie-lane = <2>;
0166 clocks = <&gateclk 7>;
0167 status = "disabled";
0168 };
0169
0170 pcie4: pcie@4,0 {
0171 device_type = "pci";
0172 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
0173 reg = <0x2000 0 0 0 0>;
0174 #address-cells = <3>;
0175 #size-cells = <2>;
0176 #interrupt-cells = <1>;
0177 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0178 0x81000000 0 0 0x81000000 0x4 0 1 0>;
0179 bus-range = <0x00 0xff>;
0180 interrupt-map-mask = <0 0 0 0>;
0181 interrupt-map = <0 0 0 0 &mpic 61>;
0182 marvell,pcie-port = <0>;
0183 marvell,pcie-lane = <3>;
0184 clocks = <&gateclk 8>;
0185 status = "disabled";
0186 };
0187
0188 pcie5: pcie@5,0 {
0189 device_type = "pci";
0190 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
0191 reg = <0x2800 0 0 0 0>;
0192 #address-cells = <3>;
0193 #size-cells = <2>;
0194 #interrupt-cells = <1>;
0195 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0196 0x81000000 0 0 0x81000000 0x5 0 1 0>;
0197 bus-range = <0x00 0xff>;
0198 interrupt-map-mask = <0 0 0 0>;
0199 interrupt-map = <0 0 0 0 &mpic 62>;
0200 marvell,pcie-port = <1>;
0201 marvell,pcie-lane = <0>;
0202 clocks = <&gateclk 9>;
0203 status = "disabled";
0204 };
0205
0206 pcie6: pcie@6,0 {
0207 device_type = "pci";
0208 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
0209 reg = <0x3000 0 0 0 0>;
0210 #address-cells = <3>;
0211 #size-cells = <2>;
0212 #interrupt-cells = <1>;
0213 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0214 0x81000000 0 0 0x81000000 0x6 0 1 0>;
0215 bus-range = <0x00 0xff>;
0216 interrupt-map-mask = <0 0 0 0>;
0217 interrupt-map = <0 0 0 0 &mpic 63>;
0218 marvell,pcie-port = <1>;
0219 marvell,pcie-lane = <1>;
0220 clocks = <&gateclk 10>;
0221 status = "disabled";
0222 };
0223
0224 pcie7: pcie@7,0 {
0225 device_type = "pci";
0226 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
0227 reg = <0x3800 0 0 0 0>;
0228 #address-cells = <3>;
0229 #size-cells = <2>;
0230 #interrupt-cells = <1>;
0231 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0232 0x81000000 0 0 0x81000000 0x7 0 1 0>;
0233 bus-range = <0x00 0xff>;
0234 interrupt-map-mask = <0 0 0 0>;
0235 interrupt-map = <0 0 0 0 &mpic 64>;
0236 marvell,pcie-port = <1>;
0237 marvell,pcie-lane = <2>;
0238 clocks = <&gateclk 11>;
0239 status = "disabled";
0240 };
0241
0242 pcie8: pcie@8,0 {
0243 device_type = "pci";
0244 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
0245 reg = <0x4000 0 0 0 0>;
0246 #address-cells = <3>;
0247 #size-cells = <2>;
0248 #interrupt-cells = <1>;
0249 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0250 0x81000000 0 0 0x81000000 0x8 0 1 0>;
0251 bus-range = <0x00 0xff>;
0252 interrupt-map-mask = <0 0 0 0>;
0253 interrupt-map = <0 0 0 0 &mpic 65>;
0254 marvell,pcie-port = <1>;
0255 marvell,pcie-lane = <3>;
0256 clocks = <&gateclk 12>;
0257 status = "disabled";
0258 };
0259
0260 pcie9: pcie@9,0 {
0261 device_type = "pci";
0262 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
0263 reg = <0x4800 0 0 0 0>;
0264 #address-cells = <3>;
0265 #size-cells = <2>;
0266 #interrupt-cells = <1>;
0267 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0268 0x81000000 0 0 0x81000000 0x9 0 1 0>;
0269 bus-range = <0x00 0xff>;
0270 interrupt-map-mask = <0 0 0 0>;
0271 interrupt-map = <0 0 0 0 &mpic 99>;
0272 marvell,pcie-port = <2>;
0273 marvell,pcie-lane = <0>;
0274 clocks = <&gateclk 26>;
0275 status = "disabled";
0276 };
0277
0278 pcie10: pcie@a,0 {
0279 device_type = "pci";
0280 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
0281 reg = <0x5000 0 0 0 0>;
0282 #address-cells = <3>;
0283 #size-cells = <2>;
0284 #interrupt-cells = <1>;
0285 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0286 0x81000000 0 0 0x81000000 0xa 0 1 0>;
0287 bus-range = <0x00 0xff>;
0288 interrupt-map-mask = <0 0 0 0>;
0289 interrupt-map = <0 0 0 0 &mpic 103>;
0290 marvell,pcie-port = <3>;
0291 marvell,pcie-lane = <0>;
0292 clocks = <&gateclk 27>;
0293 status = "disabled";
0294 };
0295 };
0296
0297 internal-regs {
0298 gpio0: gpio@18100 {
0299 compatible = "marvell,armada-370-gpio",
0300 "marvell,orion-gpio";
0301 reg = <0x18100 0x40>, <0x181c0 0x08>;
0302 reg-names = "gpio", "pwm";
0303 ngpios = <32>;
0304 gpio-controller;
0305 #gpio-cells = <2>;
0306 #pwm-cells = <2>;
0307 interrupt-controller;
0308 #interrupt-cells = <2>;
0309 interrupts = <82>, <83>, <84>, <85>;
0310 clocks = <&coreclk 0>;
0311 };
0312
0313 gpio1: gpio@18140 {
0314 compatible = "marvell,armada-370-gpio",
0315 "marvell,orion-gpio";
0316 reg = <0x18140 0x40>, <0x181c8 0x08>;
0317 reg-names = "gpio", "pwm";
0318 ngpios = <32>;
0319 gpio-controller;
0320 #gpio-cells = <2>;
0321 #pwm-cells = <2>;
0322 interrupt-controller;
0323 #interrupt-cells = <2>;
0324 interrupts = <87>, <88>, <89>, <90>;
0325 clocks = <&coreclk 0>;
0326 };
0327
0328 gpio2: gpio@18180 {
0329 compatible = "marvell,armada-370-gpio",
0330 "marvell,orion-gpio";
0331 reg = <0x18180 0x40>;
0332 ngpios = <3>;
0333 gpio-controller;
0334 #gpio-cells = <2>;
0335 interrupt-controller;
0336 #interrupt-cells = <2>;
0337 interrupts = <91>;
0338 };
0339
0340 eth3: ethernet@34000 {
0341 compatible = "marvell,armada-xp-neta";
0342 reg = <0x34000 0x4000>;
0343 interrupts = <14>;
0344 clocks = <&gateclk 1>;
0345 status = "disabled";
0346 };
0347 };
0348 };
0349 };
0350
0351 &pinctrl {
0352 compatible = "marvell,mv78460-pinctrl";
0353 };
