0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada XP family SoC
0004 *
0005 * Copyright (C) 2012 Marvell
0006 *
0007 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008 *
0009 * Contains definitions specific to the Armada XP MV78260 SoC that are not
0010 * common to all Armada XP SoCs.
0011 */
0012
0013 #include "armada-xp.dtsi"
0014
0015 / {
0016 model = "Marvell Armada XP MV78260 SoC";
0017 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
0018
0019 aliases {
0020 gpio0 = &gpio0;
0021 gpio1 = &gpio1;
0022 gpio2 = &gpio2;
0023 };
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028 enable-method = "marvell,armada-xp-smp";
0029
0030 cpu@0 {
0031 device_type = "cpu";
0032 compatible = "marvell,sheeva-v7";
0033 reg = <0>;
0034 clocks = <&cpuclk 0>;
0035 clock-latency = <1000000>;
0036 };
0037
0038 cpu@1 {
0039 device_type = "cpu";
0040 compatible = "marvell,sheeva-v7";
0041 reg = <1>;
0042 clocks = <&cpuclk 1>;
0043 clock-latency = <1000000>;
0044 };
0045 };
0046
0047 soc {
0048 /*
0049 * MV78260 has 3 PCIe units Gen2.0: Two units can be
0050 * configured as x4 or quad x1 lanes. One unit is
0051 * x4 only.
0052 */
0053 pciec: pcie@82000000 {
0054 compatible = "marvell,armada-xp-pcie";
0055 status = "disabled";
0056 device_type = "pci";
0057
0058 #address-cells = <3>;
0059 #size-cells = <2>;
0060
0061 msi-parent = <&mpic>;
0062 bus-range = <0x00 0xff>;
0063
0064 ranges =
0065 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0066 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0067 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0068 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0069 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0070 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0071 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0072 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0073 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0074 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0075 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0076 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0077 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0078 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0079 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0080 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0081 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0082
0083 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0084 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0085 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0086 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0087 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0088 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0089 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0090 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0091
0092 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0093 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
0094
0095 pcie1: pcie@1,0 {
0096 device_type = "pci";
0097 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0098 reg = <0x0800 0 0 0 0>;
0099 #address-cells = <3>;
0100 #size-cells = <2>;
0101 #interrupt-cells = <1>;
0102 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0103 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0104 bus-range = <0x00 0xff>;
0105 interrupt-map-mask = <0 0 0 0>;
0106 interrupt-map = <0 0 0 0 &mpic 58>;
0107 marvell,pcie-port = <0>;
0108 marvell,pcie-lane = <0>;
0109 clocks = <&gateclk 5>;
0110 status = "disabled";
0111 };
0112
0113 pcie2: pcie@2,0 {
0114 device_type = "pci";
0115 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
0116 reg = <0x1000 0 0 0 0>;
0117 #address-cells = <3>;
0118 #size-cells = <2>;
0119 #interrupt-cells = <1>;
0120 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0121 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0122 bus-range = <0x00 0xff>;
0123 interrupt-map-mask = <0 0 0 0>;
0124 interrupt-map = <0 0 0 0 &mpic 59>;
0125 marvell,pcie-port = <0>;
0126 marvell,pcie-lane = <1>;
0127 clocks = <&gateclk 6>;
0128 status = "disabled";
0129 };
0130
0131 pcie3: pcie@3,0 {
0132 device_type = "pci";
0133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
0134 reg = <0x1800 0 0 0 0>;
0135 #address-cells = <3>;
0136 #size-cells = <2>;
0137 #interrupt-cells = <1>;
0138 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0139 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0140 bus-range = <0x00 0xff>;
0141 interrupt-map-mask = <0 0 0 0>;
0142 interrupt-map = <0 0 0 0 &mpic 60>;
0143 marvell,pcie-port = <0>;
0144 marvell,pcie-lane = <2>;
0145 clocks = <&gateclk 7>;
0146 status = "disabled";
0147 };
0148
0149 pcie4: pcie@4,0 {
0150 device_type = "pci";
0151 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
0152 reg = <0x2000 0 0 0 0>;
0153 #address-cells = <3>;
0154 #size-cells = <2>;
0155 #interrupt-cells = <1>;
0156 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0157 0x81000000 0 0 0x81000000 0x4 0 1 0>;
0158 bus-range = <0x00 0xff>;
0159 interrupt-map-mask = <0 0 0 0>;
0160 interrupt-map = <0 0 0 0 &mpic 61>;
0161 marvell,pcie-port = <0>;
0162 marvell,pcie-lane = <3>;
0163 clocks = <&gateclk 8>;
0164 status = "disabled";
0165 };
0166
0167 pcie5: pcie@5,0 {
0168 device_type = "pci";
0169 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
0170 reg = <0x2800 0 0 0 0>;
0171 #address-cells = <3>;
0172 #size-cells = <2>;
0173 #interrupt-cells = <1>;
0174 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0175 0x81000000 0 0 0x81000000 0x5 0 1 0>;
0176 bus-range = <0x00 0xff>;
0177 interrupt-map-mask = <0 0 0 0>;
0178 interrupt-map = <0 0 0 0 &mpic 62>;
0179 marvell,pcie-port = <1>;
0180 marvell,pcie-lane = <0>;
0181 clocks = <&gateclk 9>;
0182 status = "disabled";
0183 };
0184
0185 pcie6: pcie@6,0 {
0186 device_type = "pci";
0187 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
0188 reg = <0x3000 0 0 0 0>;
0189 #address-cells = <3>;
0190 #size-cells = <2>;
0191 #interrupt-cells = <1>;
0192 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0193 0x81000000 0 0 0x81000000 0x6 0 1 0>;
0194 bus-range = <0x00 0xff>;
0195 interrupt-map-mask = <0 0 0 0>;
0196 interrupt-map = <0 0 0 0 &mpic 63>;
0197 marvell,pcie-port = <1>;
0198 marvell,pcie-lane = <1>;
0199 clocks = <&gateclk 10>;
0200 status = "disabled";
0201 };
0202
0203 pcie7: pcie@7,0 {
0204 device_type = "pci";
0205 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
0206 reg = <0x3800 0 0 0 0>;
0207 #address-cells = <3>;
0208 #size-cells = <2>;
0209 #interrupt-cells = <1>;
0210 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0211 0x81000000 0 0 0x81000000 0x7 0 1 0>;
0212 bus-range = <0x00 0xff>;
0213 interrupt-map-mask = <0 0 0 0>;
0214 interrupt-map = <0 0 0 0 &mpic 64>;
0215 marvell,pcie-port = <1>;
0216 marvell,pcie-lane = <2>;
0217 clocks = <&gateclk 11>;
0218 status = "disabled";
0219 };
0220
0221 pcie8: pcie@8,0 {
0222 device_type = "pci";
0223 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
0224 reg = <0x4000 0 0 0 0>;
0225 #address-cells = <3>;
0226 #size-cells = <2>;
0227 #interrupt-cells = <1>;
0228 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0229 0x81000000 0 0 0x81000000 0x8 0 1 0>;
0230 bus-range = <0x00 0xff>;
0231 interrupt-map-mask = <0 0 0 0>;
0232 interrupt-map = <0 0 0 0 &mpic 65>;
0233 marvell,pcie-port = <1>;
0234 marvell,pcie-lane = <3>;
0235 clocks = <&gateclk 12>;
0236 status = "disabled";
0237 };
0238
0239 pcie9: pcie@9,0 {
0240 device_type = "pci";
0241 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
0242 reg = <0x4800 0 0 0 0>;
0243 #address-cells = <3>;
0244 #size-cells = <2>;
0245 #interrupt-cells = <1>;
0246 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0247 0x81000000 0 0 0x81000000 0x9 0 1 0>;
0248 bus-range = <0x00 0xff>;
0249 interrupt-map-mask = <0 0 0 0>;
0250 interrupt-map = <0 0 0 0 &mpic 99>;
0251 marvell,pcie-port = <2>;
0252 marvell,pcie-lane = <0>;
0253 clocks = <&gateclk 26>;
0254 status = "disabled";
0255 };
0256 };
0257
0258 internal-regs {
0259 gpio0: gpio@18100 {
0260 compatible = "marvell,armada-370-gpio",
0261 "marvell,orion-gpio";
0262 reg = <0x18100 0x40>, <0x181c0 0x08>;
0263 reg-names = "gpio", "pwm";
0264 ngpios = <32>;
0265 gpio-controller;
0266 #gpio-cells = <2>;
0267 #pwm-cells = <2>;
0268 interrupt-controller;
0269 #interrupt-cells = <2>;
0270 interrupts = <82>, <83>, <84>, <85>;
0271 clocks = <&coreclk 0>;
0272 };
0273
0274 gpio1: gpio@18140 {
0275 compatible = "marvell,armada-370-gpio",
0276 "marvell,orion-gpio";
0277 reg = <0x18140 0x40>, <0x181c8 0x08>;
0278 reg-names = "gpio", "pwm";
0279 ngpios = <32>;
0280 gpio-controller;
0281 #gpio-cells = <2>;
0282 #pwm-cells = <2>;
0283 interrupt-controller;
0284 #interrupt-cells = <2>;
0285 interrupts = <87>, <88>, <89>, <90>;
0286 clocks = <&coreclk 0>;
0287 };
0288
0289 gpio2: gpio@18180 {
0290 compatible = "marvell,armada-370-gpio",
0291 "marvell,orion-gpio";
0292 reg = <0x18180 0x40>;
0293 ngpios = <3>;
0294 gpio-controller;
0295 #gpio-cells = <2>;
0296 interrupt-controller;
0297 #interrupt-cells = <2>;
0298 interrupts = <91>;
0299 };
0300
0301 eth3: ethernet@34000 {
0302 compatible = "marvell,armada-xp-neta";
0303 reg = <0x34000 0x4000>;
0304 interrupts = <14>;
0305 clocks = <&gateclk 1>;
0306 status = "disabled";
0307 };
0308 };
0309 };
0310 };
0311
0312 &pinctrl {
0313 compatible = "marvell,mv78260-pinctrl";
0314 };
