0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada XP family SoC
0004 *
0005 * Copyright (C) 2012 Marvell
0006 *
0007 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008 *
0009 * Contains definitions specific to the Armada XP MV78230 SoC that are not
0010 * common to all Armada XP SoCs.
0011 */
0012
0013 #include "armada-xp.dtsi"
0014
0015 / {
0016 model = "Marvell Armada XP MV78230 SoC";
0017 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
0018
0019 aliases {
0020 gpio0 = &gpio0;
0021 gpio1 = &gpio1;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027 enable-method = "marvell,armada-xp-smp";
0028
0029 cpu@0 {
0030 device_type = "cpu";
0031 compatible = "marvell,sheeva-v7";
0032 reg = <0>;
0033 clocks = <&cpuclk 0>;
0034 clock-latency = <1000000>;
0035 };
0036
0037 cpu@1 {
0038 device_type = "cpu";
0039 compatible = "marvell,sheeva-v7";
0040 reg = <1>;
0041 clocks = <&cpuclk 1>;
0042 clock-latency = <1000000>;
0043 };
0044 };
0045
0046 soc {
0047 /*
0048 * MV78230 has 2 PCIe units Gen2.0: One unit can be
0049 * configured as x4 or quad x1 lanes. One unit is
0050 * x1 only.
0051 */
0052 pciec: pcie@82000000 {
0053 compatible = "marvell,armada-xp-pcie";
0054 status = "disabled";
0055 device_type = "pci";
0056
0057 #address-cells = <3>;
0058 #size-cells = <2>;
0059
0060 msi-parent = <&mpic>;
0061 bus-range = <0x00 0xff>;
0062
0063 ranges =
0064 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0065 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0066 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0067 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0068 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0069 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0070 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0071 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0072 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0073 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0074 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0075 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0076 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0077 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0078 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
0079
0080 pcie1: pcie@1,0 {
0081 device_type = "pci";
0082 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0083 reg = <0x0800 0 0 0 0>;
0084 #address-cells = <3>;
0085 #size-cells = <2>;
0086 #interrupt-cells = <1>;
0087 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0088 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0089 bus-range = <0x00 0xff>;
0090 interrupt-map-mask = <0 0 0 0>;
0091 interrupt-map = <0 0 0 0 &mpic 58>;
0092 marvell,pcie-port = <0>;
0093 marvell,pcie-lane = <0>;
0094 clocks = <&gateclk 5>;
0095 status = "disabled";
0096 };
0097
0098 pcie2: pcie@2,0 {
0099 device_type = "pci";
0100 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
0101 reg = <0x1000 0 0 0 0>;
0102 #address-cells = <3>;
0103 #size-cells = <2>;
0104 #interrupt-cells = <1>;
0105 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0106 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0107 bus-range = <0x00 0xff>;
0108 interrupt-map-mask = <0 0 0 0>;
0109 interrupt-map = <0 0 0 0 &mpic 59>;
0110 marvell,pcie-port = <0>;
0111 marvell,pcie-lane = <1>;
0112 clocks = <&gateclk 6>;
0113 status = "disabled";
0114 };
0115
0116 pcie3: pcie@3,0 {
0117 device_type = "pci";
0118 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
0119 reg = <0x1800 0 0 0 0>;
0120 #address-cells = <3>;
0121 #size-cells = <2>;
0122 #interrupt-cells = <1>;
0123 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0124 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0125 bus-range = <0x00 0xff>;
0126 interrupt-map-mask = <0 0 0 0>;
0127 interrupt-map = <0 0 0 0 &mpic 60>;
0128 marvell,pcie-port = <0>;
0129 marvell,pcie-lane = <2>;
0130 clocks = <&gateclk 7>;
0131 status = "disabled";
0132 };
0133
0134 pcie4: pcie@4,0 {
0135 device_type = "pci";
0136 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
0137 reg = <0x2000 0 0 0 0>;
0138 #address-cells = <3>;
0139 #size-cells = <2>;
0140 #interrupt-cells = <1>;
0141 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0142 0x81000000 0 0 0x81000000 0x4 0 1 0>;
0143 bus-range = <0x00 0xff>;
0144 interrupt-map-mask = <0 0 0 0>;
0145 interrupt-map = <0 0 0 0 &mpic 61>;
0146 marvell,pcie-port = <0>;
0147 marvell,pcie-lane = <3>;
0148 clocks = <&gateclk 8>;
0149 status = "disabled";
0150 };
0151
0152 pcie5: pcie@5,0 {
0153 device_type = "pci";
0154 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
0155 reg = <0x2800 0 0 0 0>;
0156 #address-cells = <3>;
0157 #size-cells = <2>;
0158 #interrupt-cells = <1>;
0159 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0160 0x81000000 0 0 0x81000000 0x5 0 1 0>;
0161 bus-range = <0x00 0xff>;
0162 interrupt-map-mask = <0 0 0 0>;
0163 interrupt-map = <0 0 0 0 &mpic 62>;
0164 marvell,pcie-port = <1>;
0165 marvell,pcie-lane = <0>;
0166 clocks = <&gateclk 9>;
0167 status = "disabled";
0168 };
0169 };
0170
0171 internal-regs {
0172 gpio0: gpio@18100 {
0173 compatible = "marvell,armada-370-gpio",
0174 "marvell,orion-gpio";
0175 reg = <0x18100 0x40>, <0x181c0 0x08>;
0176 reg-names = "gpio", "pwm";
0177 ngpios = <32>;
0178 gpio-controller;
0179 #gpio-cells = <2>;
0180 #pwm-cells = <2>;
0181 interrupt-controller;
0182 #interrupt-cells = <2>;
0183 interrupts = <82>, <83>, <84>, <85>;
0184 clocks = <&coreclk 0>;
0185 };
0186
0187 gpio1: gpio@18140 {
0188 compatible = "marvell,armada-370-gpio",
0189 "marvell,orion-gpio";
0190 reg = <0x18140 0x40>, <0x181c8 0x08>;
0191 reg-names = "gpio", "pwm";
0192 ngpios = <17>;
0193 gpio-controller;
0194 #gpio-cells = <2>;
0195 #pwm-cells = <2>;
0196 interrupt-controller;
0197 #interrupt-cells = <2>;
0198 interrupts = <87>, <88>, <89>;
0199 clocks = <&coreclk 0>;
0200 };
0201 };
0202 };
0203 };
0204
0205 &pinctrl {
0206 compatible = "marvell,mv78230-pinctrl";
0207 };
