0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for Marvell Armada XP development board
0004 * (DB-MV784MP-GP)
0005 *
0006 * Copyright (C) 2013-2014 Marvell
0007 *
0008 * Lior Amsalem <alior@marvell.com>
0009 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0010 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0011 *
0012 * Note: this Device Tree assumes that the bootloader has remapped the
0013 * internal registers to 0xf1000000 (instead of the default
0014 * 0xd0000000). The 0xf1000000 is the default used by the recent,
0015 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
0016 * boards were delivered with an older version of the bootloader that
0017 * left internal registers mapped at 0xd0000000. If you are in this
0018 * situation, you should either update your bootloader (preferred
0019 * solution) or the below Device Tree should be adjusted.
0020 */
0021
0022 /dts-v1/;
0023 #include <dt-bindings/gpio/gpio.h>
0024 #include "armada-xp-mv78460.dtsi"
0025
0026 / {
0027 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
0028 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
0029
0030 chosen {
0031 stdout-path = "serial0:115200n8";
0032 };
0033
0034 memory@0 {
0035 device_type = "memory";
0036 /*
0037 * 8 GB of plug-in RAM modules by default.The amount
0038 * of memory available can be changed by the
0039 * bootloader according the size of the module
0040 * actually plugged. However, memory between
0041 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
0042 * the address range used for I/O (internal registers,
0043 * MBus windows).
0044 */
0045 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
0046 <0x00000001 0x00000000 0x00000001 0x00000000>;
0047 };
0048
0049 cpus {
0050 pm_pic {
0051 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
0052 <&gpio0 17 GPIO_ACTIVE_LOW>,
0053 <&gpio0 18 GPIO_ACTIVE_LOW>;
0054 };
0055 };
0056
0057 soc {
0058 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
0059 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
0060 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
0061 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
0062 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
0063 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
0064
0065 devbus-bootcs {
0066 status = "okay";
0067
0068 /* Device Bus parameters are required */
0069
0070 /* Read parameters */
0071 devbus,bus-width = <16>;
0072 devbus,turn-off-ps = <60000>;
0073 devbus,badr-skew-ps = <0>;
0074 devbus,acc-first-ps = <124000>;
0075 devbus,acc-next-ps = <248000>;
0076 devbus,rd-setup-ps = <0>;
0077 devbus,rd-hold-ps = <0>;
0078
0079 /* Write parameters */
0080 devbus,sync-enable = <0>;
0081 devbus,wr-high-ps = <60000>;
0082 devbus,wr-low-ps = <60000>;
0083 devbus,ale-wr-ps = <60000>;
0084
0085 /* NOR 16 MiB */
0086 nor@0 {
0087 compatible = "cfi-flash";
0088 reg = <0 0x1000000>;
0089 bank-width = <2>;
0090 };
0091 };
0092
0093 internal-regs {
0094 serial@12000 {
0095 status = "okay";
0096 };
0097 serial@12100 {
0098 status = "okay";
0099 };
0100 serial@12200 {
0101 status = "okay";
0102 };
0103 serial@12300 {
0104 status = "okay";
0105 };
0106 pinctrl {
0107 pinctrl-0 = <&pic_pins>;
0108 pinctrl-names = "default";
0109 pic_pins: pic-pins-0 {
0110 marvell,pins = "mpp16", "mpp17",
0111 "mpp18";
0112 marvell,function = "gpio";
0113 };
0114 };
0115 sata@a0000 {
0116 nr-ports = <2>;
0117 status = "okay";
0118 };
0119
0120 ethernet@70000 {
0121 status = "okay";
0122 phy = <&phy0>;
0123 phy-mode = "qsgmii";
0124 buffer-manager = <&bm>;
0125 bm,pool-long = <0>;
0126 };
0127 ethernet@74000 {
0128 status = "okay";
0129 phy = <&phy1>;
0130 phy-mode = "qsgmii";
0131 buffer-manager = <&bm>;
0132 bm,pool-long = <1>;
0133 };
0134 ethernet@30000 {
0135 status = "okay";
0136 phy = <&phy2>;
0137 phy-mode = "qsgmii";
0138 buffer-manager = <&bm>;
0139 bm,pool-long = <2>;
0140 };
0141 ethernet@34000 {
0142 status = "okay";
0143 phy = <&phy3>;
0144 phy-mode = "qsgmii";
0145 buffer-manager = <&bm>;
0146 bm,pool-long = <3>;
0147 };
0148
0149 /* Front-side USB slot */
0150 usb@50000 {
0151 status = "okay";
0152 };
0153
0154 /* Back-side USB slot */
0155 usb@51000 {
0156 status = "okay";
0157 };
0158
0159 bm@c0000 {
0160 status = "okay";
0161 };
0162
0163 nand-controller@d0000 {
0164 status = "okay";
0165
0166 nand@0 {
0167 reg = <0>;
0168 label = "pxa3xx_nand-0";
0169 nand-rb = <0>;
0170 nand-on-flash-bbt;
0171 };
0172 };
0173 };
0174
0175 bm-bppi {
0176 status = "okay";
0177 };
0178 };
0179 };
0180
0181 &pciec {
0182 status = "okay";
0183
0184 /*
0185 * The 3 slots are physically present as
0186 * standard PCIe slots on the board.
0187 */
0188 pcie@1,0 {
0189 /* Port 0, Lane 0 */
0190 status = "okay";
0191 };
0192 pcie@9,0 {
0193 /* Port 2, Lane 0 */
0194 status = "okay";
0195 };
0196 pcie@a,0 {
0197 /* Port 3, Lane 0 */
0198 status = "okay";
0199 };
0200 };
0201
0202 &mdio {
0203 phy0: ethernet-phy@0 {
0204 reg = <16>;
0205 };
0206
0207 phy1: ethernet-phy@1 {
0208 reg = <17>;
0209 };
0210
0211 phy2: ethernet-phy@2 {
0212 reg = <18>;
0213 };
0214
0215 phy3: ethernet-phy@3 {
0216 reg = <19>;
0217 };
0218 };
0219
0220 &spi0 {
0221 status = "okay";
0222
0223 flash@0 {
0224 #address-cells = <1>;
0225 #size-cells = <1>;
0226 compatible = "n25q128a13", "jedec,spi-nor";
0227 reg = <0>; /* Chip select 0 */
0228 spi-max-frequency = <108000000>;
0229 };
0230 };
