0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for Marvell Armada XP evaluation board
0004 * (DB-78460-BP)
0005 *
0006 * Copyright (C) 2012-2014 Marvell
0007 *
0008 * Lior Amsalem <alior@marvell.com>
0009 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0010 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0011 *
0012 *
0013 * Note: this Device Tree assumes that the bootloader has remapped the
0014 * internal registers to 0xf1000000 (instead of the default
0015 * 0xd0000000). The 0xf1000000 is the default used by the recent,
0016 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
0017 * boards were delivered with an older version of the bootloader that
0018 * left internal registers mapped at 0xd0000000. If you are in this
0019 * situation, you should either update your bootloader (preferred
0020 * solution) or the below Device Tree should be adjusted.
0021 */
0022
0023 /dts-v1/;
0024 #include "armada-xp-mv78460.dtsi"
0025
0026 / {
0027 model = "Marvell Armada XP Evaluation Board";
0028 compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
0029
0030 chosen {
0031 stdout-path = "serial0:115200n8";
0032 };
0033
0034 memory@0 {
0035 device_type = "memory";
0036 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
0037 };
0038
0039 soc {
0040 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
0041 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
0042 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
0043 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
0044 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
0045 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
0046
0047 devbus-bootcs {
0048 status = "okay";
0049
0050 /* Device Bus parameters are required */
0051
0052 /* Read parameters */
0053 devbus,bus-width = <16>;
0054 devbus,turn-off-ps = <60000>;
0055 devbus,badr-skew-ps = <0>;
0056 devbus,acc-first-ps = <124000>;
0057 devbus,acc-next-ps = <248000>;
0058 devbus,rd-setup-ps = <0>;
0059 devbus,rd-hold-ps = <0>;
0060
0061 /* Write parameters */
0062 devbus,sync-enable = <0>;
0063 devbus,wr-high-ps = <60000>;
0064 devbus,wr-low-ps = <60000>;
0065 devbus,ale-wr-ps = <60000>;
0066
0067 /* NOR 16 MiB */
0068 nor@0 {
0069 compatible = "cfi-flash";
0070 reg = <0 0x1000000>;
0071 bank-width = <2>;
0072 };
0073 };
0074
0075 internal-regs {
0076 serial@12000 {
0077 status = "okay";
0078 };
0079 serial@12100 {
0080 status = "okay";
0081 };
0082 serial@12200 {
0083 status = "okay";
0084 };
0085 serial@12300 {
0086 status = "okay";
0087 };
0088
0089 sata@a0000 {
0090 nr-ports = <2>;
0091 status = "okay";
0092 };
0093
0094 ethernet@70000 {
0095 status = "okay";
0096 phy = <&phy0>;
0097 phy-mode = "rgmii-id";
0098 buffer-manager = <&bm>;
0099 bm,pool-long = <0>;
0100 };
0101 ethernet@74000 {
0102 status = "okay";
0103 phy = <&phy1>;
0104 phy-mode = "rgmii-id";
0105 buffer-manager = <&bm>;
0106 bm,pool-long = <1>;
0107 };
0108 ethernet@30000 {
0109 status = "okay";
0110 phy = <&phy2>;
0111 phy-mode = "sgmii";
0112 buffer-manager = <&bm>;
0113 bm,pool-long = <2>;
0114 };
0115 ethernet@34000 {
0116 status = "okay";
0117 phy = <&phy3>;
0118 phy-mode = "sgmii";
0119 buffer-manager = <&bm>;
0120 bm,pool-long = <3>;
0121 };
0122
0123 bm@c0000 {
0124 status = "okay";
0125 };
0126
0127 mvsdio@d4000 {
0128 pinctrl-0 = <&sdio_pins>;
0129 pinctrl-names = "default";
0130 status = "okay";
0131 /* No CD or WP GPIOs */
0132 broken-cd;
0133 };
0134
0135 usb@50000 {
0136 status = "okay";
0137 };
0138
0139 usb@51000 {
0140 status = "okay";
0141 };
0142
0143 usb@52000 {
0144 status = "okay";
0145 };
0146
0147 nand-controller@d0000 {
0148 status = "okay";
0149
0150 nand@0 {
0151 reg = <0>;
0152 label = "pxa3xx_nand-0";
0153 nand-rb = <0>;
0154 nand-on-flash-bbt;
0155
0156 partitions {
0157 compatible = "fixed-partitions";
0158 #address-cells = <1>;
0159 #size-cells = <1>;
0160
0161 partition@0 {
0162 label = "U-Boot";
0163 reg = <0 0x800000>;
0164 };
0165 partition@800000 {
0166 label = "Linux";
0167 reg = <0x800000 0x800000>;
0168 };
0169 partition@1000000 {
0170 label = "Filesystem";
0171 reg = <0x1000000 0x3f000000>;
0172 };
0173 };
0174 };
0175 };
0176 };
0177
0178 bm-bppi {
0179 status = "okay";
0180 };
0181 };
0182 };
0183
0184 &pciec {
0185 status = "okay";
0186
0187 /*
0188 * All 6 slots are physically present as
0189 * standard PCIe slots on the board.
0190 */
0191 pcie@1,0 {
0192 /* Port 0, Lane 0 */
0193 status = "okay";
0194 };
0195 pcie@2,0 {
0196 /* Port 0, Lane 1 */
0197 status = "okay";
0198 };
0199 pcie@3,0 {
0200 /* Port 0, Lane 2 */
0201 status = "okay";
0202 };
0203 pcie@4,0 {
0204 /* Port 0, Lane 3 */
0205 status = "okay";
0206 };
0207 pcie@9,0 {
0208 /* Port 2, Lane 0 */
0209 status = "okay";
0210 };
0211 pcie@a,0 {
0212 /* Port 3, Lane 0 */
0213 status = "okay";
0214 };
0215 };
0216
0217 &mdio {
0218 phy0: ethernet-phy@0 {
0219 reg = <0>;
0220 };
0221
0222 phy1: ethernet-phy@1 {
0223 reg = <1>;
0224 };
0225
0226 phy2: ethernet-phy@2 {
0227 reg = <25>;
0228 };
0229
0230 phy3: ethernet-phy@3 {
0231 reg = <27>;
0232 };
0233 };
0234
0235 &spi0 {
0236 status = "okay";
0237
0238 flash@0 {
0239 #address-cells = <1>;
0240 #size-cells = <1>;
0241 compatible = "m25p64", "jedec,spi-nor";
0242 reg = <0>; /* Chip select 0 */
0243 spi-max-frequency = <20000000>;
0244 };
0245 };
