0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell 98dx3236 family SoC
0004 *
0005 * Copyright (C) 2016 Allied Telesis Labs
0006 *
0007 * Contains definitions specific to the 98dx3236 SoC that are not
0008 * common to all Armada XP SoCs.
0009 */
0010
0011 #include "armada-370-xp.dtsi"
0012
0013 / {
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 model = "Marvell 98DX3236 SoC";
0018 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
0019
0020 aliases {
0021 gpio0 = &gpio0;
0022 gpio1 = &gpio1;
0023 gpio2 = &gpio2;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029 enable-method = "marvell,98dx3236-smp";
0030
0031 cpu@0 {
0032 device_type = "cpu";
0033 compatible = "marvell,sheeva-v7";
0034 reg = <0>;
0035 clocks = <&cpuclk 0>;
0036 clock-latency = <1000000>;
0037 };
0038 };
0039
0040 soc {
0041 compatible = "marvell,armadaxp-mbus", "simple-bus";
0042
0043 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
0044 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
0045 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
0046 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
0047 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
0048
0049 bootrom {
0050 compatible = "marvell,bootrom";
0051 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
0052 };
0053
0054 /*
0055 * 98DX3236 has 1 x1 PCIe unit Gen2.0
0056 */
0057 pciec: pcie@82000000 {
0058 compatible = "marvell,armada-xp-pcie";
0059 status = "disabled";
0060 device_type = "pci";
0061
0062 #address-cells = <3>;
0063 #size-cells = <2>;
0064
0065 msi-parent = <&mpic>;
0066 bus-range = <0x00 0xff>;
0067
0068 ranges =
0069 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0070 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0071 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
0072
0073 pcie1: pcie@1,0 {
0074 device_type = "pci";
0075 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0076 reg = <0x0800 0 0 0 0>;
0077 #address-cells = <3>;
0078 #size-cells = <2>;
0079 #interrupt-cells = <1>;
0080 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0081 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0082 bus-range = <0x00 0xff>;
0083 interrupt-map-mask = <0 0 0 0>;
0084 interrupt-map = <0 0 0 0 &mpic 58>;
0085 marvell,pcie-port = <0>;
0086 marvell,pcie-lane = <0>;
0087 clocks = <&gateclk 5>;
0088 status = "disabled";
0089 };
0090 };
0091
0092 internal-regs {
0093 sdramc: sdramc@1400 {
0094 compatible = "marvell,armada-xp-sdram-controller";
0095 reg = <0x1400 0x500>;
0096 };
0097
0098 L2: l2-cache@8000 {
0099 compatible = "marvell,aurora-system-cache";
0100 reg = <0x08000 0x1000>;
0101 cache-id-part = <0x100>;
0102 cache-level = <2>;
0103 cache-unified;
0104 wt-override;
0105 };
0106
0107 gpio0: gpio@18100 {
0108 compatible = "marvell,orion-gpio";
0109 reg = <0x18100 0x40>;
0110 ngpios = <32>;
0111 gpio-controller;
0112 #gpio-cells = <2>;
0113 interrupt-controller;
0114 #interrupt-cells = <2>;
0115 interrupts = <82>, <83>, <84>, <85>;
0116 };
0117
0118 /* does not exist */
0119 gpio1: gpio@18140 {
0120 compatible = "marvell,orion-gpio";
0121 reg = <0x18140 0x40>;
0122 status = "disabled";
0123 };
0124
0125 gpio2: gpio@18180 { /* rework some properties */
0126 compatible = "marvell,orion-gpio";
0127 reg = <0x18180 0x40>;
0128 ngpios = <1>; /* only gpio #32 */
0129 gpio-controller;
0130 #gpio-cells = <2>;
0131 interrupt-controller;
0132 #interrupt-cells = <2>;
0133 interrupts = <87>;
0134 };
0135
0136 systemc: system-controller@18200 {
0137 compatible = "marvell,armada-370-xp-system-controller";
0138 reg = <0x18200 0x500>;
0139 };
0140
0141 gateclk: clock-gating-control@18220 {
0142 compatible = "marvell,mv98dx3236-gating-clock";
0143 reg = <0x18220 0x4>;
0144 clocks = <&coreclk 0>;
0145 #clock-cells = <1>;
0146 };
0147
0148 cpuclk: clock-complex@18700 {
0149 #clock-cells = <1>;
0150 compatible = "marvell,mv98dx3236-cpu-clock";
0151 reg = <0x18700 0x24>, <0x1c054 0x10>;
0152 clocks = <&coreclk 1>;
0153 };
0154
0155 corediv-clock@18740 {
0156 status = "disabled";
0157 };
0158
0159 cpu-config@21000 {
0160 compatible = "marvell,armada-xp-cpu-config";
0161 reg = <0x21000 0x8>;
0162 };
0163
0164 ethernet@70000 {
0165 compatible = "marvell,armada-xp-neta";
0166 };
0167
0168 ethernet@74000 {
0169 compatible = "marvell,armada-xp-neta";
0170 };
0171
0172 xor1: xor@f0800 {
0173 compatible = "marvell,orion-xor";
0174 reg = <0xf0800 0x100
0175 0xf0a00 0x100>;
0176 clocks = <&gateclk 22>;
0177 status = "okay";
0178
0179 xor10 {
0180 interrupts = <51>;
0181 dmacap,memcpy;
0182 dmacap,xor;
0183 };
0184 xor11 {
0185 interrupts = <52>;
0186 dmacap,memcpy;
0187 dmacap,xor;
0188 dmacap,memset;
0189 };
0190 };
0191
0192 nand_controller: nand-controller@d0000 {
0193 clocks = <&dfx_coredivclk 0>;
0194 };
0195
0196 xor0: xor@f0900 {
0197 compatible = "marvell,orion-xor";
0198 reg = <0xF0900 0x100
0199 0xF0B00 0x100>;
0200 clocks = <&gateclk 28>;
0201 status = "okay";
0202
0203 xor00 {
0204 interrupts = <94>;
0205 dmacap,memcpy;
0206 dmacap,xor;
0207 };
0208 xor01 {
0209 interrupts = <95>;
0210 dmacap,memcpy;
0211 dmacap,xor;
0212 dmacap,memset;
0213 };
0214 };
0215 };
0216
0217 dfx: dfx-server@ac000000 {
0218 compatible = "marvell,dfx-server", "simple-bus";
0219 #address-cells = <1>;
0220 #size-cells = <1>;
0221 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
0222 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
0223
0224 coreclk: mvebu-sar@f8204 {
0225 compatible = "marvell,mv98dx3236-core-clock";
0226 reg = <0xf8204 0x4>;
0227 #clock-cells = <1>;
0228 };
0229
0230 dfx_coredivclk: corediv-clock@f8268 {
0231 compatible = "marvell,mv98dx3236-corediv-clock";
0232 reg = <0xf8268 0xc>;
0233 #clock-cells = <1>;
0234 clocks = <&mainpll>;
0235 clock-output-names = "nand";
0236 };
0237 };
0238
0239 switch: switch@a8000000 {
0240 compatible = "simple-bus";
0241 #address-cells = <1>;
0242 #size-cells = <1>;
0243 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
0244
0245 pp0: packet-processor@0 {
0246 compatible = "marvell,prestera-98dx3236", "marvell,prestera";
0247 reg = <0 0x4000000>;
0248 interrupts = <33>, <34>, <35>;
0249 dfx = <&dfx>;
0250 };
0251 };
0252 };
0253
0254 clocks {
0255 /* 25 MHz reference crystal */
0256 refclk: oscillator {
0257 compatible = "fixed-clock";
0258 #clock-cells = <0>;
0259 clock-frequency = <25000000>;
0260 };
0261 };
0262 };
0263
0264 &i2c0 {
0265 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
0266 reg = <0x11000 0x100>;
0267 pinctrl-names = "default";
0268 pinctrl-0 = <&i2c0_pins>;
0269 };
0270
0271 &mpic {
0272 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
0273 };
0274
0275 &rtc {
0276 status = "disabled";
0277 };
0278
0279 &timer {
0280 compatible = "marvell,armada-xp-timer";
0281 clocks = <&coreclk 2>, <&refclk>;
0282 clock-names = "nbclk", "fixed";
0283 };
0284
0285 &watchdog {
0286 compatible = "marvell,armada-xp-wdt";
0287 clocks = <&coreclk 2>, <&refclk>;
0288 clock-names = "nbclk", "fixed";
0289 };
0290
0291 &cpurst {
0292 reg = <0x20800 0x20>;
0293 };
0294
0295 &usb0 {
0296 clocks = <&gateclk 18>;
0297 };
0298
0299 &usb1 {
0300 clocks = <&gateclk 19>;
0301 };
0302
0303 &pinctrl {
0304 compatible = "marvell,98dx3236-pinctrl";
0305
0306 nand_pins: nand-pins {
0307 marvell,pins = "mpp20", "mpp21", "mpp22",
0308 "mpp23", "mpp24", "mpp25",
0309 "mpp26", "mpp27", "mpp28",
0310 "mpp29", "mpp30";
0311 marvell,function = "dev";
0312 };
0313
0314 nand_rb: nand-rb {
0315 marvell,pins = "mpp19";
0316 marvell,function = "nand";
0317 };
0318
0319 spi0_pins: spi0-pins {
0320 marvell,pins = "mpp0", "mpp1",
0321 "mpp2", "mpp3";
0322 marvell,function = "spi0";
0323 };
0324
0325 i2c0_pins: i2c-pins-0 {
0326 marvell,pins = "mpp14", "mpp15";
0327 marvell,function = "i2c0";
0328 };
0329 };
0330
0331 &spi0 {
0332 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
0333 pinctrl-0 = <&spi0_pins>;
0334 pinctrl-names = "default";
0335 };
0336
0337 &sdio {
0338 status = "disabled";
0339 };
0340
0341 &uart0 {
0342 compatible = "marvell,armada-38x-uart";
0343 };
0344
0345 &uart1 {
0346 compatible = "marvell,armada-38x-uart";
0347 };
0348
