0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 39x family of SoCs.
0004 *
0005 * Copyright (C) 2015 Marvell
0006 *
0007 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008 */
0009
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012
0013 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0014
0015 / {
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 model = "Marvell Armada 39x family SoC";
0019 compatible = "marvell,armada390";
0020
0021 aliases {
0022 gpio0 = &gpio0;
0023 gpio1 = &gpio1;
0024 serial0 = &uart0;
0025 serial1 = &uart1;
0026 serial2 = &uart2;
0027 serial3 = &uart3;
0028 };
0029
0030 cpus {
0031 #address-cells = <1>;
0032 #size-cells = <0>;
0033 enable-method = "marvell,armada-390-smp";
0034
0035 cpu@0 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a9";
0038 reg = <0>;
0039 };
0040 cpu@1 {
0041 device_type = "cpu";
0042 compatible = "arm,cortex-a9";
0043 reg = <1>;
0044 };
0045 };
0046
0047 pmu {
0048 compatible = "arm,cortex-a9-pmu";
0049 interrupts-extended = <&mpic 3>;
0050 };
0051
0052 soc {
0053 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
0054 "simple-bus";
0055 #address-cells = <2>;
0056 #size-cells = <1>;
0057 controller = <&mbusc>;
0058 interrupt-parent = <&gic>;
0059 pcie-mem-aperture = <0xe0000000 0x8000000>;
0060 pcie-io-aperture = <0xe8000000 0x100000>;
0061
0062 bootrom {
0063 compatible = "marvell,bootrom";
0064 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
0065 };
0066
0067 internal-regs {
0068 compatible = "simple-bus";
0069 #address-cells = <1>;
0070 #size-cells = <1>;
0071 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0072
0073 L2: cache-controller@8000 {
0074 compatible = "arm,pl310-cache";
0075 reg = <0x8000 0x1000>;
0076 cache-unified;
0077 cache-level = <2>;
0078 arm,double-linefill-incr = <0>;
0079 arm,double-linefill-wrap = <0>;
0080 arm,double-linefill = <0>;
0081 prefetch-data = <1>;
0082 };
0083
0084 scu@c000 {
0085 compatible = "arm,cortex-a9-scu";
0086 reg = <0xc000 0x100>;
0087 };
0088
0089 timer@c600 {
0090 compatible = "arm,cortex-a9-twd-timer";
0091 reg = <0xc600 0x20>;
0092 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
0093 clocks = <&coreclk 2>;
0094 };
0095
0096 gic: interrupt-controller@d000 {
0097 compatible = "arm,cortex-a9-gic";
0098 #interrupt-cells = <3>;
0099 #size-cells = <0>;
0100 interrupt-controller;
0101 reg = <0xd000 0x1000>,
0102 <0xc100 0x100>;
0103 };
0104
0105 i2c0: i2c@11000 {
0106 compatible = "marvell,mv64xxx-i2c";
0107 reg = <0x11000 0x20>;
0108 #address-cells = <1>;
0109 #size-cells = <0>;
0110 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0111 clocks = <&coreclk 0>;
0112 status = "disabled";
0113 };
0114
0115 i2c1: i2c@11100 {
0116 compatible = "marvell,mv64xxx-i2c";
0117 reg = <0x11100 0x20>;
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0121 clocks = <&coreclk 0>;
0122 status = "disabled";
0123 };
0124
0125 i2c2: i2c@11200 {
0126 compatible = "marvell,mv64xxx-i2c";
0127 reg = <0x11200 0x20>;
0128 #address-cells = <1>;
0129 #size-cells = <0>;
0130 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0131 clocks = <&coreclk 0>;
0132 status = "disabled";
0133 };
0134
0135 i2c3: i2c@11300 {
0136 compatible = "marvell,mv64xxx-i2c";
0137 reg = <0x11300 0x20>;
0138 #address-cells = <1>;
0139 #size-cells = <0>;
0140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0141 clocks = <&coreclk 0>;
0142 status = "disabled";
0143 };
0144
0145 uart0: serial@12000 {
0146 compatible = "snps,dw-apb-uart";
0147 reg = <0x12000 0x100>;
0148 reg-shift = <2>;
0149 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0150 reg-io-width = <1>;
0151 clocks = <&coreclk 0>;
0152 status = "disabled";
0153 };
0154
0155 uart1: serial@12100 {
0156 compatible = "snps,dw-apb-uart";
0157 reg = <0x12100 0x100>;
0158 reg-shift = <2>;
0159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0160 reg-io-width = <1>;
0161 clocks = <&coreclk 0>;
0162 status = "disabled";
0163 };
0164
0165 uart2: serial@12200 {
0166 compatible = "snps,dw-apb-uart";
0167 reg = <0x12200 0x100>;
0168 reg-shift = <2>;
0169 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0170 reg-io-width = <1>;
0171 clocks = <&coreclk 0>;
0172 status = "disabled";
0173 };
0174
0175 uart3: serial@12300 {
0176 compatible = "snps,dw-apb-uart";
0177 reg = <0x12300 0x100>;
0178 reg-shift = <2>;
0179 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0180 reg-io-width = <1>;
0181 clocks = <&coreclk 0>;
0182 status = "disabled";
0183 };
0184
0185 pinctrl@18000 {
0186 i2c0_pins: i2c0-pins {
0187 marvell,pins = "mpp2", "mpp3";
0188 marvell,function = "i2c0";
0189 };
0190
0191 uart0_pins: uart0-pins {
0192 marvell,pins = "mpp0", "mpp1";
0193 marvell,function = "ua0";
0194 };
0195
0196 uart1_pins: uart1-pins {
0197 marvell,pins = "mpp19", "mpp20";
0198 marvell,function = "ua1";
0199 };
0200
0201 spi1_pins: spi1-pins {
0202 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
0203 marvell,function = "spi1";
0204 };
0205
0206 nand_pins: nand-pins {
0207 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
0208 "mpp38", "mpp28", "mpp40", "mpp42",
0209 "mpp35", "mpp36", "mpp25", "mpp30",
0210 "mpp32";
0211 marvell,function = "dev";
0212 };
0213 };
0214
0215 gpio0: gpio@18100 {
0216 compatible = "marvell,orion-gpio";
0217 reg = <0x18100 0x40>;
0218 ngpios = <32>;
0219 gpio-controller;
0220 #gpio-cells = <2>;
0221 interrupt-controller;
0222 #interrupt-cells = <2>;
0223 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0224 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0225 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0226 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0227 };
0228
0229 gpio1: gpio@18140 {
0230 compatible = "marvell,orion-gpio";
0231 reg = <0x18140 0x40>;
0232 ngpios = <28>;
0233 gpio-controller;
0234 #gpio-cells = <2>;
0235 interrupt-controller;
0236 #interrupt-cells = <2>;
0237 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0238 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0239 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0240 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0241 };
0242
0243 system-controller@18200 {
0244 compatible = "marvell,armada-390-system-controller",
0245 "marvell,armada-370-xp-system-controller";
0246 reg = <0x18200 0x100>;
0247 };
0248
0249 gateclk: clock-gating-control@18220 {
0250 compatible = "marvell,armada-390-gating-clock";
0251 reg = <0x18220 0x4>;
0252 clocks = <&coreclk 0>;
0253 #clock-cells = <1>;
0254 };
0255
0256 coreclk: mvebu-sar@18600 {
0257 compatible = "marvell,armada-390-core-clock";
0258 reg = <0x18600 0x04>;
0259 #clock-cells = <1>;
0260 };
0261
0262 mbusc: mbus-controller@20000 {
0263 compatible = "marvell,mbus-controller";
0264 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
0265 };
0266
0267 mpic: interrupt-controller@20a00 {
0268 compatible = "marvell,mpic";
0269 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
0270 #interrupt-cells = <1>;
0271 #size-cells = <1>;
0272 interrupt-controller;
0273 msi-controller;
0274 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0275 };
0276
0277 timer@20300 {
0278 compatible = "marvell,armada-380-timer",
0279 "marvell,armada-xp-timer";
0280 reg = <0x20300 0x30>, <0x21040 0x30>;
0281 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0282 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0283 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0284 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0285 <&mpic 5>,
0286 <&mpic 6>;
0287 clocks = <&coreclk 2>, <&coreclk 5>;
0288 clock-names = "nbclk", "fixed";
0289 };
0290
0291 watchdog@20300 {
0292 compatible = "marvell,armada-380-wdt";
0293 reg = <0x20300 0x34>, <0x20704 0x4>,
0294 <0x18260 0x4>;
0295 clocks = <&coreclk 2>, <&refclk>;
0296 clock-names = "nbclk", "fixed";
0297 };
0298
0299 cpurst@20800 {
0300 compatible = "marvell,armada-370-cpu-reset";
0301 reg = <0x20800 0x10>;
0302 };
0303
0304 mpcore-soc-ctrl@20d20 {
0305 compatible = "marvell,armada-380-mpcore-soc-ctrl";
0306 reg = <0x20d20 0x6c>;
0307 };
0308
0309 coherency-fabric@21010 {
0310 compatible = "marvell,armada-380-coherency-fabric";
0311 reg = <0x21010 0x1c>;
0312 };
0313
0314 pmsu@22000 {
0315 compatible = "marvell,armada-390-pmsu",
0316 "marvell,armada-380-pmsu";
0317 reg = <0x22000 0x1000>;
0318 };
0319
0320 xor@60800 {
0321 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0322 reg = <0x60800 0x100
0323 0x60a00 0x100>;
0324 clocks = <&gateclk 22>;
0325 status = "okay";
0326
0327 xor00 {
0328 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0329 dmacap,memcpy;
0330 dmacap,xor;
0331 };
0332 xor01 {
0333 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0334 dmacap,memcpy;
0335 dmacap,xor;
0336 dmacap,memset;
0337 };
0338 };
0339
0340 xor@60900 {
0341 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0342 reg = <0x60900 0x100
0343 0x60b00 0x100>;
0344 clocks = <&gateclk 28>;
0345 status = "okay";
0346
0347 xor10 {
0348 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0349 dmacap,memcpy;
0350 dmacap,xor;
0351 };
0352 xor11 {
0353 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0354 dmacap,memcpy;
0355 dmacap,xor;
0356 dmacap,memset;
0357 };
0358 };
0359
0360 rtc@a3800 {
0361 compatible = "marvell,armada-380-rtc";
0362 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
0363 reg-names = "rtc", "rtc-soc";
0364 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0365 };
0366
0367 nand_controller: nand-controller@d0000 {
0368 compatible = "marvell,armada370-nand-controller";
0369 reg = <0xd0000 0x54>;
0370 #address-cells = <1>;
0371 #size-cells = <0>;
0372 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0373 clocks = <&coredivclk 0>;
0374 status = "disabled";
0375 };
0376
0377 sdhci@d8000 {
0378 compatible = "marvell,armada-380-sdhci";
0379 reg-names = "sdhci", "mbus", "conf-sdio3";
0380 reg = <0xd8000 0x1000>,
0381 <0xdc000 0x100>,
0382 <0x18454 0x4>;
0383 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0384 clocks = <&gateclk 17>;
0385 mrvl,clk-delay-cycles = <0x1F>;
0386 status = "disabled";
0387 };
0388
0389 coredivclk: clock@e4250 {
0390 compatible = "marvell,armada-390-corediv-clock",
0391 "marvell,armada-380-corediv-clock";
0392 reg = <0xe4250 0xc>;
0393 #clock-cells = <1>;
0394 clocks = <&mainpll>;
0395 clock-output-names = "nand";
0396 };
0397
0398 thermal@e8078 {
0399 compatible = "marvell,armada380-thermal";
0400 reg = <0xe4078 0x4>, <0xe4074 0x4>;
0401 status = "okay";
0402 };
0403 };
0404
0405 pcie {
0406 compatible = "marvell,armada-370-pcie";
0407 status = "disabled";
0408 device_type = "pci";
0409
0410 #address-cells = <3>;
0411 #size-cells = <2>;
0412
0413 msi-parent = <&mpic>;
0414 bus-range = <0x00 0xff>;
0415
0416 ranges =
0417 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0418 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0419 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0420 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0421 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0422 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0423 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0424 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0425 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0426 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
0427 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
0428 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
0429
0430 /*
0431 * This port can be either x4 or x1. When
0432 * configured in x4 by the bootloader, then
0433 * pcie@4,0 is not available.
0434 */
0435 pcie@1,0 {
0436 device_type = "pci";
0437 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
0438 reg = <0x0800 0 0 0 0>;
0439 #address-cells = <3>;
0440 #size-cells = <2>;
0441 #interrupt-cells = <1>;
0442 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0443 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0444 bus-range = <0x00 0xff>;
0445 interrupt-map-mask = <0 0 0 0>;
0446 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0447 marvell,pcie-port = <0>;
0448 marvell,pcie-lane = <0>;
0449 clocks = <&gateclk 8>;
0450 status = "disabled";
0451 };
0452
0453 /* x1 port */
0454 pcie@2,0 {
0455 device_type = "pci";
0456 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0457 reg = <0x1000 0 0 0 0>;
0458 #address-cells = <3>;
0459 #size-cells = <2>;
0460 #interrupt-cells = <1>;
0461 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0462 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0463 bus-range = <0x00 0xff>;
0464 interrupt-map-mask = <0 0 0 0>;
0465 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0466 marvell,pcie-port = <1>;
0467 marvell,pcie-lane = <0>;
0468 clocks = <&gateclk 5>;
0469 status = "disabled";
0470 };
0471
0472 /* x1 port */
0473 pcie@3,0 {
0474 device_type = "pci";
0475 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
0476 reg = <0x1800 0 0 0 0>;
0477 #address-cells = <3>;
0478 #size-cells = <2>;
0479 #interrupt-cells = <1>;
0480 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0481 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0482 bus-range = <0x00 0xff>;
0483 interrupt-map-mask = <0 0 0 0>;
0484 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0485 marvell,pcie-port = <2>;
0486 marvell,pcie-lane = <0>;
0487 clocks = <&gateclk 6>;
0488 status = "disabled";
0489 };
0490
0491 /*
0492 * x1 port only available when pcie@1,0 is
0493 * configured as a x1 port
0494 */
0495 pcie@4,0 {
0496 device_type = "pci";
0497 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
0498 reg = <0x2000 0 0 0 0>;
0499 #address-cells = <3>;
0500 #size-cells = <2>;
0501 #interrupt-cells = <1>;
0502 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0503 0x81000000 0 0 0x81000000 0x4 0 1 0>;
0504 bus-range = <0x00 0xff>;
0505 interrupt-map-mask = <0 0 0 0>;
0506 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0507 marvell,pcie-port = <3>;
0508 marvell,pcie-lane = <0>;
0509 clocks = <&gateclk 7>;
0510 status = "disabled";
0511 };
0512 };
0513
0514 spi0: spi@10600 {
0515 compatible = "marvell,armada-390-spi",
0516 "marvell,orion-spi";
0517 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
0518 #address-cells = <1>;
0519 #size-cells = <0>;
0520 cell-index = <0>;
0521 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0522 clocks = <&coreclk 0>;
0523 status = "disabled";
0524 };
0525
0526 spi1: spi@10680 {
0527 compatible = "marvell,armada-390-spi",
0528 "marvell,orion-spi";
0529 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
0530 #address-cells = <1>;
0531 #size-cells = <0>;
0532 cell-index = <1>;
0533 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0534 clocks = <&coreclk 0>;
0535 status = "disabled";
0536 };
0537 };
0538
0539 clocks {
0540 /* 1 GHz fixed main PLL */
0541 mainpll: mainpll {
0542 compatible = "fixed-clock";
0543 #clock-cells = <0>;
0544 clock-frequency = <1000000000>;
0545 };
0546
0547 /* 25 MHz reference crystal */
0548 refclk: oscillator {
0549 compatible = "fixed-clock";
0550 #clock-cells = <0>;
0551 clock-frequency = <25000000>;
0552 };
0553 };
0554 };
