boot/dts/armada-395-gp.dts

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * Device Tree file for Marvell Armada 395 GP board
0004  *
0005  * Copyright (C) 2016 Marvell
0006  *
0007  * Grzegorz Jaszczyk <jaz@semihalf.com>
0008  */
0009
0010 /dts-v1/;
0011 #include "armada-395.dtsi"
0012
0013 / {
0014         model = "Marvell Armada 395 GP Board";
0015         compatible = "marvell,a395-gp", "marvell,armada395",
0016                      "marvell,armada390";
0017
0018         chosen {
0019                 stdout-path = "serial0:115200n8";
0020         };
0021
0022         memory {
0023                 device_type = "memory";
0024                 reg = <0x00000000 0x40000000>; /* 1 GB */
0025         };
0026
0027         soc {
0028                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0029                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
0030
0031                 internal-regs {
0032                         i2c@11000 {
0033                                 status = "okay";
0034                                 clock-frequency = <100000>;
0035
0036                                 eeprom@57 {
0037                                         compatible = "atmel,24c64";
0038                                         reg = <0x57>;
0039                                 };
0040                         };
0041
0042                         serial@12000 {
0043                                 /*
0044                                  * Exported on the micro USB connector CON17
0045                                  * through an FTDI
0046                                  */
0047                                 status = "okay";
0048                         };
0049
0050                         /* CON1 */
0051                         usb@58000 {
0052                                 status = "okay";
0053                         };
0054
0055                         /* CON2 */
0056                         sata@a8000 {
0057                                 status = "okay";
0058                         };
0059
0060                         /* CON18 */
0061                         sdhci@d8000 {
0062                                 clock-frequency = <200000000>;
0063                                 broken-cd;
0064                                 wp-inverted;
0065                                 bus-width = <8>;
0066                                 status = "okay";
0067                                 no-1-8-v;
0068                         };
0069
0070                         /* CON4 */
0071                         usb3@f0000 {
0072                                 status = "okay";
0073                         };
0074                 };
0075
0076                 pcie {
0077                         status = "okay";
0078
0079                         /*
0080                          * The two PCIe units are accessible through
0081                          * mini PCIe slot on the board.
0082                          */
0083
0084                         /* CON7 */
0085                         pcie@2,0 {
0086                                 /* Port 1, Lane 0 */
0087                                 status = "okay";
0088                         };
0089
0090                         /* CON8 */
0091                         pcie@4,0 {
0092                                 /* Port 3, Lane 0 */
0093                                 status = "okay";
0094                         };
0095                 };
0096         };
0097 };
0098
0099 &nand_controller {
0100         status = "okay";
0101         pinctrl-0 = <&nand_pins>;
0102         pinctrl-names = "default";
0103
0104         nand@0 {
0105                 reg = <0>;
0106                 label = "pxa3xx_nand-0";
0107                 nand-rb = <0>;
0108                 marvell,nand-keep-config;
0109                 nand-on-flash-bbt;
0110                 nand-ecc-strength = <4>;
0111                 nand-ecc-step-size = <512>;
0112
0113                 partitions {
0114                         compatible = "fixed-partitions";
0115                         #address-cells = <1>;
0116                         #size-cells = <1>;
0117
0118                         partition@0 {
0119                                 label = "U-Boot";
0120                                 reg = <0x00000000 0x00600000>;
0121                                 read-only;
0122                         };
0123
0124                         partition@800000 {
0125                                 label = "uImage";
0126                                 reg = <0x00600000 0x00400000>;
0127                                 read-only;
0128                         };
0129
0130                         partition@1000000 {
0131                                 label = "Root";
0132                                 reg = <0x00a00000 0x3f600000>;
0133                         };
0134                 };
0135         };
0136 };