0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Marvell Armada 38x family of SoCs.
0004 *
0005 * Copyright (C) 2014 Marvell
0006 *
0007 * Lior Amsalem <alior@marvell.com>
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 */
0011
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/interrupt-controller/irq.h>
0014
0015 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0016
0017 / {
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020
0021 model = "Marvell Armada 38x family SoC";
0022 compatible = "marvell,armada380";
0023
0024 aliases {
0025 gpio0 = &gpio0;
0026 gpio1 = &gpio1;
0027 serial0 = &uart0;
0028 serial1 = &uart1;
0029 };
0030
0031 pmu {
0032 compatible = "arm,cortex-a9-pmu";
0033 interrupts-extended = <&mpic 3>;
0034 };
0035
0036 soc {
0037 compatible = "marvell,armada380-mbus", "simple-bus";
0038 #address-cells = <2>;
0039 #size-cells = <1>;
0040 controller = <&mbusc>;
0041 interrupt-parent = <&gic>;
0042 pcie-mem-aperture = <0xe0000000 0x8000000>;
0043 pcie-io-aperture = <0xe8000000 0x100000>;
0044
0045 bootrom {
0046 compatible = "marvell,bootrom";
0047 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
0048 };
0049
0050 devbus_bootcs: devbus-bootcs {
0051 compatible = "marvell,mvebu-devbus";
0052 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
0053 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 clocks = <&coreclk 0>;
0057 status = "disabled";
0058 };
0059
0060 devbus_cs0: devbus-cs0 {
0061 compatible = "marvell,mvebu-devbus";
0062 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
0063 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 clocks = <&coreclk 0>;
0067 status = "disabled";
0068 };
0069
0070 devbus_cs1: devbus-cs1 {
0071 compatible = "marvell,mvebu-devbus";
0072 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
0073 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076 clocks = <&coreclk 0>;
0077 status = "disabled";
0078 };
0079
0080 devbus_cs2: devbus-cs2 {
0081 compatible = "marvell,mvebu-devbus";
0082 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
0083 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
0084 #address-cells = <1>;
0085 #size-cells = <1>;
0086 clocks = <&coreclk 0>;
0087 status = "disabled";
0088 };
0089
0090 devbus_cs3: devbus-cs3 {
0091 compatible = "marvell,mvebu-devbus";
0092 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
0093 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
0094 #address-cells = <1>;
0095 #size-cells = <1>;
0096 clocks = <&coreclk 0>;
0097 status = "disabled";
0098 };
0099
0100 internal-regs {
0101 compatible = "simple-bus";
0102 #address-cells = <1>;
0103 #size-cells = <1>;
0104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0105
0106 sdramc: sdramc@1400 {
0107 compatible = "marvell,armada-xp-sdram-controller";
0108 reg = <0x1400 0x500>;
0109 };
0110
0111 L2: cache-controller@8000 {
0112 compatible = "arm,pl310-cache";
0113 reg = <0x8000 0x1000>;
0114 cache-unified;
0115 cache-level = <2>;
0116 arm,double-linefill-incr = <0>;
0117 arm,double-linefill-wrap = <0>;
0118 arm,double-linefill = <0>;
0119 prefetch-data = <1>;
0120 };
0121
0122 scu@c000 {
0123 compatible = "arm,cortex-a9-scu";
0124 reg = <0xc000 0x58>;
0125 };
0126
0127 timer@c200 {
0128 compatible = "arm,cortex-a9-global-timer";
0129 reg = <0xc200 0x20>;
0130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
0131 clocks = <&coreclk 2>;
0132 };
0133
0134 timer@c600 {
0135 compatible = "arm,cortex-a9-twd-timer";
0136 reg = <0xc600 0x20>;
0137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
0138 clocks = <&coreclk 2>;
0139 };
0140
0141 gic: interrupt-controller@d000 {
0142 compatible = "arm,cortex-a9-gic";
0143 #interrupt-cells = <3>;
0144 #size-cells = <0>;
0145 interrupt-controller;
0146 reg = <0xd000 0x1000>,
0147 <0xc100 0x100>;
0148 };
0149
0150 i2c0: i2c@11000 {
0151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
0152 reg = <0x11000 0x20>;
0153 #address-cells = <1>;
0154 #size-cells = <0>;
0155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0156 clocks = <&coreclk 0>;
0157 status = "disabled";
0158 };
0159
0160 i2c1: i2c@11100 {
0161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
0162 reg = <0x11100 0x20>;
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0166 clocks = <&coreclk 0>;
0167 status = "disabled";
0168 };
0169
0170 uart0: serial@12000 {
0171 compatible = "marvell,armada-38x-uart", "ns16550a";
0172 reg = <0x12000 0x100>;
0173 reg-shift = <2>;
0174 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0175 reg-io-width = <1>;
0176 clocks = <&coreclk 0>;
0177 status = "disabled";
0178 };
0179
0180 uart1: serial@12100 {
0181 compatible = "marvell,armada-38x-uart", "ns16550a";
0182 reg = <0x12100 0x100>;
0183 reg-shift = <2>;
0184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0185 reg-io-width = <1>;
0186 clocks = <&coreclk 0>;
0187 status = "disabled";
0188 };
0189
0190 pinctrl: pinctrl@18000 {
0191 reg = <0x18000 0x20>;
0192
0193 ge0_rgmii_pins: ge-rgmii-pins-0 {
0194 marvell,pins = "mpp6", "mpp7", "mpp8",
0195 "mpp9", "mpp10", "mpp11",
0196 "mpp12", "mpp13", "mpp14",
0197 "mpp15", "mpp16", "mpp17";
0198 marvell,function = "ge0";
0199 };
0200
0201 ge1_rgmii_pins: ge-rgmii-pins-1 {
0202 marvell,pins = "mpp21", "mpp27", "mpp28",
0203 "mpp29", "mpp30", "mpp31",
0204 "mpp32", "mpp37", "mpp38",
0205 "mpp39", "mpp40", "mpp41";
0206 marvell,function = "ge1";
0207 };
0208
0209 i2c0_pins: i2c-pins-0 {
0210 marvell,pins = "mpp2", "mpp3";
0211 marvell,function = "i2c0";
0212 };
0213
0214 mdio_pins: mdio-pins {
0215 marvell,pins = "mpp4", "mpp5";
0216 marvell,function = "ge";
0217 };
0218
0219 ref_clk0_pins: ref-clk-pins-0 {
0220 marvell,pins = "mpp45";
0221 marvell,function = "ref";
0222 };
0223
0224 ref_clk1_pins: ref-clk-pins-1 {
0225 marvell,pins = "mpp46";
0226 marvell,function = "ref";
0227 };
0228
0229 spi0_pins: spi-pins-0 {
0230 marvell,pins = "mpp22", "mpp23", "mpp24",
0231 "mpp25";
0232 marvell,function = "spi0";
0233 };
0234
0235 spi1_pins: spi-pins-1 {
0236 marvell,pins = "mpp56", "mpp57", "mpp58",
0237 "mpp59";
0238 marvell,function = "spi1";
0239 };
0240
0241 nand_pins: nand-pins {
0242 marvell,pins = "mpp22", "mpp34", "mpp23",
0243 "mpp33", "mpp38", "mpp28",
0244 "mpp40", "mpp42", "mpp35",
0245 "mpp36", "mpp25", "mpp30",
0246 "mpp32";
0247 marvell,function = "dev";
0248 };
0249
0250 nand_rb: nand-rb {
0251 marvell,pins = "mpp41";
0252 marvell,function = "nand";
0253 };
0254
0255 uart0_pins: uart-pins-0 {
0256 marvell,pins = "mpp0", "mpp1";
0257 marvell,function = "ua0";
0258 };
0259
0260 uart1_pins: uart-pins-1 {
0261 marvell,pins = "mpp19", "mpp20";
0262 marvell,function = "ua1";
0263 };
0264
0265 sdhci_pins: sdhci-pins {
0266 marvell,pins = "mpp48", "mpp49", "mpp50",
0267 "mpp52", "mpp53", "mpp54",
0268 "mpp55", "mpp57", "mpp58",
0269 "mpp59";
0270 marvell,function = "sd0";
0271 };
0272
0273 sata0_pins: sata-pins-0 {
0274 marvell,pins = "mpp20";
0275 marvell,function = "sata0";
0276 };
0277
0278 sata1_pins: sata-pins-1 {
0279 marvell,pins = "mpp19";
0280 marvell,function = "sata1";
0281 };
0282
0283 sata2_pins: sata-pins-2 {
0284 marvell,pins = "mpp47";
0285 marvell,function = "sata2";
0286 };
0287
0288 sata3_pins: sata-pins-3 {
0289 marvell,pins = "mpp44";
0290 marvell,function = "sata3";
0291 };
0292 };
0293
0294 gpio0: gpio@18100 {
0295 compatible = "marvell,armada-370-gpio",
0296 "marvell,orion-gpio";
0297 reg = <0x18100 0x40>, <0x181c0 0x08>;
0298 reg-names = "gpio", "pwm";
0299 ngpios = <32>;
0300 gpio-controller;
0301 #gpio-cells = <2>;
0302 #pwm-cells = <2>;
0303 interrupt-controller;
0304 #interrupt-cells = <2>;
0305 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0306 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0307 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0308 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0309 clocks = <&coreclk 0>;
0310 };
0311
0312 gpio1: gpio@18140 {
0313 compatible = "marvell,armada-370-gpio",
0314 "marvell,orion-gpio";
0315 reg = <0x18140 0x40>, <0x181c8 0x08>;
0316 reg-names = "gpio", "pwm";
0317 ngpios = <28>;
0318 gpio-controller;
0319 #gpio-cells = <2>;
0320 #pwm-cells = <2>;
0321 interrupt-controller;
0322 #interrupt-cells = <2>;
0323 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0324 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0325 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0327 clocks = <&coreclk 0>;
0328 };
0329
0330 systemc: system-controller@18200 {
0331 compatible = "marvell,armada-380-system-controller",
0332 "marvell,armada-370-xp-system-controller";
0333 reg = <0x18200 0x100>;
0334 };
0335
0336 gateclk: clock-gating-control@18220 {
0337 compatible = "marvell,armada-380-gating-clock";
0338 reg = <0x18220 0x4>;
0339 clocks = <&coreclk 0>;
0340 #clock-cells = <1>;
0341 };
0342
0343 comphy: phy@18300 {
0344 compatible = "marvell,armada-380-comphy";
0345 reg-names = "comphy", "conf";
0346 reg = <0x18300 0x100>, <0x18460 4>;
0347 #address-cells = <1>;
0348 #size-cells = <0>;
0349
0350 comphy0: phy@0 {
0351 reg = <0>;
0352 #phy-cells = <1>;
0353 };
0354
0355 comphy1: phy@1 {
0356 reg = <1>;
0357 #phy-cells = <1>;
0358 };
0359
0360 comphy2: phy@2 {
0361 reg = <2>;
0362 #phy-cells = <1>;
0363 };
0364
0365 comphy3: phy@3 {
0366 reg = <3>;
0367 #phy-cells = <1>;
0368 };
0369
0370 comphy4: phy@4 {
0371 reg = <4>;
0372 #phy-cells = <1>;
0373 };
0374
0375 comphy5: phy@5 {
0376 reg = <5>;
0377 #phy-cells = <1>;
0378 };
0379 };
0380
0381 coreclk: mvebu-sar@18600 {
0382 compatible = "marvell,armada-380-core-clock";
0383 reg = <0x18600 0x04>;
0384 #clock-cells = <1>;
0385 };
0386
0387 mbusc: mbus-controller@20000 {
0388 compatible = "marvell,mbus-controller";
0389 reg = <0x20000 0x100>, <0x20180 0x20>,
0390 <0x20250 0x8>;
0391 };
0392
0393 mpic: interrupt-controller@20a00 {
0394 compatible = "marvell,mpic";
0395 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
0396 #interrupt-cells = <1>;
0397 #size-cells = <1>;
0398 interrupt-controller;
0399 msi-controller;
0400 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0401 };
0402
0403 timer: timer@20300 {
0404 compatible = "marvell,armada-380-timer",
0405 "marvell,armada-xp-timer";
0406 reg = <0x20300 0x30>, <0x21040 0x30>;
0407 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0408 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0409 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0410 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0411 <&mpic 5>,
0412 <&mpic 6>;
0413 clocks = <&coreclk 2>, <&refclk>;
0414 clock-names = "nbclk", "fixed";
0415 };
0416
0417 watchdog: watchdog@20300 {
0418 compatible = "marvell,armada-380-wdt";
0419 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
0420 clocks = <&coreclk 2>, <&refclk>;
0421 clock-names = "nbclk", "fixed";
0422 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
0423 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0424 };
0425
0426 cpurst: cpurst@20800 {
0427 compatible = "marvell,armada-370-cpu-reset";
0428 reg = <0x20800 0x10>;
0429 };
0430
0431 mpcore-soc-ctrl@20d20 {
0432 compatible = "marvell,armada-380-mpcore-soc-ctrl";
0433 reg = <0x20d20 0x6c>;
0434 };
0435
0436 coherencyfab: coherency-fabric@21010 {
0437 compatible = "marvell,armada-380-coherency-fabric";
0438 reg = <0x21010 0x1c>;
0439 };
0440
0441 pmsu: pmsu@22000 {
0442 compatible = "marvell,armada-380-pmsu";
0443 reg = <0x22000 0x1000>;
0444 };
0445
0446 /*
0447 * As a special exception to the "order by
0448 * register address" rule, the eth0 node is
0449 * placed here to ensure that it gets
0450 * registered as the first interface, since
0451 * the network subsystem doesn't allow naming
0452 * interfaces using DT aliases. Without this,
0453 * the ordering of interfaces is different
0454 * from the one used in U-Boot and the
0455 * labeling of interfaces on the boards, which
0456 * is very confusing for users.
0457 */
0458 eth0: ethernet@70000 {
0459 compatible = "marvell,armada-370-neta";
0460 reg = <0x70000 0x4000>;
0461 interrupts-extended = <&mpic 8>;
0462 clocks = <&gateclk 4>;
0463 tx-csum-limit = <9800>;
0464 status = "disabled";
0465 };
0466
0467 eth1: ethernet@30000 {
0468 compatible = "marvell,armada-370-neta";
0469 reg = <0x30000 0x4000>;
0470 interrupts-extended = <&mpic 10>;
0471 clocks = <&gateclk 3>;
0472 status = "disabled";
0473 };
0474
0475 eth2: ethernet@34000 {
0476 compatible = "marvell,armada-370-neta";
0477 reg = <0x34000 0x4000>;
0478 interrupts-extended = <&mpic 12>;
0479 clocks = <&gateclk 2>;
0480 status = "disabled";
0481 };
0482
0483 usb0: usb@58000 {
0484 compatible = "marvell,orion-ehci";
0485 reg = <0x58000 0x500>;
0486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0487 clocks = <&gateclk 18>;
0488 status = "disabled";
0489 };
0490
0491 xor0: xor@60800 {
0492 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0493 reg = <0x60800 0x100
0494 0x60a00 0x100>;
0495 clocks = <&gateclk 22>;
0496 status = "okay";
0497
0498 xor00 {
0499 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0500 dmacap,memcpy;
0501 dmacap,xor;
0502 };
0503 xor01 {
0504 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0505 dmacap,memcpy;
0506 dmacap,xor;
0507 dmacap,memset;
0508 };
0509 };
0510
0511 xor1: xor@60900 {
0512 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0513 reg = <0x60900 0x100
0514 0x60b00 0x100>;
0515 clocks = <&gateclk 28>;
0516 status = "okay";
0517
0518 xor10 {
0519 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0520 dmacap,memcpy;
0521 dmacap,xor;
0522 };
0523 xor11 {
0524 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0525 dmacap,memcpy;
0526 dmacap,xor;
0527 dmacap,memset;
0528 };
0529 };
0530
0531 mdio: mdio@72004 {
0532 #address-cells = <1>;
0533 #size-cells = <0>;
0534 compatible = "marvell,orion-mdio";
0535 reg = <0x72004 0x4>;
0536 clocks = <&gateclk 4>;
0537 };
0538
0539 cesa: crypto@90000 {
0540 compatible = "marvell,armada-38x-crypto";
0541 reg = <0x90000 0x10000>;
0542 reg-names = "regs";
0543 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0544 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0545 clocks = <&gateclk 23>, <&gateclk 21>,
0546 <&gateclk 14>, <&gateclk 16>;
0547 clock-names = "cesa0", "cesa1",
0548 "cesaz0", "cesaz1";
0549 marvell,crypto-srams = <&crypto_sram0>,
0550 <&crypto_sram1>;
0551 marvell,crypto-sram-size = <0x800>;
0552 };
0553
0554 rtc: rtc@a3800 {
0555 compatible = "marvell,armada-380-rtc";
0556 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
0557 reg-names = "rtc", "rtc-soc";
0558 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0559 };
0560
0561 ahci0: sata@a8000 {
0562 compatible = "marvell,armada-380-ahci";
0563 reg = <0xa8000 0x2000>;
0564 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0565 clocks = <&gateclk 15>;
0566 status = "disabled";
0567 };
0568
0569 bm: bm@c8000 {
0570 compatible = "marvell,armada-380-neta-bm";
0571 reg = <0xc8000 0xac>;
0572 clocks = <&gateclk 13>;
0573 internal-mem = <&bm_bppi>;
0574 status = "disabled";
0575 };
0576
0577 ahci1: sata@e0000 {
0578 compatible = "marvell,armada-380-ahci";
0579 reg = <0xe0000 0x2000>;
0580 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0581 clocks = <&gateclk 30>;
0582 status = "disabled";
0583 };
0584
0585 coredivclk: clock@e4250 {
0586 compatible = "marvell,armada-380-corediv-clock";
0587 reg = <0xe4250 0xc>;
0588 #clock-cells = <1>;
0589 clocks = <&mainpll>;
0590 clock-output-names = "nand";
0591 };
0592
0593 thermal: thermal@e8078 {
0594 compatible = "marvell,armada380-thermal";
0595 reg = <0xe4078 0x4>, <0xe4070 0x8>;
0596 status = "okay";
0597 };
0598
0599 nand_controller: nand-controller@d0000 {
0600 compatible = "marvell,armada370-nand-controller";
0601 reg = <0xd0000 0x54>;
0602 #address-cells = <1>;
0603 #size-cells = <0>;
0604 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0605 clocks = <&coredivclk 0>;
0606 status = "disabled";
0607 };
0608
0609 sdhci: sdhci@d8000 {
0610 compatible = "marvell,armada-380-sdhci";
0611 reg-names = "sdhci", "mbus", "conf-sdio3";
0612 reg = <0xd8000 0x1000>,
0613 <0xdc000 0x100>,
0614 <0x18454 0x4>;
0615 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0616 clocks = <&gateclk 17>;
0617 mrvl,clk-delay-cycles = <0x1F>;
0618 status = "disabled";
0619 };
0620
0621 usb3_0: usb3@f0000 {
0622 compatible = "marvell,armada-380-xhci";
0623 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
0624 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0625 clocks = <&gateclk 9>;
0626 status = "disabled";
0627 };
0628
0629 usb3_1: usb3@f8000 {
0630 compatible = "marvell,armada-380-xhci";
0631 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
0632 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0633 clocks = <&gateclk 10>;
0634 status = "disabled";
0635 };
0636 };
0637
0638 crypto_sram0: sa-sram0 {
0639 compatible = "mmio-sram";
0640 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
0641 clocks = <&gateclk 23>;
0642 #address-cells = <1>;
0643 #size-cells = <1>;
0644 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
0645 };
0646
0647 crypto_sram1: sa-sram1 {
0648 compatible = "mmio-sram";
0649 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
0650 clocks = <&gateclk 21>;
0651 #address-cells = <1>;
0652 #size-cells = <1>;
0653 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
0654 };
0655
0656 bm_bppi: bm-bppi {
0657 compatible = "mmio-sram";
0658 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
0659 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
0660 #address-cells = <1>;
0661 #size-cells = <1>;
0662 clocks = <&gateclk 13>;
0663 no-memory-wc;
0664 status = "disabled";
0665 };
0666
0667 spi0: spi@10600 {
0668 compatible = "marvell,armada-380-spi",
0669 "marvell,orion-spi";
0670 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
0671 #address-cells = <1>;
0672 #size-cells = <0>;
0673 cell-index = <0>;
0674 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0675 clocks = <&coreclk 0>;
0676 status = "disabled";
0677 };
0678
0679 spi1: spi@10680 {
0680 compatible = "marvell,armada-380-spi",
0681 "marvell,orion-spi";
0682 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
0683 #address-cells = <1>;
0684 #size-cells = <0>;
0685 cell-index = <1>;
0686 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0687 clocks = <&coreclk 0>;
0688 status = "disabled";
0689 };
0690 };
0691
0692 clocks {
0693 /* 1 GHz fixed main PLL */
0694 mainpll: mainpll {
0695 compatible = "fixed-clock";
0696 #clock-cells = <0>;
0697 clock-frequency = <1000000000>;
0698 };
0699
0700 /* 25 MHz reference crystal */
0701 refclk: oscillator {
0702 compatible = "fixed-clock";
0703 #clock-cells = <0>;
0704 clock-frequency = <25000000>;
0705 };
0706 };
0707 };
