boot/dts/armada-38x-solidrun-microsom.dtsi

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * Device Tree file for SolidRun Armada 38x Microsom
0004  *
0005  *  Copyright (C) 2015 Russell King
0006  */
0007 #include <dt-bindings/input/input.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009
0010 / {
0011         memory {
0012                 device_type = "memory";
0013                 reg = <0x00000000 0x10000000>; /* 256 MB */
0014         };
0015
0016         soc {
0017                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0018                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0019                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0020                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0021                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0022
0023                 internal-regs {
0024                         rtc@a3800 {
0025                                 /*
0026                                  * If the rtc doesn't work, run "date reset"
0027                                  * twice in u-boot.
0028                                  */
0029                                 status = "okay";
0030                         };
0031                 };
0032         };
0033 };
0034
0035 &bm {
0036         status = "okay";
0037 };
0038
0039 &bm_bppi {
0040         status = "okay";
0041 };
0042
0043 &eth0 {
0044         /* ethernet@70000 */
0045         pinctrl-0 = <&ge0_rgmii_pins>;
0046         pinctrl-names = "default";
0047         phy = <&phy_dedicated>;
0048         phy-mode = "rgmii-id";
0049         buffer-manager = <&bm>;
0050         bm,pool-long = <0>;
0051         bm,pool-short = <1>;
0052         status = "okay";
0053 };
0054
0055 &mdio {
0056         /*
0057          * Add the phy clock here, so the phy can be accessed to read its
0058          * IDs prior to binding with the driver.
0059          */
0060         pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
0061         pinctrl-names = "default";
0062
0063         phy_dedicated: ethernet-phy@0 {
0064                 /*
0065                  * Annoyingly, the marvell phy driver configures the LED
0066                  * register, rather than preserving reset-loaded setting.
0067                  * We undo that rubbish here.
0068                  */
0069                 marvell,reg-init = <3 16 0 0x101e>;
0070                 reg = <0>;
0071         };
0072 };
0073
0074 &i2c0 {
0075         clock-frequency = <400000>;
0076         pinctrl-0 = <&i2c0_pins>;
0077         pinctrl-names = "default";
0078         status = "okay";
0079
0080         eeprom@53 {
0081                 compatible = "atmel,24c02";
0082                 reg = <0x53>;
0083                 pagesize = <16>;
0084         };
0085 };
0086
0087 &pinctrl {
0088         microsom_phy_clk_pins: microsom-phy-clk-pins {
0089                 marvell,pins = "mpp45";
0090                 marvell,function = "ref";
0091         };
0092         /* Optional eMMC */
0093         microsom_sdhci_pins: microsom-sdhci-pins {
0094                 marvell,pins = "mpp21", "mpp28", "mpp37",
0095                                "mpp38", "mpp39", "mpp40";
0096                 marvell,function = "sd0";
0097         };
0098 };
0099
0100 &spi1 {
0101         /* The microsom has an optional W25Q32 on board, connected to CS0 */
0102         pinctrl-0 = <&spi1_pins>;
0103
0104         w25q32: flash@0 {
0105                 #address-cells = <1>;
0106                 #size-cells = <1>;
0107                 compatible = "w25q32", "jedec,spi-nor";
0108                 reg = <0>; /* Chip select 0 */
0109                 spi-max-frequency = <3000000>;
0110         };
0111 };
0112
0113 &uart0 {
0114         pinctrl-0 = <&uart0_pins>;
0115         pinctrl-names = "default";
0116         status = "okay";
0117 };