0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for Marvell Armada 388 Reference Design board
0004 * (RD-88F6820-AP)
0005 *
0006 * Copyright (C) 2014 Marvell
0007 *
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010 */
0011
0012 /dts-v1/;
0013 #include "armada-388.dtsi"
0014
0015 / {
0016 model = "Marvell Armada 385 Reference Design";
0017 compatible = "marvell,a385-rd", "marvell,armada388",
0018 "marvell,armada385","marvell,armada380";
0019
0020 chosen {
0021 stdout-path = "serial0:115200n8";
0022 };
0023
0024 memory {
0025 device_type = "memory";
0026 reg = <0x00000000 0x10000000>; /* 256 MB */
0027 };
0028
0029 soc {
0030 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0031 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0032 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0033 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
0034
0035 internal-regs {
0036 i2c@11000 {
0037 status = "okay";
0038 clock-frequency = <100000>;
0039 };
0040
0041 sdhci@d8000 {
0042 pinctrl-names = "default";
0043 pinctrl-0 = <&sdhci_pins>;
0044 broken-cd;
0045 no-1-8-v;
0046 wp-inverted;
0047 bus-width = <8>;
0048 status = "okay";
0049 };
0050
0051 serial@12000 {
0052 status = "okay";
0053 };
0054
0055 ethernet@30000 {
0056 status = "okay";
0057 phy = <&phy0>;
0058 phy-mode = "rgmii-id";
0059 };
0060
0061 ethernet@70000 {
0062 status = "okay";
0063 phy = <&phy1>;
0064 phy-mode = "rgmii-id";
0065 };
0066
0067
0068 mdio@72004 {
0069 phy0: ethernet-phy@0 {
0070 reg = <0>;
0071 };
0072
0073 phy1: ethernet-phy@1 {
0074 reg = <1>;
0075 };
0076 };
0077
0078 usb3@f0000 {
0079 status = "okay";
0080 };
0081 };
0082
0083 pcie {
0084 status = "okay";
0085 /*
0086 * One PCIe units is accessible through
0087 * standard PCIe slot on the board.
0088 */
0089 pcie@1,0 {
0090 /* Port 0, Lane 0 */
0091 status = "okay";
0092 };
0093 };
0094 };
0095 };
0096
0097 &spi0 {
0098 status = "okay";
0099
0100 flash@0 {
0101 #address-cells = <1>;
0102 #size-cells = <1>;
0103 compatible = "st,m25p128", "jedec,spi-nor";
0104 reg = <0>; /* Chip select 0 */
0105 spi-max-frequency = <108000000>;
0106 };
0107 };
0108
