0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Device Tree file for Marvell Armada 385 development board
0004 * (RD-88F6820-GP)
0005 *
0006 * Copyright (C) 2014 Marvell
0007 *
0008 * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009 */
0010
0011 /dts-v1/;
0012 #include "armada-388.dtsi"
0013 #include <dt-bindings/gpio/gpio.h>
0014
0015 / {
0016 model = "Marvell Armada 388 DB-88F6820-GP";
0017 compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
0018
0019 chosen {
0020 stdout-path = "serial0:115200n8";
0021 };
0022
0023 memory {
0024 device_type = "memory";
0025 reg = <0x00000000 0x80000000>; /* 2 GB */
0026 };
0027
0028 soc {
0029 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
0030 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
0031 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
0032 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
0033 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
0034
0035 internal-regs {
0036 i2c@11000 {
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&i2c0_pins>;
0039 status = "okay";
0040 clock-frequency = <100000>;
0041
0042 expander0: pca9555@20 {
0043 compatible = "nxp,pca9555";
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&pca0_pins>;
0046 interrupt-parent = <&gpio0>;
0047 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0048 gpio-controller;
0049 #gpio-cells = <2>;
0050 interrupt-controller;
0051 #interrupt-cells = <2>;
0052 reg = <0x20>;
0053 };
0054
0055 expander1: pca9555@21 {
0056 compatible = "nxp,pca9555";
0057 pinctrl-names = "default";
0058 interrupt-parent = <&gpio0>;
0059 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0060 gpio-controller;
0061 #gpio-cells = <2>;
0062 interrupt-controller;
0063 #interrupt-cells = <2>;
0064 reg = <0x21>;
0065 };
0066
0067 eeprom@57 {
0068 compatible = "atmel,24c64";
0069 reg = <0x57>;
0070 };
0071 };
0072
0073 serial@12000 {
0074 /*
0075 * Exported on the micro USB connector CON16
0076 * through an FTDI
0077 */
0078
0079 pinctrl-names = "default";
0080 pinctrl-0 = <&uart0_pins>;
0081 status = "okay";
0082 };
0083
0084 /* GE1 CON15 */
0085 ethernet@30000 {
0086 pinctrl-names = "default";
0087 pinctrl-0 = <&ge1_rgmii_pins>;
0088 status = "okay";
0089 phy = <&phy1>;
0090 phy-mode = "rgmii-id";
0091 buffer-manager = <&bm>;
0092 bm,pool-long = <2>;
0093 bm,pool-short = <3>;
0094 };
0095
0096 /* CON4 */
0097 usb@58000 {
0098 vcc-supply = <®_usb2_0_vbus>;
0099 status = "okay";
0100 };
0101
0102 /* GE0 CON1 */
0103 ethernet@70000 {
0104 pinctrl-names = "default";
0105 /*
0106 * The Reference Clock 0 is used to provide a
0107 * clock to the PHY
0108 */
0109 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
0110 status = "okay";
0111 phy = <&phy0>;
0112 phy-mode = "rgmii-id";
0113 buffer-manager = <&bm>;
0114 bm,pool-long = <0>;
0115 bm,pool-short = <1>;
0116 };
0117
0118
0119 mdio@72004 {
0120 pinctrl-names = "default";
0121 pinctrl-0 = <&mdio_pins>;
0122
0123 phy0: ethernet-phy@1 {
0124 reg = <1>;
0125 };
0126
0127 phy1: ethernet-phy@0 {
0128 reg = <0>;
0129 };
0130 };
0131
0132 sata@a8000 {
0133 pinctrl-names = "default";
0134 pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
0135 status = "okay";
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138
0139 sata0: sata-port@0 {
0140 reg = <0>;
0141 target-supply = <®_5v_sata0>;
0142 };
0143
0144 sata1: sata-port@1 {
0145 reg = <1>;
0146 target-supply = <®_5v_sata1>;
0147 };
0148 };
0149
0150 bm@c8000 {
0151 status = "okay";
0152 };
0153
0154 sata@e0000 {
0155 pinctrl-names = "default";
0156 pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
0157 status = "okay";
0158 #address-cells = <1>;
0159 #size-cells = <0>;
0160
0161 sata2: sata-port@0 {
0162 reg = <0>;
0163 target-supply = <®_5v_sata2>;
0164 };
0165
0166 sata3: sata-port@1 {
0167 reg = <1>;
0168 target-supply = <®_5v_sata3>;
0169 };
0170 };
0171
0172 sdhci@d8000 {
0173 pinctrl-names = "default";
0174 pinctrl-0 = <&sdhci_pins>;
0175 no-1-8-v;
0176 /*
0177 * A388-GP board v1.5 and higher replace
0178 * hitherto card detection method based on GPIO
0179 * with the one using DAT3 pin. As they are
0180 * incompatible, software-based polling is
0181 * enabled with 'broken-cd' property. For boards
0182 * older than v1.5 it can be replaced with:
0183 * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
0184 * whereas for the newer ones following can be
0185 * used instead:
0186 * 'dat3-cd;'
0187 * 'cd-inverted;'
0188 */
0189 broken-cd;
0190 wp-inverted;
0191 bus-width = <8>;
0192 status = "okay";
0193 };
0194
0195 /* CON5 */
0196 usb3@f0000 {
0197 usb-phy = <&usb2_1_phy>;
0198 status = "okay";
0199 };
0200
0201 /* CON7 */
0202 usb3@f8000 {
0203 usb-phy = <&usb3_phy>;
0204 status = "okay";
0205 };
0206 };
0207
0208 bm-bppi {
0209 status = "okay";
0210 };
0211
0212 pcie {
0213 status = "okay";
0214 /*
0215 * One PCIe units is accessible through
0216 * standard PCIe slot on the board.
0217 */
0218 pcie@1,0 {
0219 /* Port 0, Lane 0 */
0220 status = "okay";
0221 };
0222
0223 /*
0224 * The two other PCIe units are accessible
0225 * through mini PCIe slot on the board.
0226 */
0227 pcie@2,0 {
0228 /* Port 1, Lane 0 */
0229 status = "okay";
0230 };
0231 pcie@3,0 {
0232 /* Port 2, Lane 0 */
0233 status = "okay";
0234 };
0235 };
0236
0237 gpio-fan {
0238 compatible = "gpio-fan";
0239 gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
0240 gpio-fan,speed-map = < 0 0
0241 3000 1>;
0242 };
0243 };
0244
0245 usb2_1_phy: usb2_1_phy {
0246 compatible = "usb-nop-xceiv";
0247 vcc-supply = <®_usb2_1_vbus>;
0248 #phy-cells = <0>;
0249 };
0250
0251 usb3_phy: usb3_phy {
0252 compatible = "usb-nop-xceiv";
0253 vcc-supply = <®_usb3_vbus>;
0254 #phy-cells = <0>;
0255 };
0256
0257 reg_usb3_vbus: usb3-vbus {
0258 compatible = "regulator-fixed";
0259 regulator-name = "usb3-vbus";
0260 regulator-min-microvolt = <5000000>;
0261 regulator-max-microvolt = <5000000>;
0262 enable-active-high;
0263 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
0264 };
0265
0266 reg_usb2_0_vbus: v5-vbus0 {
0267 compatible = "regulator-fixed";
0268 regulator-name = "v5.0-vbus0";
0269 regulator-min-microvolt = <5000000>;
0270 regulator-max-microvolt = <5000000>;
0271 enable-active-high;
0272 regulator-always-on;
0273 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
0274 };
0275
0276 reg_usb2_1_vbus: v5-vbus1 {
0277 compatible = "regulator-fixed";
0278 regulator-name = "v5.0-vbus1";
0279 regulator-min-microvolt = <5000000>;
0280 regulator-max-microvolt = <5000000>;
0281 enable-active-high;
0282 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
0283 };
0284
0285 reg_sata0: pwr-sata0 {
0286 compatible = "regulator-fixed";
0287 regulator-name = "pwr_en_sata0";
0288 regulator-min-microvolt = <12000000>;
0289 regulator-max-microvolt = <12000000>;
0290 enable-active-high;
0291 regulator-boot-on;
0292 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
0293 };
0294
0295 reg_5v_sata0: v5-sata0 {
0296 compatible = "regulator-fixed";
0297 regulator-name = "v5.0-sata0";
0298 regulator-min-microvolt = <5000000>;
0299 regulator-max-microvolt = <5000000>;
0300 vin-supply = <®_sata0>;
0301 };
0302
0303 reg_12v_sata0: v12-sata0 {
0304 compatible = "regulator-fixed";
0305 regulator-name = "v12.0-sata0";
0306 regulator-min-microvolt = <12000000>;
0307 regulator-max-microvolt = <12000000>;
0308 vin-supply = <®_sata0>;
0309 };
0310
0311 reg_sata1: pwr-sata1 {
0312 regulator-name = "pwr_en_sata1";
0313 compatible = "regulator-fixed";
0314 regulator-min-microvolt = <12000000>;
0315 regulator-max-microvolt = <12000000>;
0316 enable-active-high;
0317 regulator-boot-on;
0318 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
0319 };
0320
0321 reg_5v_sata1: v5-sata1 {
0322 compatible = "regulator-fixed";
0323 regulator-name = "v5.0-sata1";
0324 regulator-min-microvolt = <5000000>;
0325 regulator-max-microvolt = <5000000>;
0326 vin-supply = <®_sata1>;
0327 };
0328
0329 reg_12v_sata1: v12-sata1 {
0330 compatible = "regulator-fixed";
0331 regulator-name = "v12.0-sata1";
0332 regulator-min-microvolt = <12000000>;
0333 regulator-max-microvolt = <12000000>;
0334 vin-supply = <®_sata1>;
0335 };
0336
0337 reg_sata2: pwr-sata2 {
0338 compatible = "regulator-fixed";
0339 regulator-name = "pwr_en_sata2";
0340 enable-active-high;
0341 regulator-boot-on;
0342 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
0343 };
0344
0345 reg_5v_sata2: v5-sata2 {
0346 compatible = "regulator-fixed";
0347 regulator-name = "v5.0-sata2";
0348 regulator-min-microvolt = <5000000>;
0349 regulator-max-microvolt = <5000000>;
0350 vin-supply = <®_sata2>;
0351 };
0352
0353 reg_12v_sata2: v12-sata2 {
0354 compatible = "regulator-fixed";
0355 regulator-name = "v12.0-sata2";
0356 regulator-min-microvolt = <12000000>;
0357 regulator-max-microvolt = <12000000>;
0358 vin-supply = <®_sata2>;
0359 };
0360
0361 reg_sata3: pwr-sata3 {
0362 compatible = "regulator-fixed";
0363 regulator-name = "pwr_en_sata3";
0364 enable-active-high;
0365 regulator-boot-on;
0366 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
0367 };
0368
0369 reg_5v_sata3: v5-sata3 {
0370 compatible = "regulator-fixed";
0371 regulator-name = "v5.0-sata3";
0372 regulator-min-microvolt = <5000000>;
0373 regulator-max-microvolt = <5000000>;
0374 vin-supply = <®_sata3>;
0375 };
0376
0377 reg_12v_sata3: v12-sata3 {
0378 compatible = "regulator-fixed";
0379 regulator-name = "v12.0-sata3";
0380 regulator-min-microvolt = <12000000>;
0381 regulator-max-microvolt = <12000000>;
0382 vin-supply = <®_sata3>;
0383 };
0384 };
0385
0386 &pinctrl {
0387 pca0_pins: pca0_pins {
0388 marvell,pins = "mpp18";
0389 marvell,function = "gpio";
0390 };
0391 };
0392
0393 &spi0 {
0394 pinctrl-names = "default";
0395 pinctrl-0 = <&spi0_pins>;
0396 status = "okay";
0397
0398 flash@0 {
0399 #address-cells = <1>;
0400 #size-cells = <1>;
0401 compatible = "st,m25p128", "jedec,spi-nor";
0402 reg = <0>; /* Chip select 0 */
0403 spi-max-frequency = <50000000>;
0404 m25p,fast-read;
0405 };
0406 };
